IS64LP12832
IS64LP12836, IS64LP25618
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. 00A
01/20/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Interleaved or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin TQFP and
119-pin PBGA package
Power-down snooze mode
Power Supply
+ 3.3V V
DD
+ 3.3V OR 2.5V V
DDQ
(I/O)
Temperature offerings
Option A1: -40
0
C to +85
0
C
Option A2: -40
0
C to +105
0
C
Option A3: -40
0
C to +125
0
C
DESCRIPTION
The
ISSI
IS64LP12832, IS64LP12836, and IS64LP25618
are high-speed synchronous static RAMs designed to
provide high-performance memory with burst for high-
speed networking and communication applications.
IS64LP12832 is organized as 131,072 words by 32 bits.
IS64LP12836 is organized as 131,072 words by 36 bits.
IS64LP25618 is organized as 262,144 words by 18 bits. The
IS64LP12832, IS64LP12836, and IS64LP25618 are fabri-
cated with
ISSI
's advanced CMOS technology. These
devices integrate a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls
DQc,
BW4
controls DQd, conditioned by
BWE
being
LOW. A LOW on
GW
input would cause all bytes to be
written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
ADVANCED INFORMATION
JANUARY 2003
FAST ACCESS TIME
Symbol
Parameter
-166
-150
Units
t
KQ
Clock Access Time
3.5
3.8
ns
t
KC
Cycle Time
6
6.7
ns
Frequency
166
150
MHz
128K x 32, 128K x 36, 256K x 18
SYNCHRONOUS
PIPELINED STATIC RAM
IS64LP12832
IS64LP12836, IS64LP25618
ISSI
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
01/20/03
BLOCK DIAGRAM
17/18
BINARY
COUNTER
BW1
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
16/17
18/19
ADDRESS
REGISTER
CE
D
CLK
Q
DQd
BYTE WRITE
REGISTERS
D
CLK
Q
DQc
BYTE WRITE
REGISTERS
D
CLK
Q
DQb
BYTE WRITE
REGISTERS
D
CLK
Q
DQa
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BW4
CE
CE2
CE2
BW2
BW3
128K x 32/128K x 36,
256K x 18
MEMORY ARRAY
32 or 36
or 18
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
32 or 36
or 18
OE
4
OE
DQ
a-d
(x32/ x36)
(x32/ x36)
(x32/ x36/ x18)
(x32/ x36/ x18)
32 or 36
or 18
A
Integrated Silicon Solution, Inc. -- 1-800-379-4774 3
Rev. 00A
01/20/03
IS64LP12832
IS64LP12836, IS64LP25618
ISSI
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Ad-
vance
BW1
-
BW4
Individual Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE
,
CE2
, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
DD
+3.3V Power Supply
GND
Ground
V
DDQ
Isolated Output Buffer Supply: +3.3V
or 2.5V
ZZ
Snooze Enable
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
DQc1
1
DQc2
2
VDDQ
DQc5
5
DQc7
7
VDDQ
DQd1
1
DQd4
4
VDDQ
DQd6
6
DQd8
8
NC
NC
VDDQ
A6
6
CE2
A7
7
NC
DQc3
3
DQc4
4
DQc6
6
DQc8
8
VDD
DQd2
2
DQd3
3
DQd5
5
DQd7
7
NC
A5
NC
NC
A4
4
A3
3
A2
2
GND
GND
GND
BW3
GND
NC
GND
BW4
GND
GND
GND
MODE
A10
10
NC
ADSP
ADSC
VDD
NC
CE
OE
ADV
GW
VDD
CLK
NC
BWE
A1
A0
VDD
A11
11
NC
A8
8
A9
9
A12
12
GND
GND
GND
BW2
GND
NC
GND
BW1
GND
GND
GND
NC
A14
14
NC
A16
16
CE2
A15
15
NC
DQb6
6
DQb5
5
DQb4
4
DQb2
2
VDD
DQa7
7
DQa5
5
DQa4
4
DQa3
3
NC
A13
13
NC
NC
VDDQ
NC
NC
DQb8
8
DQb7
7
VDDQ
DQb3
3
DQb1
1
VDDQ
DQa8
8
DQa6
6
VDDQ
DQa2
2
DQa1
1
NC
ZZ
VDDQ
1
2
3
4
5
6
7
NC
DQb
DQb
VDDQ
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
NC
A
A
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
GND
CLK
GW
BWE
OE
ADS
C
ADSP
ADV
A
A
NC
DQc
DQc
VDDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
DQc
DQc
NC
VDD
NC
GND
DQd
DQd
VDDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
128K x 32
119-pin PBGA (Top View) 100-Pin TQFP
IS64LP12832
IS64LP12836, IS64LP25618
ISSI
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A
01/20/03
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BW1
-
BW4
Individual Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE
,
CE2
, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
DD
+3.3V Power Supply
GND
Ground
V
DDQ
Isolated Output Buffer Supply: +3.3V or
2.5V
ZZ
Snooze Enable
DQPa-DQPd
Parity Data I/O
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
DQc1
1
DQc2
2
VDDQ
DQc5
5
DQc7
7
VDDQ
DQd1
1
DQd4
4
VDDQ
DQd6
6
DQd8
8
NC
NC
VDDQ
A6
6
CE2
A7
7
DQPc
DQc3
3
DQc4
4
DQc6
6
DQc8
8
VDD
DQd2
2
DQd3
3
DQd5
5
DQd7
7
DQPd
A5
5
NC
NC
A4
4
A3
3
A2
2
GND
GND
GND
BW3
GND
NC
GND
BW4
GND
GND
GND
MODE
A10
10
NC
ADSP
ADSC
VDD
NC
CE
OE
ADV
GW
VDD
CLK
NC
BWE
A1
A0
VDD
A11
11
NC
A8
8
A9
9
A12
12
GND
GND
GND
BW2
GND
NC
GND
BW1
GND
GND
GND
NC
A14
14
NC
A16
16
CE2
A15
15
DQPb
DQb6
6
DQb5
5
DQb4
4
DQb2
2
VDD
DQa7
7
DQa5
5
DQa4
4
DQa3
3
DQPa
A13
13
NC
NC
VDDQ
NC
NC
DQb8
8
DQb7
7
VDDQ
DQb3
3
DQb1
1
VDDQ
DQa8
8
DQa6
6
VDDQ
DQa2
2
DQa1
1
NC
ZZ
VDDQ
1
2
3
4
5
6
7
DQPb
DQb
DQb
VDDQ
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
DQPa
A
A
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
GND
CLK
GW
BWE
OE
ADS
C
ADSP
ADV
A
A
DQPc
DQc
DQc
VDDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
DQc
DQc
NC
VDD
NC
GND
DQd
DQd
VDDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
128K x 36
119-pin PBGA (Top View)
100-Pin TQFP
Integrated Silicon Solution, Inc. -- 1-800-379-4774 5
Rev. 00A
01/20/03
IS64LP12832
IS64LP12836, IS64LP25618
ISSI
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BW1
-
BW2
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE
, CE2,
CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQb
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
DD
+3.3V Power Supply
GND
Ground
V
DDQ
Isolated Output Buffer Supply: +3.3V
ZZ
Snooze Enable
DQPa-DQPb
Parity Data I/O
A
NC
NC
VDDQ
GND
NC
DQPa
DQa
DQa
GND
VDDQ
DQa
DQa
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
NC
NC
GND
VDDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BW2
BW1
CE2
VDD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
VDDQ
GND
NC
NC
DQb
DQb
GND
VDDQ
DQb
DQb
NC
VDD
NC
GND
DQb
DQb
VDDQ
GND
DQb
DQb
DQPb
NC
GND
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
DQb
NC
VDDQ
NC
DQb
VDDQ
NC
DQb
VDDQ
DQb
NC
NC
NC
VDDQ
A6
6
CE2
A7
7
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
A
NC
A4
4
A3
3
A2
2
GND
GND
GND
BW2
GND
NC
GND
GND
GND
GND
GND
MODE
A
NC
ADSP
ADSC
VDD
NC
CE
OE
ADV
GW
VDD
CLK
NC
BWE
A1
A0
VDD
NC
NC
A8
8
A9
9
A12
12
GND
GND
GND
GND
GND
NC
GND
BW1
GND
GND
GND
GND
A
NC
A16
16
CE2
A15
15
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
1
2
3
4
5
6
7
256K x 18
119-pin PBGA (Top View)
100-Pin TQFP
PIN CONFIGURATION
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