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Электронный компонент: IS64LV6416L-10TA1

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IS64LV6416L
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. C
05/02/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
ISSI
FEATURES
High-speed access time: 10, 12 ns
CMOS low power operation:
250 mW (typical) operating
250 W (typical) standby
TTL compatible interface levels
Single 3.3V power supply
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Temperature offerings:
Option A1: 40
o
C to +85
o
C
Option A2: 40
o
C to +105
o
C
Option A3: 40
o
C to +125
o
C
DESCRIPTION
The
ISSI
IS64LV6416L is a high-speed, 1,048,576-bit
static RAM organized as 65,536 words by 16 bits. It is
fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 10 ns with low power consumption.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs,
CE
and
OE
. The active
LOW Write Enable (
WE
) controls both writing and reading
of the memory. A data byte allows Upper Byte (
UB
) and
Lower Byte (
LB
) access.
The IS64LV6416L is packaged in the JEDEC standard
44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
MAY 2003
A0-A15
CE
OE
WE
64K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
64K x 16 HIGH-SPEED CMOS STATIC
RAM WITH 3.3V SUPPLY
IS64LV6416L
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
05/02/03
ISSI
PIN CONFIGURATIONS
44-Pin TSOP-II (T)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
V
DD
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V
DD
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
48-Pin mini BGA (6mm x 8mm) (B)
PIN DESCRIPTIONS
A0-A15
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
V
DD
Power
GND
Ground
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
NC
I/O
8
UB
A3
A4
CE
I/O
0
I/O
9
I/O
10
A5
A6
I/O
1
I/O
2
GND
I/O
11
NC
A7
I/O
3
V
DD
V
DD
I/O
12
NC
NC
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
NC
A8
A9
A10
A11
NC
IS64LV6416L
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. C
05/02/03
1
2
3
4
5
6
7
8
9
10
11
12
ISSI
OPERATING RANGE
Options
Ambient Temperature
V
DD
A1
40C to +85C
3.3V 10%
A2
40C to +105C
3.3V 10%
A3
40C to +125C
3.3V 10%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
Parameter
Test Conditions
Options
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 8.0 mA
A1, A2
--
0.4
V
A3
--
0.5
V
V
IH
Input HIGH Voltage
2
V
DD
+ 0.3
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
DD
2
2
A
I
LO
Output Leakage
GND
V
OUT
V
DD
, Outputs Disabled
2
2
A
Notes:
1. V
IL
(min.) = 2.0V for pulse width less than 10 ns.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to V
DD
+0.5
V
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.5
W
I
OUT
DC Output Current (LOW)
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
TRUTH TABLE
I/O PIN
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
LB
LB
LB
LB
LB
UB
UB
UB
UB
UB
I/O0-I/O7
I/O8-I/O15
V
DD
Current
Not Selected
X
H
X
X
X
High-Z
High-Z
I
SB
1
, I
SB
2
Output Disabled
H
L
H
X
X
High-Z
High-Z
I
CC
X
L
X
H
H
High-Z
High-Z
Read
H
L
L
L
H
D
OUT
High-Z
I
CC
H
L
L
H
L
High-Z
D
OUT
H
L
L
L
L
D
OUT
D
OUT
Write
L
L
X
L
H
D
IN
High-Z
I
CC
L
L
X
H
L
High-Z
D
IN
L
L
X
L
L
D
IN
D
IN
IS64LV6416L
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
05/02/03
ISSI
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-10 ns -12 ns
Symbol Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
I
CC
V
DD
Dynamic Operating
V
DD
= Max.,
A1
--
95
--
--
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
A2
--
--
--
105
A3
--
--
--
115
I
SB
1
TTL Standby Current
V
DD
= Max.,
A1
--
15
--
--
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
A2
--
--
--
18
CE
V
IH
, f = 0
A3
--
--
--
20
I
SB
2
CMOS Standby
V
DD
= Max.,
A1
--
2
--
--
mA
Current (CMOS Inputs)
CE
V
DD
0.2V,
A2
--
--
--
3
V
IN
V
DD
0.2V, or
A3
--
--
--
5
V
IN
0.2V, f = 0
typ
(2)
--
0.5
--
0.5
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
= 3.3V, T
A
= 25
o
C and not 100% tested.
IS64LV6416L
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. C
05/02/03
1
2
3
4
5
6
7
8
9
10
11
12
ISSI
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-10 ns
-12 ns
Symbol
Parameter
Min. Max.
Min. Max.
Unit
t
RC
Read Cycle Time
10
--
12
--
ns
t
AA
Address Access Time
--
10
--
12
ns
t
OHA
Output Hold Time
3
--
3
--
ns
t
ACE
CE
Access Time
--
10
--
12
ns
t
DOE
OE
Access Time
--
5
--
6
ns
t
HZOE
(2)
OE
to High-Z Output
--
5
--
6
ns
t
LZOE
(2)
OE
to Low-Z Output
0
--
0
--
ns
t
HZCE
(2
CE
to High-Z Output
0
5
0
6
ns
t
LZCE
(2)
CE
to Low-Z Output
3
--
3
--
ns
t
BA
LB
,
UB
Access Time
--
6
--
6
ns
t
HZB
LB
,
UB
to High-Z Output
0
5
0
6
ns
t
LZB
LB
,
UB
to Low-Z Output
0
--
0
--
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1a and 1b
AC TEST LOADS
Figure 1a. Figure 1b.
319
30 pF
Including
jig and
scope
353
OUTPUT
3.3V
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V