IS65WV25616ALL
IS65WV25616BLL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. 00B
06/20/06
Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
256K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC SRAM
FEATURES
High-speed access time: 55ns, 70ns
CMOS low power operation
36 mW (typical) operating
9 W (typical) CMOS standby
TTL compatible interface levels
Single power supply
1.65V--2.2V V
DD
(65WV25616ALL)
2.5V--3.6V V
DD
(65WV25616BLL)
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
TEMPERATURE OFFERINGS:
Option A1: -40C to +85C
Option A2: -40C to +105C
Option A3: -40C to +125C
Lead-free available
DESCRIPTION
The
ISSI
IS65WV25616ALL/IS65WV25616BLL are high-
speed, low power, 4M bit SRAMs organized as 256K words
by 16 bits. It is fabricated using
ISSI
's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When
CS1 is HIGH (deselected) or when CS1 is LOW, and
both
LB and UB are HIGH, the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte
(UB) and Lower Byte (LB)
access.
The IS65WV25616BALL/65WV25616BLL are packaged in
the JEDEC standard 44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
PRELIMINARY INFORMATION
JUNE 2006
A0-A17
CS1
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
25616LL_BLK.eps
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00B
06/20/06
IS65WV25616ALL, IS65WV25616BLL
ISSI
TRUTH TABLE
I/O PIN
Mode
WE
WE
WE
WE
WE
CS1
CS1
CS1
CS1
CS1
OE
OE
OE
OE
OE
LB
LB
LB
LB
LB
UB
UB
UB
UB
UB
I/O0-I/O7
I/O8-I/O15
V
DD
Current
Not Selected
X
H
X
X
X
High-Z
High-Z
I
SB
1
, I
SB
2
X
X
X
X
X
High-Z
High-Z
I
SB
1
, I
SB
2
X
X
X
H
H
High-Z
High-Z
I
SB
1
, I
SB
2
Output Disabled
H
L
H
L
X
High-Z
High-Z
I
CC
H
L
H
X
L
High-Z
High-Z
I
CC
Read
H
L
L
L
H
D
OUT
High-Z
I
CC
H
L
L
H
L
High-Z
D
OUT
H
L
L
L
L
D
OUT
D
OUT
Write
L
L
X
L
H
D
IN
High-Z
I
CC
L
L
X
H
L
High-Z
D
IN
L
L
X
L
L
D
IN
D
IN
PIN DESCRIPTIONS
A0-A17
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CS1
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
V
DD
Power
GND
Ground
44-Pin mini TSOP (Type II)
(Package Code T)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
V
DD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V
DD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17
25616T.eps
IS65WV25616ALL, IS65WV25616BLL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. 00B
06/20/06
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
V
DD
Min.
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= -0.1 mA
1.65-2.2V
1.4
--
V
I
OH
= -1 mA
2.5-3.6V
2.2
--
V
V
OL
Output LOW Voltage
I
OL
= 0.1 mA
1.65-2.2V
--
0.2
V
I
OL
= 2.1 mA
2.5-3.6V
--
0.4
V
V
IH
Input HIGH Voltage
1.65-2.2V
1.4
V
DD
+ 0.2
V
2.5-3.6V
2.2
V
DD
+ 0.3
V
V
IL
(1)
Input LOW Voltage
1.65-2.2V
0.2
0.4
V
2.5-3.6V
0.2
0.6
V
I
LI
Input Leakage
GND
V
IN
V
DD
2
2
A
I
LO
Output Leakage
GND
V
OUT
V
DD
, Outputs Disabled
2
2
A
Notes:
1. V
IL
(min.) = 1.0V for pulse width less than 10 ns.
OPERATING RANGE (V
DD
)
Range
Ambient Temperature
IS65WV25616ALL
IS65WV25616BLL
A1
-40C to +85C
1.65V - 2.2V
2.5V-3.6V
A2
40C to +105C
1.65V - 2.2V
2.5V-3.6V
A3
40C to +125C
1.65V - 2.2V
2.5V-3.6V
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.2 to V
DD
+0.3
V
V
DD
V
DD
Related to GND
0.2 to V
DD
+0.3
V
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00B
06/20/06
IS65WV25616ALL, IS65WV25616BLL
ISSI
IS65WV25616ALL, POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Test Conditions
Max.
Unit
70
I
CC
V
DD
Dynamic Operating
V
DD
= Max.,
A1
25
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
A2, A3
30
I
CC
1
Operating Supply
V
DD
= Max.,
CS1 = 0.2V
A1
10
mA
Current
WE = V
DD
-0.2V
A2, A3
15
f=1
MHZ
I
SB
1
TTL Standby Current
V
DD
= Max.,
A1
0.5
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
A2, A3
0.6
CS1 = V
IH
, f = 1 MH
Z
OR
ULB Control
V
DD
= Max., V
IN
= V
IH
or V
IL
CS1 = V
IL
, f = 0,
UB = V
IH
,
LB = V
IH
I
SB
2
CMOS Standby
V
DD
= Max.,
A1
15
A
Current (CMOS Inputs)
CS1
V
DD
0.2V,
A2
30
V
IN
V
DD
0.2V, or A3
50
V
IN
0.2V, f = 0
OR
ULB Control
V
DD
= Max.,
CS1 = V
IL
,
V
IN
0.2V, f = 0; UB / LB = V
DD
0.2V
IS65WV25616BLL, POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Test Conditions
Max.
Max.
Unit
55
70
I
CC
Vdd Dynamic Operating
V
DD
= Max.,
A1
40
--
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
A2, A3
--
40
I
CC
1
Operating Supply
V
DD
= Max.,
CS1 = 0.2V
A1
15
--
mA
Current
WE = V
DD
-0.2V,
A2, A3
--
20
f=1
MHZ
I
SB
1
TTL Standby Current
V
DD
= Max.,
A1
0.45
--
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
A2, A3
--
0.45
CS1 = V
IH
, f = 1 MH
Z
OR
ULB Control
V
DD
= Max., V
IN
= V
IH
or V
IL
CS1 = V
IL
, f = 0,
UB = V
IH
,
LB = V
IH
I
SB
2
CMOS Standby
V
DD
= Max.,
A1
20
--
A
Current (CMOS Inputs)
CS1
V
DD
0.2V,
A2
--
55
V
IN
V
DD
0.2V, or A3
--
90
V
IN
0.2V, f = 0
OR
ULB Control
V
DD
= Max.,
CS1 = V
IL
,
V
IN
0.2V, f = 0; UB / LB = V
DD
0.2V
IS65WV25616ALL, IS65WV25616BLL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. 00B
06/20/06
AC TEST CONDITIONS
IS65WV25616ALL
IS65WV25616BLL
Parameter
(Unit)
(Unit)
Input Pulse Level
0.4V to V
DD
-0.2V
0.4V to V
DD
-0.3V
Input Rise and Fall Times
5 ns
5ns
Input and Output Timing
V
REF
V
REF
and Reference Level
Output Load
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
Figure 1
Figure 2
IS65WV25616ALL
IS65WV25616BLL
1.65V-2.2V
2.5V - 3.6V
R1(
)
)
)
)
)
3070
3070
R2(
)
)
)
)
)
3150
3150
V
REF
0.9V
1.5V
V
TM
1.8V
2.8V
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
R1
30 pF
Including
jig and
scope
R2
OUTPUT
VTM
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
8
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
10
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
62WV5126ALL tst1a.eps
25616l_tst1c.eps
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