Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
PRELIMINARY INFORMATION
Rev. 00A
10/21/02
ISSI
Copyright 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IS71V08F32ESx08
IS71V16F32ESx08
3.0 Volt-Only Flash & SRAM COMBO with
Stacked Multi-Chip Package (MCP) --
32 Mbit Simultaneous Operation Flash
Memory and 8 Mbit Static RAM
PRELIMINARY INFORMATION
OCTOBER 2002
MCP FEATURES
Power supply voltage 2.7V to 3.3V
High performance:
Flash: 70ns maximum access time
SRAM: 70ns maximum access time
Package: 73-ball BGA
Operating Temperature: -40C to +85C
FLASH FEATURES
Power Dissipation:
Read Current at 1 Mhz: 4 mA maximum
Read Current at 5 Mhz: 18 mA maximum
Sleep Mode: 5
A maximum
Simultaneous Read and Write Operations:
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
Low-Power Mode:
A period of no activity causes flash to enter a
low-power state
Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank
Sector Erase Architecture:
8 sectors of 4k words each and 63 sectors of 32K words
each in Word Mode, or 8 sectors of 8k bytes each and 63
sectors of 64K bytes each in Byte Mode
Erase Algorithms:
Automatically preprograms/erases the flash memory
entirely, or by sector
Program Algorithms:
Automatically writes and verifies data at specified
address
Hidden ROM Region:
256 byte with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
Data Polling and Toggle Bit:
Allow for detection of program or erase cycle comple-
tion
Ready-Busy output (RY/
BY
):
Detection
of program or erase cycle completion
Over 100,000 write/erase cycles
Low supply voltage (Vccf
2.5V) inhibits writes
WP
/ACC input pin:
If V
IL
, allows protection of boot sectors
If V
IH
, allows removal of boot sector protection
If Vacc, program time is reduced by 40%
Boot sector: Top or Bottom
SRAM FEATURES (8 Mb density)
Power Dissipation:
Operating: 25 mA maximum
Standby: 15 A maximum
Chip Selects:
CE1
s, CE2s
Power down feature using
CE1s
, or CE2s
Data retention supply voltage: 1.2 to 3.3 volt
Byte data control:
LB
s (DQ0DQ7),
UB
s
(DQ8DQ15) -- in x16 version
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
10/21/02
IS71V08F32ES
X
08
IS71V16F32ESx08
ISSI
GENERAL DESCRIPTION
The flash and SRAM MCP is a 32 Mbit Flash/8 Mbit SRAM data bus. The 32 Mbit flash is composed of 2,097,152 words
of 16 bits or 4,194,304 bytes of 8 bits. The SRAM has 524,288 words of 16 bits or 1,048,576 bytes of 8 bits. The Flash
memory in Word mode (or x16 version of SRAM) is accessed with data lines DQ0-DQ15. The Flash memory in Byte mode
( or x8 version of SRAM) is accessed by data lines DQ0 - DQ7. Single byte SRAM data access can be accomplished by
using
LB
s or
UB
s, and DQ0 - DQ7 or DQ8-DQ15, respectively.
The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations.
The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM
programmer.
The 32 Mbit flash/8 Mbit SRAM is offered in a 73-pin BGA package. The flash is compatible with the JEDEC Flash
command set standard . The flash access time is 70ns and the SRAM access time is 70ns.
The Flash architecture is composed of two virtual banks which allows simultaneous operation on each. Optimized
performance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read
from the other bank. Both operations would then be operating simultaneously, with zero latency.
MCP BLOCK DIAGRAM
GND
GND
V
CCf
RY/
BY
8-MBIT
Static RAM
32-MBIT
Flash Memory
DQ0-DQ15/A-1
A0-A20
A0-A20
A-1
WP
/ACC
RESET
CE
f
I/Of
LB
s
UB
s
WE
OE
CE1
s
CE2s
DQ0-DQ15
A0-A18
V
CCS
SA
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
PRELIMINARY INFORMATION
Rev. 00A
10/21/02
IS71V08F32ES
X
08
IS71V16F32ESx08
ISSI
LOGIC SYMBOL
A0-A20, A-1
CE
f
CE1
s
CE2s
OE
WE
WP
/ACC
RESET
UB
s
LB
s
I/Of
DQ0-DQ15
22
16 or 8
RY/
BY
SA
FLASH MEMORY BLOCK DIAGRAM
STATE CONTROL
&
COMMAND REGISTER
RESET
WE
CE
I/of
WP
/ACC
DQ0-DQ15
A0-A20
A0-A20
A0-A20
A0-A20
A0-A20
Lower Bank Address
Upper Bank Address
Y -Decoder
Latches and
Control Logic
Lower
Bank
Upper
Bank
X-Decoder
Y -Decoder
Latches and
Control Logic
X-Decoder
Status
Control
DQ0-DQ15
DQ0-DQ15
DQ0-DQ15
OE
I/of
OE
I/of
V
CC
GND
RY/
BY
Organization Type
Bank 1 Size
Bank 2 Size
Boot Block
Part Number
Dual Bank
8Mb
24Mb
Top
IS71V16F32EST08
Dual Bank
8Mb
24Mb
Bottom
IS71V16F32ESB08
FLASH BANK ORGANIZATION
Note:
For complete device part number, see Part Number Logic Diagram or ordering information
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
10/21/02
IS71V08F32ES
X
08
IS71V16F32ESx08
ISSI
PIN DESCRIPTIONS
A0-A18
Address Inputs, Common
A19- A20, A-1
Address Inputs, Flash
DQ0-DQ15/A-1
Data Inputs/Outputs, Common
RESET
Reset
CE1
s, CE2s
Chip Enable, SRAM
I/Of
I/O Configuration, Flash
CE
f
Chip Enable, Flash
OE
Output Enable, Common
WE
Write Enable, Common
LB
s
Lower-byte Control, SRAM
UB
s
Upper-byte Control, SRAM
WP
/ACC
Write Protect/Acceleration Pin, Flash
RY/
BY
Ready/Busy Output (Flash)
SA
High Order Address Pin, SRAM
(x8 version only)
NC
No Connection
Vccf
Power, Flash
Vccs
Power, SRAM
GND
Ground, Common
PIN CONFIGURATION (32 Mb Flash and 8 Mb SRAM)
PACKAGE CODE: B 73 BALL FBGA (Top View) (8.00 mm x 11.60 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
L
M
NC
NC
NC
NC
NC
NC
NC
A3
A2
A1
A0
CEf
CE1S
A7
A6
A5
A4
GND
OE
DQ0
DQ8
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
NC
WP/
ACC
RESET
RY/
BY
DQ3
Vccf
DQ11
NC
NC
WE
CE2s
A20
DQ4
VccS
NC
NC
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
A11
A12
A13
A14
SA
DQ15*
DQ7
DQ14
A15
NC
NC
A16
I/Of
GND
NC
NC
NC
NC
NC
NC
Shared
Flash Only
SRAM Only
*
DQ15/A-1
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
PRELIMINARY INFORMATION
Rev. 00A
10/21/02
IS71V08F32ES
X
08
IS71V16F32ESx08
ISSI
OPERATION
(1,3)
CE
CE
CE
CE
CE
f
CE
CE
CE
CE
CE
1s CE2s
OE
OE
OE
OE
OE
WE
WE
WE
WE
WE
SA
(6)
LB
LB
LB
LB
LB
s
UB
UB
UB
UB
UB
s
DQ
0-
DQ
7
DQ
8
-DQ
15
RESET
RESET
RESET
RESET
RESET WP
WP
WP
WP
WP
/ACC
(5)
Full Standby
H
H
X
X
X
X
X
X
High-Z
High-Z
H
X
H
X
L
X
X
X
X
X
High-Z
High-Z
H
X
Output Disable
H
L
H
H
H
X
X
X
High-Z
High-Z
H
X
H
L
H
X
X
X
H
H
High-Z
High-Z
H
X
L
H
X
H
H
X
X
X
High-Z
High-Z
H
X
L
X
L
H
H
X
X
X
High-Z
High-Z
H
X
Read from Flash
(2)
L
H
X
L
H
X
X
X
D
OUT
D
OUT
H
X
L
X
L
L
H
X
X
X
D
OUT
D
OUT
H
X
Write to Flash
L
H
X
H
L
X
X
X
D
IN
D
IN
H
X
L
X
L
H
L
X
X
X
D
IN
D
IN
H
X
Read from SRAM
H
L
H
L
H
X
L
L
D
OUT
D
OUT
H
X
H
L
H
L
H
X
H
L
High-Z
D
OUT
H
X
H
L
H
L
H
X
L
H
D
OUT
High-Z
H
X
Write to SRAM
H
L
H
X
L
X
L
L
D
IN
D
IN
H
X
H
L
H
X
L
X
H
L
High-Z
D
IN
H
X
H
L
H
X
L
X
L
H
D
IN
High-Z
H
X
Temporary Sector
X
X
X
X
X
X
X
X
X
X
V
ID
(8)
X
Group Unprotection
(4)
Flash Hardware
X
H
X
X
X
X
X
X
High-Z
High-Z
L
X
Reset
X
X
L
X
X
X
X
X
High-Z
High-Z
L
X
Boot Block Sector
X
X
X
X
X
X
X
X
X
X
X
L
Write Protection
Notes:
1. Any operations not indicated this column are inhibited.
2.
WE
can be VIL if
OE
is VIL,
OE
at VIH initiates the write operations.
3. Do not apply
CE
f = VIL,
CE
1s = VIL and CE2s = VIH all at once.
4. It is also used for the extended sector group protections.
5.
WP
/ACC = VIL: protection of boot sectors.
WP
/ACC = VIH: removal of boot sectors protection.
WP
/ACC = VACC (9V): Program time will reduce by 40%.
6. SA: Don't care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
8. See DC CHARACTERISTICS.
DEVICE BUS OPERATIONS (IS71V16F32ESx08)
User Bus Operations (Flash=Word mode: I/Of = Vccf, SRAM = x16 Version)
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