Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
PRELIMINARY INFORMATION
Rev. 00A
08/01/02
75V16F64GS16
ISSI
Copyright 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark
of Fujitsu Limited, Japan. Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc
64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM
STACKED MULTI-CHIP PACKAGE (MCP)
PRELIMINARY INFORMATION
AUGUST 2002
MCP FEATURES
Power supply voltage of 2.7 to 3.1 volt
High performance:
-
Flash access time as fast as 70 ns
- PSRAM access time as fast as 80 ns
Package: 65-Ball FBGA
Operating Temperature: 30C to +85C
FLASH MEMORY FEATURES
0.16 m Process Technology
Simultaneous Read/Write Operations (Dual Bank)
FlexBank
TM
architecture
- Bank A : 8 Mbit ( 8 KB x 8 and 64 KB x 15)
- Bank B : 24 Mbit (64 KB x 48)
- Bank C : 24 Mbit (64 KB x 48)
- Bank D : 8 Mbit ( 8 KB x 8 and 64 KB x 15)
- Two virtual Banks are chosen from the combination
of four physical banks (Refer to "Example of Virtual
Banks Combination Table" and Simultaneous
Operation Table" in FLEXIBLE SECTOR-ERASE
ARCHITECTURE on FLASH MEMORY)
- Host system can program or erase in one bank, and
then read immediately and simultaneously from the
other bank with zero latency between read and write
operations.
- Read-while-erase
- Read-while-program
Single 3.0 V Read, Program, and Erase
- Minimized system level power requirements
Minimum 100,000 Program/Erase Cycles
Sector Erase Architecture
- Sixteen 4 Kword and one hundred twenty-six 32
Kword sectors in word
- Any combination of sectors can be concurrently
erased
- Supports full chip erase
Hidden ROM (Hi-ROM) Region
- 256 byte of Hi-ROM, accessible through a new "HI-
ROM Enable" command sequence
- Factory serialized and protected to provide a secure
electronic serial number (ESN)
WP
/ACC Input Pin
- At V
IL
, allows protection of "outermost" 2
8 Kbytes
on both ends of boot sectors, regardless of sector
protection/unprotection status
- At V
IH
, allows removal of boot sector protection
- At V
ACC
, program time will be reduced by 40 %
Embedded Erase
TM
Algorithms
- Automatically preprograms and erases the chip
or any sector
Embedded Program
TM
Algorithms
- Automatically writes and verifies data at specified
address
Data Polling and Toggle Bit Feature for Detection of
Program or Erase Cycle Completion
Ready/Busy Output (RY/
BY
)
- Hardware method for detection of program or
erase cycle completion
Automatic Sleep Mode
- When addresses remain stable, the device
automatically switches itself to low power mode.
Low V
CC
f Write Inhibit
2.5 V
Program Suspend/Resume
- Suspends the program operation to allow a read
in another byte
Erase Suspend/Resume
- Suspends the erase operation to allow a read
data and/or program in another sector within the
same device
PSRAM FEATURES
Power Dissipation:
- Operating : 20 mA Max
- Standby : 70 A Max
- Power Down
: 10 A Max
Power down Control by CE2r
Byte Write Control :
LB
(DQ
7
-DQ
0
),
UB
(DQ
15
-DQ
8
)
4 words Address Access Capability
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
08/01/02
75V16F64GS16
ISSI
PIN DESCRIPTIONS
A0-A19
Address Inputs, Common
A20-A21
Address Inputs, Flash
DQ0-DQ15 Data Inputs/Outputs, Common
RESET
Hardware Reset Pin/Acceleration, Flash
CE1
r,CE2r Chip Enable, PSRAM
RY/
BY
Ready/Busy Output, Flash Open Drain Output
CE
f
Chip Enable, Flash
OE
Output Enable, Common
WE
Write Enable, Common
LB
Lower-byte Control, PSRAM
UB
Upper-byte Control, PSRAM
WP
/ACC
Write Protect/Acceleration, Flash
RY/
BY
Ready/Busy Output
NC
No Internal Connection
Vccf
Device Power Supply, Flash
GND
Device Ground, Common
Vccr
Device Power, PSRAM
PIN CONFIGURATION (64 Mb Flash and 16 Mb PSRAM)
PACKAGE CODE: D 65 BALL FBGA (Top View) (9.00 mm x 9.00 mm Body, 0.8 mm Ball Pitch)
A B C D E F G H J K
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
A11
A8
WE
WP
/ACC
LB
A7
NC
A15
A12
A19
CE2r
RESET
UB
A6
A3
A21
A13
A9
A20
RY/
BY
A18
A5
A2
NC
A14
A10
A17
A4
A16
NC
DQ6
DQ1
GND
A0
Vccf
DQ15
DQ13
DQ4
DQ3
DQ9
OE
CE
f
GND
DQ7
DQ12
Vccr
Vccf
DQ10
DQ0
CE
1r
DQ14
DQ5
NC
DQ11
DQ2
DQ8
NC
NC
NC
NC
Common
Flash Only
PSRAM Only
A1
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
PRELIMINARY INFORMATION
Rev. 00A
08/01/02
75V16F64GS16
ISSI
Full Standby
H
H
H
X
X
X
X
High-Z
High-Z
H
X
Output Disable
(3)
H
L
X
H
H
X
X
High-Z
High-Z
H
X
L
H
X
H
H
X
X
High-Z
High-Z
H
X
Read from Flash
(4)
L
H
X
L
H
X
X
D
OUT
D
OUT
H
X
Write to Flash
L
H
X
H
L
X
X
D
IN
D
IN
H
X
Read from PSRAM
(5)
H
L
H
L
H
X
X
D
OUT
D
OUT
H
X
Write to PSRAM
L
L
D
IN
D
IN
H
L
H
H
L
H
L
High-Z
D
IN
H
X
L
H
D
IN
High-Z
Temporary
Sector
X
X
X
X
X
X
X
X
X
V
ID
X
Group Unprotection
(6)
Flash Hardware
X
H
H
X
X
X
X
High-Z
High-Z
L
X
Reset
Boot Block
Sector Write
X
X
X
X
X
X
X
X
X
X
L
Protection
PSRAM Power Down
(8)
X
X
L
X
X
X
X
X
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See "DC CHARACTERISTICS" for voltage levels.
Notes:
1. Other operations not indicated in this table are prohibited.
2. Do not apply
CE
f = VIL,
CE
1r = VIL and CE2r = VIH all at once.
3. PSRAM Output Disable condition should not be kept longer than 1 ms.
4.
WE
can be VIL if
OE
is VIL,
OE
at VIH initiates the write operations.
5. PSRAM Byte control at Read operation is not supported.
6. Also used for the extended sector group protections.
7. Protects "outermost" 2 8 Kbytes (4 words) on both ends of the boot block sectors.
8. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
DEVICE BUS OPERATIONS
OPERATION
(1,2)
CE
CE
CE
CE
CE
f
CE1
CE1
CE1
CE1
CE1
r
CE2r
OE
OE
OE
OE
OE
WE
WE
WE
WE
WE
LB
LB
LB
LB
LB
s
UB
UB
UB
UB
UB
s
DQ
7-
DQ
0
DQ
15
-DQ
8
RESET
RESET
RESET
RESET
RESET WP
WP
WP
WP
WP
/ACC
(7)
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