Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00B
12/14/05

IS42R32200C1

ISSI

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

· Clock frequency: 133, 100 MHz

· Fully synchronous; all signals referenced to a

positive clock edge

· Internal bank for hiding row access/precharge

· Single 2.5V power supply

· LVTTL interface

· Programmable burst length:

(1, 2, 4, 8, full page)

· Programmable burst sequence:

Sequential/Interleave

· Self refresh modes

· 4096 refresh cycles every 64 ms

· Random column address every clock cycle

· Programmable

CAS latency (2, 3 clocks)

· Burst read/write and burst read/single write

operations capability

· Burst termination by burst stop and precharge

command

· Industrial temperature availability

· Package 400-mil 86-pin TSOP II

· Lead free package is available

OVERVIEW
ISSI

's 64Mb Synchronous DRAM IS42R32200C1 is

organized as 524,288 bits x 32-bit x 4-bank for improved
performance. The synchronous DRAMs achieve high-
speed data transfer using pipeline architecture. All inputs
and outputs signals refer to the rising edge of the clock
input.

512K Bits x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM

PRELIMINARY INFORMATION

DECEMBER 2005

PIN CONFIGURATION

(86-Pin TSOP (Type II)

DQ0

DDQ

DQ1

DQ2

GNDQ

DQ3

DQ4

DDQ

DQ5

DQ6

GNDQ

DQ7

DQM0

CAS
RAS

BA0

BA1

A10/AP

DQM2

DQ16

GNDQ

DQ17

DQ18

DDQ

DQ19

DQ20

GNDQ

DQ21

DQ22

DDQ

DQ23

GND

DQ15

GNDQ

DQ14

DQ13

DDQ

DQ12

DQ11

GNDQ

DQ10

DQ9

DDQ

DQ8

GND

DQM1

CLK

CKE

DQM3

GND

DQ31

DDQ

DQ30

DQ29

GNDQ

DQ28

DQ27

DDQ

DQ26

DQ25

GNDQ

DQ24

GND

PIN DESCRIPTIONS

A0-A10

Address Input

BA0, BA1

Bank Select Address

DQ0 to DQ31

Data I/O

CLK

System Clock Input

CKE

Clock Enable

Chip Select

RAS

Row Address Strobe Command

CAS

Column Address Strobe Command

Write Enable

DQM0 to DQM3 Input/Output Mask

Power

GND

Ground

DDQ

Power Supply for DQ Pin

GND

Ground for DQ Pin

No Connection

IS42R32200C1

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00B

12/14/05

GENERAL DESCRIPTION

The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 2.5V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 2,048
rows by 256 columns by 32 bits.

The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.

The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.

A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE

function enabled. Precharge one bank while accessing one
of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.

SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A10 select the row). The READ or
WRITE commands in conjunction with address bits reg-
istered are used to select the starting column location for
the burst access.

Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.

FUNCTIONAL BLOCK DIAGRAM

CLK

CKE

RAS

CAS

A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

BA0
BA1

A10

COMMAND

DECODER

CLOCK

GENERATOR

MODE

REFRESH

CONTROLLER

REFRESH

COUNTER

SELF

REFRESH

CONTROLLER

ROW

ADDRESS

LATCH

MUL

TIPLEXER

COLUMN

ADDRESS LATCH

BURST COUNTER

COLUMN

ADDRESS BUFFER

COLUMN DECODER

DATA IN

BUFFER

DATA OUT

BUFFER

DQM0-3

DQ 0-31

DDQ

GND/GNDQ

256

(x 32)

2048

W DECODER

2048

MEMORY CELL

ARRAY

BANK 0

SENSE AMP I/O GATE

BANK CONTROL LOGIC

ROW

ADDRESS

BUFFER

IS42R32200C1

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1-800-379-4774

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12/14/05

PIN FUNCTIONS

Symbol

Pin No.

Type

Function (In Detail)

A0-A10

25 to 27

Input Pin

Address Inputs: A0-A10 are sampled during the ACTIVE

60 to 66

command (row-address A0-A10) and READ/WRITE command (A0-A7

with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.

BA0, BA1

22,23

Input Pin

Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.

CAS

Input Pin

CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.

CKE

Input Pin

The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode. CKE is an asynchronous input.

CLK

Input Pin

CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.

Input Pin

The

CS input determines whether command input is enabled within the device.

Command input is enabled when

CS is LOW, and disabled with CS is HIGH. The

device remains in the previous state when

CS is HIGH.

DQ0 to

2, 4, 5, 7, 8, 10,11,13

DQ Pin

DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units

DQ31

74,76,77,79,80,82,83,85

using the DQM0-DQM3 pins

45,47,48,50,51,53,54,56

31,33,34,36,37,39,40,42

DQM0

16,28,59,71

Input Pin

DQMx control thel ower and upper bytes of the DQ buffers. In read mode,

DQM3

the output buffers are place in a High-Z state. During a WRITE cycle the input data is
masked. When DQMx is sampled HIGH and is an input mask signal for write accesses
and an output enable signal for read accesses. DQ0 through DQ7 are controlled by
DQM0. DQ8 throughDQ15 are controlled by DQM1. DQ16 through DQ23 are
controlled by DQM2. DQ24 through DQ31 are controlled by DQM3.

RAS

Input Pin

RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.

Input Pin

WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.

DDQ

3,9,35,41,49,55,25,81

Supply Pin

DDQ

is the output buffer power supply.

1,15,29,43

Supply Pin

is the device internal power supply.

GND

6,12,32,38,46,52,78,84

Supply Pin

GND

is the output buffer ground.

GND

44,58,72,86

Supply Pin

GND is the device internal ground.

IS42R32200C1

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1-800-379-4774

Rev. 00B

12/14/05

FUNCTION (In Detail)

A0-A10 are address inputs sampled during the ACTIVE
(row-address A0-A10) and READ/WRITE command (A0-A7
with A10 defining auto PRECHARGE). A10 is sampled during
a PRECHARGE command to determine if all banks are to
be PRECHARGED (A10 HIGH) or bank selected by BA0,
BA1 (LOW). The address inputs also provide the op-code
during a LOAD MODE REGISTER command.

Bank Select Address (BA0 and BA1) defines which bank the
ACTIVE, READ, WRITE or PRECHARGE command is
being applied.
CAS, in conjunction with the RAS and WE, forms the
device command. See the "Command Truth Table" for
details on device commands.

The CKE input determines whether the CLK input is
enabled. The next rising edge of the CLK signal will be
valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down
mode, CLOCK SUSPEND mode, or SELF-REFRESH
mode. CKE is an asynchronous input.

CLK is the master clock input for this device. Except for
CKE, all inputs to this device are acquired in synchroni-
zation with the rising edge of this pin.

The CS input determines whether command input is
enabled within the device. Command input is enabled
when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH. DQ0
through DQ7 are controlled by DQM0. DQ8 through DQ15
are controlled by DQM1. DQ16 through DQ23 are controlled
by DQM2. DQ24 through DQ31 are controlled by DQM3. In
read mode, DQMx control the output buffer. When DQMx is
LOW, the corresponding buffer byte is enabled, and when
HIGH, disabled. The outputs go to the HIGH Impedance
State when DQMx is HIGH. This function corresponds to
OE in conventional DRAMs. In write mode, DQMx control
the input buffer. When DQMx is LOW, the corresponding
buffer byte is enabled, and data can be written to the device.
When DQMx is HIGH, input data is masked and cannot be
written to the device.
RAS, in conjunction with CAS and WE , forms the device
command. See the "Command Truth Table" item for
details on device commands.
WE , in conjunction with RAS and CAS , forms the device
command. See the "Command Truth Table" item for
details on device commands.

DDQ

is the output buffer power supply.

is the device internal power supply.

GND

is the output buffer ground.

GND is the device internal ground.

READ

The READ command selects the bank from BA0, BA1
inputs and starts a burst read access to an active row.
Inputs A0-A7 provides the starting column location. When
A10 is HIGH, this command functions as an AUTO
PRECHARGE command. When the auto precharge is
selected, the row being accessed will be precharged at
the end of the READ burst. The row will remain open for
subsequent accesses when AUTO PRECHARGE is not
selected. DQ's read data is subject to the logic level on
the DQM inputs two clocks earlier. When a given DQM
signal was registered HIGH, the corresponding DQ's will
be High-Z two clocks later. DQ's will provide valid data
when the DQM signal was registered LOW.

WRITE

A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank, and
the starting column location is provided by inputs A0-A7.
Whether or not AUTO-PRECHARGE is used is deter-
mined by A10.

The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.

A memory array is written with corresponding input data
on DQ's and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as "Don't Care". A10 determined
whether one or all banks are precharged. After executing
this command, the next command for the selected banks(s)
is executed after passage of the period t

, which is the

period required for bank precharging. Once a bank has
been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.

AUTO PRECHARGE

The AUTO PRECHARGE function ensures that the
precharge is initiated at the earliest valid stage within a
burst. This function allows for individual-bank precharge
without requiring an explicit command. A10 to enables the
AUTO PRECHARGE function in conjunction with a spe-
cific READ or WRITE command. For each individual
READ or WRITE command, auto precharge is either

IS42R32200C1

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enabled or disabled. AUTO PRECHARGE does not apply
except in full-page burst mode. Upon completion of the
READ or WRITE burst, a precharge of the bank/row that
is addressed is automatically performed.

AUTO REFRESH COMMAND

This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (t

)

is required for a single refresh operation, and no other
commands can be executed during this period. This com-
mand is executed at least 4096 times every 64ms. During
an AUTO REFRESH command, address bits are "Don't
Care". This command corresponds to CBR Auto-refresh.

SELF REFRESH

During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are
generated automatically internally. SELF REFRESH can
be used to retain data in the SDRAM without external
clocking, even if the rest of the system is powered down.
The SELF REFRESH operation is started by dropping the
CKE pin from HIGH to LOW. During the SELF REFRESH
operation all other inputs to the SDRAM become "Don't
Care".The device must remain in self refresh mode for a
minimum period equal to t

RAS

or may remain in self refresh

mode for an indefinite period beyond that.The SELF-
REFRESH operation continues as long as the CKE pin
remains LOW and there is no need for external control of
any other pins.The next command cannot be executed
until the device internal recovery period (t

) has elapsed.

Once CKE goes HIGH, the NOP command must be
issued (minimum of two clocks) to provide time for the
completion of any internal refresh in progress. After the
self-refresh, since it is impossible to determine the ad-
dress of the last row to be refreshed, an AUTO-REFRESH
should immediately be performed for all addresses.

BURST TERMINATE

The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.

COMMAND INHIBIT

COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled

NO OPERATION

When

CS is low, the NOP command prevents unwanted

commands from being registered during idle or wait
states.

LOAD MODE REGISTER

During the LOAD MODE REGSITER command the mode
register is loaded from A0-A10. This command can only
be issued when all banks are idle.

ACTIVE COMMAND

When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A10 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open for
accesses.

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TRUTH TABLE COMMANDS AND DQM OPERATION

(1)

FUNCTION

RAS

CAS

DQM

ADDR

DQs

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

(3)

Bank/Row

READ (Select bank/column, start READ burst)

(4)

L/H

(8)

Bank/Col

WRITE (Select bank/column, start WRITE burst)

(4)

L/H

(8)

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks)

(5)

Code

AUTO REFRESH or SELF REFRESH

(6,7)

(Enter self refresh mode)

LOAD MODE REGISTER

(2)

Op-Code

Write Enable/Output Enable

(8)

Active

Write Inhibit/Output High-Z

(8)

High-Z

NOTES:
1. CKE is HIGH for all commands except SELF REFRESH.
2. A0-A10 define the op-code written to the mode register.
3. A0-A10 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables

auto precharge; BA0, BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care."
6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and DQs are "Don't Care" except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

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TRUTH TABLE CURRENT STATE BANK n, COMMAND TO BANK

(1-6)

CURRENT STATE

COMMAND (ACTION)

CS RAS CAS WE

Any

COMMAND INHIBIT (NOP/Continue previous operation)

NO OPERATION (NOP/Continue previous operation)

Idle

ACTIVE (Select and activate row)

AUTO REFRESH

(7)

LOAD MODE REGISTER

(7)

PRECHARGE

(11)

Row Active

READ (Select column and start READ burst)

(10)

WRITE (Select column and start WRITE burst)

(10)

PRECHARGE (Deactivate row in bank or banks)

(8)

Read

READ (Select column and start new READ burst)

(10)

(Auto

WRITE (Select column and start WRITE burst)

(10)

Precharge

PRECHARGE (Truncate READ burst, start PRECHARGE)

(8)

Disabled)

BURST TERMINATE

(9)

Write

READ (Select column and start READ burst)

(10)

(Auto

WRITE (Select column and start new WRITE burst)

(10)

Precharge

PRECHARGE (Truncate WRITE burst, start PRECHARGE)

(8)

Disabled)

BURST TERMINATE

(9)

TRUTH TABLE CKE

(1-4)

CURRENT STATE

COMMANDn

ACTIONn

CKEn-1

CKEn

Power-Down

Maintain Power-Down

Self Refresh

Maintain Self Refresh

Clock Suspend

Maintain Clock Suspend

Power-Down

(5)

COMMAND INHIBIT or NOP

Exit Power-Down

Self Refresh

(6)

COMMAND INHIBIT or NOP

Exit Self Refresh

Clock Suspend

(7)

Exit Clock Suspend

All Banks Idle

COMMAND INHIBIT or NOP

Power-Down Entry

All Banks Idle

AUTO REFRESH

Self Refresh Entry

Reading or Writing

VALID

Clock Suspend Entry

See TRUTH TABLE CURRENT STATE BANK n, COMMAND TO BANK

NOTES:
1. CKEn is the logic state of CKE at clock edge

n; CKEn-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge

3. COMMANDn is the command registered at clock edge

n, and ACTONn is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge

n will put the device in the all banks idle state in time for clock edge n+1 (provided that t

CKS

is met).

6. Exiting self refresh at clock edge

n will put the device in all banks idle state once t

XSR

is met. COMMAND INHIBIT or NOP commands

should be issued on clock edges occurring during the t

XSR

period. A minimum of two NOP commands must be sent during t

XSR

period.

7. After exiting clock suspend at clock edge

n, the device will resume operation and recognize the next command at clock edge n+1.

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NOTE:

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after t

XSR

has been met (if the

previous state was SELF REFRESH).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those

allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and t

has been met.

Row Active: A row in the bank has been activated, and t

RCD

has been met. No data bursts/accesses and no register

accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or

allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to
the other bank are determined by its current state and CURRENT STATE BANK n truth tables.

Precharging: Starts with registration of a PRECHARGE command and ends when t

is met. Once t

is met, the bank

will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when t

RCD

is met. Once t

RCD

is met, the bank will

be in the row active state.

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when t

has been met.

Once t

is met, the bank will be in the idle state.

Write w/Auto

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when t

has been met.

Once t

is met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be

applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when t

is met. Once t

is met, the

SDRAM will be in the all banks idle state.

Accessing Mode

MRD

has been met. Once

MRD

is met, the SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when t

is met. Once t

is met, all

banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs

or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

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TRUTH TABLE CURRENT STATE BANK

n, COMMAND TO BANK m

(1-6)

CURRENT STATE

COMMAND (ACTION)

CS RAS CAS WE

Any

COMMAND INHIBIT (NOP/Continue previous operation)

NO OPERATION (NOP/Continue previous operation)

Idle

Any Command Otherwise Allowed to Bank

Row

ACTIVE (Select and activate row)

Activating,

READ (Select column and start READ burst)

(7)

Active, or

WRITE (Select column and start WRITE burst)

(7)

Precharging

PRECHARGE

Read

ACTIVE (Select and activate row)

(Auto

READ (Select column and start new READ burst)

(7,10)

Precharge

WRITE (Select column and start WRITE burst)

(7,11)

Disabled)

PRECHARGE

(9)

Write

ACTIVE (Select and activate row)

(Auto

READ (Select column and start READ burst)

(7,12)

Precharge

WRITE (Select column and start new WRITE burst)

(7,13)

Disabled)

PRECHARGE

(9)

Read

ACTIVE (Select and activate row)

(With Auto

READ (Select column and start new READ burst)

(7,8,14)

Precharge)

WRITE (Select column and start WRITE burst)

(7,8,15)

PRECHARGE

(9)

Write

ACTIVE (Select and activate row)

(With Auto

READ (Select column and start READ burst)

(7,8,16)

Precharge)

WRITE (Select column and start new WRITE burst)

(7,8,17)

PRECHARGE

(9)

NOTE:

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after t

XSR

has been met (if the previous

state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank

n and the commands shown

are those allowed to be issued to bank

m (assuming that bank m is in such a state that the given command is allowable). Exceptions are

covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and t

has been met.

Row Active: A row in the bank has been activated, and t

RCD

has been met. No data bursts/accesses and no register

accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when t

has been met.

Once t

is met, the bank will be in the idle state.

Write w/Auto

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when t

has been

met. Once t

is met, the bank will be in the idle state.

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.

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7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled

and READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-

rupted by bank m's burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the

READ on bank n, CAS latency later (Consecutive READ Bursts).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt

the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to prevent
bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt

the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt

the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the

READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP 1).

15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the

READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the

WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after
t

is met, where t

begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered

one clock prior to the READ to bank m (Fig CAP 3).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the

WRITE on bank n when registered. The PRECHARGE to bank n will begin after t

is met, where t WR begins when the WRITE

to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Fig CAP 4).

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FUNCTIONAL DESCRIPTION

The 64Mb SDRAMs (512K x 32 x 4 banks) are quad-bank
DRAMs which operate at 2.5V and include a synchronous
interface (all signals are registered on the positive edge of
the clock signal, CLK). Each of the 16,777,216-bit banks
is organized as 2,048 rows by 256 columns by 32bits.

Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank, A0-A10
select the row). The address bits (A0-A7) registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a
predefined manner.

The 64M SDRAM is initialized after the power is applied
to V

and V

DDQ

(simultaneously) and the clock is stable.

A 100µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or a NOP. The COMMAND
INHIBIT or NOP may be applied during the 100µs period
and continue should at least through the end of the period.

With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 100µs delay has been satisfied. All
banks must be precharged. This will leave all banks in an
idle idle state where two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete,
the SRDRAM is then ready for mode register programming.

The mode register should be loaded prior to applying any
operational command because it will power up in an
unknown state.

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REGISTER DEFINITION

Mode Register

The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS\ latency,
an operating mode and a write burst mode, as shown in
MODE REGISTER DEFINITION.

The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information

until it is programmed again or the device loses power.

Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 and M12 are reserved for future use.

The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements will result in unspecified operation.

MODE REGISTER DEFINITION

Latency Mode

M6 M5 M4 CAS

Latency

0 0 0

Reserved

0 0 1

Reserved

0 1 0

0 1 1

1 0 0

Reserved

1 0 1

Reserved

1 1 0

Reserved

1 1 1

Reserved

Write Burst Mode

Mode

Burst

Write

Single-Bit

Write

MRS

M8 M7 MRS

Mode Register Set

All Other States Reserved

Burst Type

M3 Type

0 Sequential
1 Interleaved

Burst Length

M2 M1 M0 Sequential Interleave

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

Reserved

1 0 1

Reserved

1 1 0

Reserved

1 1 1

Full

Page

Reserved

Address Bus

BA0,1 A10/AP

A9 A8

A7 A6 A5

A4 A3

A2 A1 A0

(1)

Note:
1. Maintain low during Mode Register Set.

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BURST DEFINITION

Burst

Starting Column

Order of Accesses Within a Burst

Length

Address

Type = Sequential

Type = Interleaved

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

n = A0-A7

Cn, Cn + 1, Cn + 2

Not Supported

Page

Cn + 3, Cn + 4...

(y)

(location 0-y)

...Cn - 1,

Cn...

Burst Length

Read and write accesses to the SDRAM are burst ori-
ented, with the burst length being programmable, as
shown in MODE REGISTER DEFINITION. The burst
length determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE
command. Burst lengths of 1, 2, 4 or 8 locations are
available for both the sequential and the interleaved burst
types, and a full-page burst is available for the sequential
type. The full-page burst is used in conjunction with the
BURST TERMINATE command to generate arbitrary
burst lengths.

Reserved states should not be used, as unknown opera-
tion or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.

All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-A7 (x32) when the burst length is set to two; by A2-A7
(x32) when the burst length is set to four; and by A3-A7
(x32) when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts wrap
within the page if the boundary is reached.

Burst Type

Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.

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DON'T CARE

UNDEFINED

CLK

COMMAND

READ NOP NOP NOP

CAS Latency - 3

OUT

T0 T1 T2 T3 T4

CLK

COMMAND

READ NOP NOP

CAS Latency - 2

OUT

T0 T1 T2 T3

CAS Latency

The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the
latency is

m clocks, the data will be available by clock

edge

n + m. The DQs will start driving as a result of the

clock edge one cycle earlier

(n + m - 1), and provided that

the relevant access times are met, the data will be valid
by clock edge

n + m. For example, assuming that the

clock cycle time is such that all relevant access times are
met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as shown
in CAS Latency diagrams. The Allowable Operating Fre-
quency table indicates the operating frequencies at which
each CAS latency setting can be used.

Reserved states should not be used as unknown operation
or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are

Allowable Operating Frequency (MHz)

Speed

CAS Latency = 2

CAS Latency = 3

7.5

100

133

reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.

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Activating Specific Row Within Specific Bank

DON'T CARE

CLK

COMMAND

ACTIVE NOP NOP

RCD

T0 T1 T2 T3 T4

READ or

WRITE

OPERATION

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to
a bank within the SDRAM, a row in that bank must be
"opened." This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated
(see Activating Specific Row Within Specific Bank).

After opening a row (issuing an ACTIVE command), a READ
or WRITE command may be issued to that row, subject to
the t

RCD

specification. Minimum t

RCD

should be divided by

the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a t

RCD

specification of 20ns with a

125 MHz clock (8ns period) results in 2.5 clocks, rounded
to 3. This is reflected in the following example, which
covers any case where 2 < [t

RCD

(MIN)/t

]

3. (The

same procedure is used to convert other specification
limits from time units to clock cycles).

A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been "closed" (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by t

A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by t

RRD

Example: Meeting t

RCD

(MIN) when 2

<<
<<
< [t

RCD

(min)/t

]

CLK

CKE

HIGH - Z

ROW ADDRESS

BANK ADDRESS

RAS

CAS

A0-A10

BA0, BA1

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READ COMMAND

READS

READ bursts are initiated with a READ command, as shown
in the READ COMMAND diagram.

The starting column and bank addresses are provided with the
READ command, and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the
burst. For the generic READ commands used in the following
illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the
starting column address will be available following the
CAS latency after the READ command. Each subsequent
data-out element will be valid by the next positive clock
edge. The CAS Latency diagram shows general timing
for each possible CAS latency setting.

Upon completion of a burst, assuming no other commands
have been initiated, the DQs will go High-Z. A full-page
burst will continue until terminated. (At the end of the page,
it will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed burst or
the last desired data element of a longer burst which is
being truncated.

The new READ command should be issued

x cycles

before the clock edge at which the last desired data
element is valid, where

x equals the CAS latency minus

one. This is shown in Consecutive READ Bursts for CAS
latencies of two and three; data element

n + 3 is either the

last of a burst of four or the last desired of a longer burst.
The 64Mb SDRAM uses a pipelined architecture and
therefore does not require the

2n rule associated with a

prefetch architecture. A READ command can be initiated
on any clock cycle following a previous READ command.
Full-speed random read accesses can be performed to the
same bank, as shown in Random READ Accesses, or each
subsequent READ may be performed to a different bank.

Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-length
READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations).
The WRITE burst may be initiated on the clock edge
immediately following the last (or last desired) data
element from the READ burst, provided that DQ contention
can be avoided. In a given system design, there may be
a possibility that the device driving the input data will go
Low-Z before the SDRAM DQs go High-Z. In this case, at
least a single-cycle delay should occur between the last
read data and the WRITE command.

The DQM input is used to avoid DQ contention, as shown
in Figures RW1 and RW2. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers)
to suppress data-out from the READ. Once the WRITE
command is registered, the DQs will go High-Z (or remain
High-Z), regardless of the state of the DQM signal,
provided the DQM was active on the clock just prior to the
WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For
example, if DQM was LOW during T4 in Figure RW2, then
the WRITEs at T5 and T7 would be valid, while the WRITE
at T6 would be invalid.

The DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers)
to ensure that the written data is not masked. Figure RW1
shows the case where the clock frequency allows for bus
contention to be avoided without adding a NOP cycle, and
Figure RW2 shows the case where the additional NOP is
needed.

A fixed-length READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank (provided
that auto precharge was not activated), and a full-page burst
may be truncated with a PRECHARGE command to the

CLK

CKE

HIGH-Z

COLUMN ADDRESS

AUTO PRECHARGE

NO PRECHARGE

RAS

CAS

A0-A7

A10

BA0, BA1

BANK ADDRESS

A8, A9

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DON'T CARE

UNDEFINED

CLK

COMMAND

READ NOP NOP NOP

CAS Latency - 3

OUT

T0 T1 T2 T3 T4

CLK

COMMAND

READ NOP NOP

CAS Latency - 2

OUT

T0 T1 T2 T3

CAS Latency

same bank. The PRECHARGE command should be issued
x cycles before the clock edge at which the last desired
data element is valid, where

x equals the CAS latency

minus one. This is shown in the READ to PRECHARGE
diagram for each possible CAS latency; data element

n +

3 is either the last of a burst of four or the last desired of a
longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued
until t

is met. Note that part of the row precharge time is

hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the

PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.

Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The
BURST TERMINATE command should be issued

x cycles

before the clock edge at which the last desired data
element is valid, where

x equals the CAS latency minus

one. This is shown in the READ Burst Termination
diagram for each possible CAS latency; data element

n +

3 is the last desired data element of a longer burst.

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CLK

CKE

HIGH - Z

COLUMN ADDRESS

AUTO PRECHARGE

BANK ADDRESS

RAS

CAS

A0-A7

A10

BA0, BA1

NO PRECHARGE

A8, A9

WRITE Command

The starting column and bank addresses are provided with
the WRITE command, and auto precharge is either enabled
or disabled for that access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the
burst. For the generic WRITE commands used in the
following illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be
registered coincident with the WRITE command. Subsequent
data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length
burst, assuming no other commands have been initiated,
the DQs will remain High-Z and any additional input data will
be ignored (see WRITE Burst). A full-page burst will
continue until terminated. (At the end of the page, it will wrap
to column 0 and continue.)

Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be issued
on any clock following the previous WRITE command, and
the data provided coincident with the new command applies
to the new command.

An example is shown in WRITE to WRITE diagram. Data
n + 1 is either the last of a burst of two or the last desired
of a longer burst. The 64Mb SDRAM uses a pipelined
architecture and therefore does not require the

2n rule

associated with a prefetch architecture. A WRITE command
can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses
within a page can be performed to the same bank, as
shown in Random WRITE Cycles, or each subsequent
WRITE may be performed to a different bank.

Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-length
WRITE burst may be immediately followed by a subsequent
READ command. Once the READ com mand is regis-
tered, the data inputs will be ignored, and WRITEs will not
be executed. An example is shown in WRITE to READ.
Data

n + 1 is either the last of a burst of two or the last

desired of a longer burst.

Data for a fixed-length WRITE burst may be fol lowed by,
or truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page WRITE burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued t

after the

clock edge at which the last desired input data element is
registered. The auto precharge mode requires a t

of at

least one clock plus time, regardless of frequency. In
addition, when truncating a WRITE burst, the DQM signal
must be used to mask input data for the clock edge prior
to, and the clock edge coincident with, the PRECHARGE
command. An example is shown in the WRITE to
PRECHARGE diagram. Data

n+1 is either the last of a burst

of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the
same bank cannot be issued until t

is met.

In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto
precharge. The disadvantage of the PRECHARGE command
is that it requires that the command and address buses be
available at the appropriate time to issue the command; the
advantage of the PRECHARGE command is that it can be
used to truncate fixed-length or full-page bursts.

Fixed-length or full-page WRITE bursts can be truncated
with the BURST TERMINATE command. When truncating
a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last
data written (provided that DQM is LOW at that time) will
be the input data applied one clock previous to the BURST
TERMINATE command. This is shown in WRITE Burst
Termination, where data

n is the last desired data element

of a longer burst.

WRITEs

WRITE bursts are initiated with a WRITE command, as
shown in WRITE Command diagram.

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CLK

CKE

HIGH - Z

ALL BANKS

BANK SELECT

BANK ADDRESS

RAS

CAS

A0-A9

A10

BA0, BA1

DON'T CARE

CLK

CKE

COMMAND

NOP NOP

ACTIVE

CKS

All banks idle

Enter power-down mode

Exit power-down mode

RCD

RAS

Input buffers gated off

PRECHARGE Command

POWER-DOWN

Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses are
in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-
down occurs when there is a row active in either bank, this
mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding
CKE, for maximum power savings while in standby. The
device may not remain in the power-down state longer than
the refresh period (64ms) since no refresh operations are
performed in this mode.

The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting t

CKS

). See figure below.

PRECHARGE

The PRECHARGE command (see figure) is used to
deactivate the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a
subsequent row access some specified time (t

) after

the PRECHARGE command is issued. Input A10 deter-
mines whether one or all banks are to be precharged, and
in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as "Don't Care."
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE com-
mands being issued to that bank.

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DON'T CARE

CLK

CKE

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5

NOP

WRITE NOP

NOP

BANK a,

COL n

n+1

n+2

INTERNAL

CLOCK

DON'T CARE

CLK

CKE

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6

READ NOP NOP

NOP NOP NOP

BANK a,

COL n

n+1

n+2

n+3

INTERNAL

CLOCK

CLOCK SUSPEND

Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, "freezing"
the synchronous logic.

For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.

Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)

Clock suspend mode is exited by registering CKE HIGH;
the internal clock and related operation will resume on the
subsequent positive clock edge.

Clock Suspend During WRITE Burst

Burst Length 4 or greater DQM is low.

CAS Latency=2. Burst Length =4 or greater. DQM is low.

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DON'T CARE

CLK

COMMAND

BANK n

BANK m

ADDRESS

T0 T1 T2 T3 T4 T5 T6 T7

NOP

NOP NOP NOP NOP

OUT

a+1

OUT

b+1

BANK n,

COL a

BANK m,

COL b

CAS Latency - 3 (BANK n)

CAS Latency - 3 (BANK m)

RP - BANK n

RP - BANK m

READ - AP

BANK n

READ - AP

BANK m

Page Active

READ with Burst of 4

Interrupt Burst, Precharge

Idle

Page Active

READ with Burst of 4

Precharge

Internal States

DON'T CARE

CLK

COMMAND

BANK n

BANK m

ADDRESS

DQM

T0 T1 T2 T3 T4 T5 T6 T7

NOP NOP NOP

OUT

b+1

b+2

b+3

BANK n,

COL a

BANK m,

COL b

CAS Latency - 3 (BANK n)

RP - BANK n

RP - BANK m

Read - AP

BANK n

WRITE - AP

BANK m

READ with Burst of 4

Interrupt Burst, Precharge

Idle

Page Active

WRITE with Burst of 4

Write-Back

Internal States

Page Active

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic 1.
In this mode, all WRITE commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).

CONCURRENT AUTO PRECHARGE

An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI

SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.

READ with Auto Precharge

1. Interrupted by a READ (with or without auto precharge):

A READ to bank m will interrupt a READ on bank n, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.

2. Interrupted by a WRITE (with or without auto precharge):

A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used two clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.

Fig CAP 1 - READ With Auto Precharge interrupted by a READ

Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE

IS42R32200C1

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00B

12/14/05

DON'T CARE

CLK

COMMAND

BANK n

BANK m

ADDRESS

T0 T1 T2 T3 T4 T5 T6 T7

NOP

NOP NOP NOP NOP

a+1

OUT

b+1

BANK n,

COL a

BANK m,

COL b

CAS Latency - 3 (BANK m)

RP - BANK n

RP - BANK m

WRITE - AP

BANK n

READ - AP

BANK m

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

Page Active

READ with Burst of 4

Precharge

Internal States

- BANK n

DON'T CARE

CLK

COMMAND

BANK n

BANK m

ADDRESS

T0 T1 T2 T3 T4 T5 T6 T7

NOP

NOP NOP

NOP NOP NOP

BANK n,

COL a

BANK m,

COL b

RP - BANK n

RP - BANK m

WRITE - AP

BANK n

WRITE - AP

BANK m

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

Page Active

WRITE with Burst of 4

Write-Back

Internal States

- BANK n

a+1

a+2

b+1

b+2

b+3

WRITE with Auto Precharge

3. Interrupted by a READ (with or without auto precharge):

A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing CAS latency later.
The PRECHARGE to bank n will begin after t

is met,

where t

begins when the READ to bank m is registered.

The last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m.

4. Interrupted by a WRITE (with or without auto precharge):

AWRITE to bank m will interrupt a WRITE on bank n when
registered. The PRECHARGE to bank n will begin after
t

is met, where t

begins when the WRITE to bank

m is registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to bank m.

Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ

Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE

IS42R32200C1

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00B
12/14/05

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameters

Rating

Unit

MAX

Maximum Supply Voltage

0.5 to +3.6

DDQ

MAX

Maximum Supply Voltage for Output Buffer

0.5 to +3.6

Input Voltage

0.5 to +3.6

OUT

Output Voltage

0.5 to +3.6

MAX

Allowable Power Dissipation

Output Shorted Current

OPR

Operating Temperature

Com.

0 to +70

°C

Ind.

40 to +85

STG

Storage Temperature

55 to +150

°C

DC RECOMMENDED OPERATING CONDITIONS

(2,5)

(

At T

= 0 to +70°C)

Symbol

Parameter

Min.

Typ.

Max.

Unit

, V

DDQ

Supply Voltage

2.3

2.5

2.7

Input High Voltage

(3)

1.7

+ 0.3

Input Low Voltage

(4)

-0.3

+0.7

CAPACITANCE CHARACTERISTICS

(1,2)

(At T

= 0 to +25°C, V

= V

DDQ

= 2.5 ± 0.2V, f = 1 MHz)

Symbol

Parameter

Typ.

Max.

Unit

IN1

Input Capacitance: A0-A10, BA0, BA1

IN2

Input Capacitance: (CLK, CKE,

CS, RAS, CAS, WE, LDQM, UDQM)

CI/O

Data Input/Output Capacitance: DQ0-DQ31

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

2. All voltages are referenced to GND.
3. V

(max) = V

DDQ

+ 1.5V with a pulse width

3 ns. The pluse width cannot be greater than one third of the cycle rate.

4. V

(min) = GND 1.5V with a pulse < 3 ns. The pluse width cannot be greater than one third of the cycle rate.

5. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device operation

is ensured. (Vdd and VddQ must be powered up simultaneously. GND and GNDQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated anytime the t

REF

refresh requirement is exceeded.

IS42R32200C1

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00B

12/14/05

DC ELECTRICAL CHARACTERISTICS

(Recommended Operation Conditions unless otherwise noted.)

Symbol

Parameter

Test Condition

Speed

Min.

Max.

Unit

Input Leakage Current

, with pins other than

µA

the tested pin at 0V

Output Leakage Current

Output is disabled

1.5

µA

OUT

Output High Voltage Level

OUT

= 1 mA

2.0

Output Low Voltage Level

OUT

= +1 mA

0.4

CC1

Operating Current

(1,2)

One Bank Operation,

CAS latency = 3

120

Burst Length=1
t

(min.)

OUT

= 0mA

CC2P

Precharge Standby Current

CKE

(

MAX

)

= t

(

MIN

)

CC2PS

(In Power-Down Mode)

CC2N

Precharge Standby Current

CKE

(

MIN

)

= t

(

MIN

)

CC2NS

(In Non Power-Down Mode)

Com.

Ind.

CC3P

Active Standby Current

CKE

(

MAX

)

= t

(

MIN

) Com.

Ind.

CC3PS

(In Power-Down Mode)

Com.

Ind.

CC3N

Active Standby Current

CKE

(

MIN

)

= t

(

MIN

)

CC3NS

(In Non Power-Down Mode)

Com.

Ind.

CC4

Operating Current

= t

(

MIN

)

CAS latency = 3

100

(In Burst Mode)

(1)

OUT

= 0mA

CAS latency = 2

CC5

Auto-Refresh Current

= t

(

MIN

)

100

CC6

Self-Refresh Current

CKE

0.2V

1.5

Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time

increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vdd and GND for each memory
chip to suppress power supply voltage noise (voltage drops) due to these transient currents.

2. Icc

and Icc

depend on the output load. The maximum values for Icc

and Icc

are obtained with the output open state.

IS42R32200C1

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00B
12/14/05

AC ELECTRICAL CHARACTERISTICS

(1,2,3)

-75

Symbol

Parameter

Condition

Min.

Max.

Units

CK3

Clock Cycle Time

CAS Latency = 3

7.5

CK2

CAS Latency = 2

AC3

Access Time From CLK

(4)

CAS Latency = 3

6.5

AC2

CAS Latency = 2

CLK HIGH Level Width

2.5

CLK LOW Level Width

2.5

Output Data Hold Time

2.5

Output LOW Impedance Time

HZ3

Output HIGH Impedance Time

(5)

CAS Latency = 3

6.5

HZ2

CAS Latency = 2

Input Data Setup Time

Input Data Hold Time

0.8

Address Setup Time

Address Hold Time

0.8

CKS

CKE Setup Time

CKH

CKE Hold Time

0.8

CKA

CKE to CLK Recovery Delay Time

1CLK+3

Command Setup Time (

CS, RAS, CAS, WE, DQM)

Command Hold Time (

CS, RAS, CAS, WE, DQM)

Command Period (REF to REF / ACT to ACT)

RAS

Command Period (ACT to PRE)

38.7

120K

Command Period (PRE to ACT)

RCD

Active Command To Read / Write Command Delay Time

RRD

Command Period (ACT [0] to ACT[1])

IS42R32200C1

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00B

12/14/05

AC ELECTRICAL CHARACTERISTICS

(1,2,3)

-75

Symbol

Parameter

Condition

Min.

Max.

Units

DPL3

Input Data To Precharge

CAS Latency = 3

2CLK

Command Delay time

DPL2

CAS Latency = 2

2CLK

DAL3

Input Data To Active / Refresh

CAS Latency = 3

2CLK+t

Command Delay time (During Auto-Precharge)

DAL2

CAS Latency = 2

2CLK+t

Transition Time

(2)

0.3

Write Recovery Time

1CLK+7.5ns

XSR

Exit Self Refresh and Active Command

(6)

RFC

Auto Refresh Period

REF

Refresh Cycle Time (4096)

Notes:
1. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device

operation is ensured. (V

and V

DDQ

must be powered up simultaneously. GND and GNDQ must be at same potential.) The two

AUTO REFRESH command wake-ups should be repeated anytime the t

REF

refresh requirement is exceeded.

2. Measured with t

= 1 ns.

3. The reference level is 1.2V when measuring input signal timing. Rise/fall times are measured between V

(min.) and V

(max.).

4. Access time is measured at 1.2V with the load shown in the figure below.
5. The time t

(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V

(min.) or V

(max.)

when the output is in the high impedance state.

6. CLK must be toggled a minimum of two times during this period.

IS42R32200C1

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00B
12/14/05

OPERATING FREQUENCY / LATENCY RELATIONSHIPS

SYMBOL

PARAMETER

CONDITION

UNITS

Clock Cycle Time

7.5

Operating Frequency

133

100

MHz

CCD

READ/WRITE command to READ/WRITE command

cycle

CKED

CKE to clock disable or power-down entry mode

cycle

PED

CKE to clock enable or power-down exit setup mode

cycle

DQD

DQM to input data delay

cycle

DQM

DQM to data mask during WRITEs

cycle

DQZ

DQM to data high-impedance during READs

cycle

DWD

WRITE command to input data delay

cycle

DAL

Data-in to ACTIVE command

CL=3

cycle

CL=2

DPL

Data-in to PRECHARGE command

cycle

BDL

Last data-in to burst STOP command

cycle

CDL

Last data-in to new READ/WRITE command

cycle

RDL

Last data-in to PRECHARGE command

cycle

MRD

LOAD MODE REGISTER command

cycle

to ACTIVE or REFRESH command

ROH

Data-out to high-impedance from

CL = 3

cycle

PRECHARGE command

CL = 2

AC TEST CONDITIONS

(Input/Output Reference Level: 1.2V)

Input Load

Output Load

2.5V

1.2V

CLK

INPUT

OUTPUT

CHI

2.5V

1.2V

I/O

+1.2V

30 pF

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. C
01/28/02

Plastic TSOP 54Pin, 86-Pin
Package Code: T (Type II)

Plastic TSOP (T - Type II)

Millimeters

Inches

Symbol

Min

Max

Min

Max

Ref. Std.

No. Leads (N)

1.20

0.047

0.05

0.15

0.002

0.006

0.30

0.45

0.012

0.018

0.12

0.21

0.005

0.0083

22.02 22.42

0.867

0.8827

10.03 10.29

0.395

0.405

11.56 11.96

0.455

0.471

0.80 BSC

0.031 BSC

0.40

0.60

0.016

0.024

ZD 0.71 REF

0°

8°

0°

8°

SEATING PLANE

N/2

N/2+1

Notes:
1. Controlling dimension: millimieters,

unless otherwise specified.

2. BSC = Basic lead spacing between

centers.

3. Dimensions D and E1 do not include

mold flash protrusions and

should be

measured from the bottom of the
package

4. Formed leads shall be planar with

respect to one another within 0.004
inches at the seating plane.

Plastic TSOP (T - Type II)

Millimeters

Inches

Symbol

Min

Max

Min

Max

Ref. Std.

No. Leads (N)

1.20

0.047

0.05

0.15

0.002

0.006

0.95

1.05

0.037

0.041

0.17

0.27

0.007

0.011

0.12

0.21

0.005

0.008

22.02 22.42

0.867

0.8827

10.16 BSC

0.400 BSC

11.56 11.96

0.455

0.471

0.50 BSC

0.020 BSC

0.40

0.60

0.016

0.024

0.80 REF

0.031 REF

ZD 0.61 REF 0.024 BSC

0°

8°

0°

8°

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