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Электронный компонент: PDM21048LL-12

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Rev. 0.0 - 4/30/98
1
ADVANCED
Features
n
High-speed access times
Com'l: 100 and 120 ns
n
Low power operation (typical)
- PDM21048LL
Active: 65 mW
Standby: 7
W
n
Single +2.7V (
0.3V) power supply
n
TTL-compatible inputs and outputs
n
I/Os are 3.6V tolerant
n
Low data retention voltage: 1.5V
n
Packages
Plastic TSOP (I) - T
Plastic STSOP (I) - ST
Description
The PDM21048LL is a very low power CMOS static
RAM organized as 131,072 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE1) inputs are both LOW, and
CE2 is high. Reading is accomplished when WE and
CE2 remain HIGH and CE1 and OE are both LOW.
The PDM21048LL operates from a single +2.7V
power supply and all the inputs and outputs are
fully TTL- compatible. The device supports low data
retention voltage for battery back-up operation with
low current.
The PDM21048LL is available in a 32-pin plastic
TSOP (I) and a 32-pin plastic STSOP (I).
A




A
0
17
I/O
I/O
0
7
CE1
WE
Addresses
Decoder
Memory
Matrix
Input
Data
Control
Column I/O
OE
CE2
Control
Functional Block Diagram
PDM21048LL
256K x 8-Bit Low Power
2.7 Volt
PDM21048LL
2
Rev. 0.0 - 4/30/98
ADVANCED
Truth Table
NOTE: H = V
IH
, L = V
IL
, X = DON'T CARE
Absolute Maximum Ratings
(1)
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form
: T
j
= T
a
+ P *
ja
where T
a
is the ambient tempera-
ture, P is average operating power and
ja
the thermal resistance of the package. For
this product, use the following
ja
values:
SOJ: 78
o
C/W
TSOP: 112
o
C/W
OE
WE
CE1
CE2
I/O
MODE
X
X
H
X
Hi-Z
Standby
X
X
X
L
Hi-Z
Standby
L
H
L
H
D
OUT
Read
X
L
L
H
D
IN
Write
H
H
L
H
Hi-Z
Output Disable
Symbol
Rating
Com'l.
Ind.
Unit
V
TERM
Terminal Voltage with Respect to Vss
0.5 to +4.6
0.5 to +4.6
V
T
BIAS
Temperature Under Bias
55 to +125
65 to +135
C
T
STG
Storage Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
1.0
1.0
W
I
OUT
DC Output Current
20
20
mA
T
j
Maximum Junction Temperature
(2)
125
125
C
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Configurations
TSOP (I), STSOP (I)
Pin Description
Name
Description
A17-A0
Address Inputs
I/O7-I/O0
Data Inputs/Outputs
OE
Output Enable Input
WE
Write Enable Input
CE1, CE2
Chip Enable Inputs
V
CC
Power (+2.7V)
V
SS
Ground
PDM21048LL
Rev. 0.0 - 4/30/98
3
ADVANCED
Recommended DC Operating Conditions
DC Electrical Characteristics
(V
CC
= 3.3V
0.3V)
NOTE:1.V
IL
(min) = 3.0V for pulse width less than 20 ns. 2. V
CC
= 2.7V, 25C.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
2.4
2.7
3.0
V
V
SS
Supply Voltage
0
0
0
V
Commercial
Ambient Temperature
0
25
70
C
Symbol
Parameter
Test Conditions
Min.
Typ.
(2)
Max.
Unit
I
LI
Input Leakage Current
V
CC
= MAX., V
IN
= Vss to V
CC
1
--
1
A
I
LO
Output Leakage Current
V
CC
= MAX.,
CE1= V
IH
, or
CE2 = V
IL
V
OUT
= Vss to
V
CC
1
--
1
A
V
IL
Input Low Voltage
0.3
(1)
--
0.8
V
V
IH
Input High Voltage
2.2
--
Vcc+0.3
V
V
OL
Output Low Voltage
I
OL
= 2mA, V
CC
= Min.
--
--
0.4
V
V
OH
Output High Voltage
I
OH
= 1 mA,
V
CC
= Min.
2.2
--
--
V
I
CC
Operating Power Supply
Current
V
CC
= MAX
CE1 = V
IL,
CE2 =V
IH
I
OUT
= 0 mA
f = f
MAX
--
--
35
mA
I
SB
Standby Current (TTL)
V
CC
= MAX
CE1 = V
IH
or
CE2
=
V
IL
--
--
1
mA
I
SB1
Full Standby Current
(CMOS)
V
CC
= MAX
CE1
V
CC
-0.2V,
CE2
0.2V
V
IN
V
CC
-0.2V
or
0.2V
--
2
A
35
A
PDM21048LL
4
Rev. 0.0 - 4/30/98
ADVANCED
Data Retention Characteristics
NOTE: 1. V
CC
= 2.7V, 25C.
Capacitance
(1)
(T
A
= +25
C, f = 1.0 MHz)
NOTE: 1. This parameter is determined by device characterization but is not production
tested.
AC Test Conditions
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
DR
V
CC
for data retention
CE1
V
CC
-0.2V
CE2
0.2V
V
IN
V
CC
-0.2V
or
0.2V
1.5
--
--
V
I
CC DR
Data retention current
CE1
V
CC
-0.2V
CE2
0.2V
V
IN
V
CC
-0.2V
or
0.2V
--
1
20
A
t
CDR
Chip deselect to data
retention time
See waveform
0
--
--
ns
t
R
Recovery time
See waveform
t
RC
--
--
ns
Symbol
Parameter
Max.
Unit
C
IN
Input Capacitance
6
pF
C
OUT
Output Capacitance
8
pF
Input pulse levels
V
SS
to 2.4V
Input rise and fall times
5 ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
PDM21048LL
Rev. 0.0 - 4/30/98
5
ADVANCED
DON'T CARE
VCC
V
V
IH
IL
t
CDR
V
t
RC
2.7V
2.7V
Data Retention Mode
CE1
DR
CE2
VDR
0.2V
V
V
IH
IL
353
319
100 pF
+2.7V
DATA
OUT
353
319
5 pF
+2.7V
DATA
OUT
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
, t
HZOE
)
Low V
CC
Data Retention Waveform
PDM21048LL
6
Rev. 0.0 - 4/30/98
ADVANCED
Read Cycle No. 1
(1)
Read Cycle No. 2
(2)
AC Electrical Characteristics
Description
-10
-12
READ Cycle
Sym Min
Max
Min
Max
Units
READ cycle time
t
RC
100
120
ns
Address access time
t
AA
100
120
ns
Chip enable access time
t
ACE
100
120
ns
Output hold from address change
t
OH
10
10
ns
Chip enable to output in low Z
(3,4,5)
t
LZCE
10
10
ns
Chip disable to output in high Z
(3,4,5)
t
HZCE
35
35
ns
Output enable access time
t
AOE
50
50
ns
Output enable to output in low Z
(4,5)
t
LZOE
10
10
ns
Output disable to output in high Z
(4,5)
t
HZOE
30
30
ns
t
RC
t
AA
t
OH
PREVIOUS DATA VALID
DOUT
ADDR
DATA VALID
t
RC
t
ACE
t
AA
t
LZCE
t
HZCE
t
LZOE
t
HZOE
t
AOE
ADDR
CE1
CE2
OE
D
OUT
DATA VALID
PDM21048LL
Rev. 0.0 - 4/30/98
7
ADVANCED
Write Cycle No. 1 (Write Enable Controlled)
Write Cycle No. 2 (Chip Enable Controlled)
t
WC
t
AW
t
WP2
t
CW
t
AH
t
AS
t
DH
t
DS
t
LZWE
t
HZWE
ADDR
CE1
CE2
WE
D
OUT
HIGH-Z
D
IN
DATA VALID
t
WC
t
AW
t
WP1
t
CW
t
AH
t
AS
t
DH
t
DS
ADDR
CE1
CE2
WE
D
OUT
HIGH-Z
D
IN
DATA VALID
PDM21048LL
8
Rev. 0.0 - 4/30/98
ADVANCED
Device Type
Power
Speed
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Commercial (0
to +70
C)
10
100 ns
12
120 ns
LL
Low Power
Blank
Blank Tubes
TR Tape & Reel
TY
Tray
PDM21048 - 2 Meg (256Kx8) Static RAM
XXXXX
X
XX
X
X
X
T
32-pin Plastic TSOP (I)
ST
32-pin Plastic STSOP (I)
AC Electrical Characteristics
NOTES: (For two previous Electrical Characteristics tables)
1. The device is continuously selected. Chip Enable is held in its active state.
2. The address is valid prior to or coincident with the latest occuring Chip Enable.
3. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
.
4. This parameter is sampled.
5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured
500 mV from steady state voltage.
Description
-10
-12
WRITE Cycle
Sym
Min.
Max.
Min.
Max.
Units
WRITE cycle time
t
WC
100
120
ns
Chip enable to end of write
t
CW
100
120
ns
Address valid to end of write
t
AW
100
120
ns
Address setup time
t
AS
0
0
ns
Address hold from end of write
t
AH
0
0
ns
Write pulse width
t
WP
50
60
ns
Data setup time
t
DS
40
50
ns
Data hold time
t
DH
0
0
ns
Write disable to output in low Z
(4,5)
t
LZWE
5
5
ns
Write enable to output in high Z
(4,5)
t
HZWE
30
30
ns
Ordering Information
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