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Электронный компонент: PDM31256SA20TTY

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Rev. 3.3 - 4/29/98
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Features
n
High-speed access times
Com'l: 10, 12, 15 and 20ns
Ind'l: 12, 15 and 20ns
n
Low power operation (typical)
- PDM31256SA
Active: 200 mW
Standby: 15mW
n
Single +3.3V (
0.3V) power supply
n
TTL-compatible inputs and outputs
n
Packages
Plastic SOJ (300 mil) - SO
Plastic TSOP (I) - T
Description
The PDM31256 is a high-performance CMOS static
RAM organized as 32,768 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
The PDM31256 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
The PDM31256 is available in a 28-pin 300-mil
plastic SOJ and a 28-pin plastic TSOP (I).
A




A
0
14
I/O
I/O
0
7
CE
WE
Addresses
Decoder
Memory
Matrix
Input
Data
Control
Column I/O
OE
Control
Functional Block Diagram
PDM31256
3.3V 256K Static RAM
32K x 8-Bit
PDM31256
2
Rev. 3.3 - 4/29/98
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A1
A2
22
23
24
25
26
27
28
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
21
22
23
24
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
Vcc
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
13
14
25
26
27
28
Truth Table
NOTE: 1. H = V
IH
, L = V
IL
, X = DON'T CARE
Absolute Maximum Ratings
(1)
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form
: T
j
= T
a
+ P *
ja
where T
a
is the ambient tempera-
ture, P is average operating power and
ja
the thermal resistance of the package. For
this product, use the following
ja
values:
SOJ: 78
o
C/W
TSOP: 112
o
C/W
OE
WE
CE
I/O
MODE
X
X
H
Hi-Z
Standby
L
H
L
D
OUT
Read
X
L
L
D
IN
Write
H
H
L
Hi-Z
Output Disable
Symbol
Rating
Com'l.
Ind.
Unit
V
TERM
Terminal Voltage with Respect to Vss
0.5 to +4.6
0.5 to +4.6
V
T
BIAS
Temperature Under Bias
55 to +125
65 to +135
C
T
STG
Storage Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
1.0
1.0
W
I
OUT
DC Output Current
50
50
mA
T
j
Maximum Junction Temperature
(2)
125
145
C
Pin Configurations
TSOP
SOJ
Pin Description
Name
Description
A14-A0
Address Inputs
I/O7-I/O0
Data Inputs/Outputs
OE
Output Enable Input
WE
Write Enable Input
CE
Chip Enable Input
V
CC
Power (+3.3V)
V
SS
Ground
PDM31256
Rev. 3.3 - 4/29/98
3
1
2
3
4
5
6
7
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9
10
11
12
Recommended DC Operating Conditions
DC Electrical Characteristics
(V
CC
= 3.3V
0.3V)
NOTE:1.V
IL
(min) = 3.0V for pulse width less than 20 ns.
Power Supply Characteristics
NOTES: All values are maximum guaranteed values.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
V
SS
Supply Voltage
0
0
0
V
Commercial
Ambient Temperature
0
25
70
C
Industrial
Ambient Temperature
40
25
85
C
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
LI
Input Leakage Current
V
CC
= MAX., V
IN
= Vss to V
CC
5
5
A
I
LO
Output Leakage Current
V
CC
= MAX.,
CE = V
IH
, V
OUT
=
Vss to V
CC
5
5
A
V
IL
Input Low Voltage
0.3
(1)
0.8
V
V
IH
Input High Voltage
2.2
Vcc+0.3
V
V
OL
Output Low Voltage
I
OL
= 8 mA
V
CC
= Min.
--
0.4
V
V
OH
Output High Voltage
I
OH
= 4 mA,
V
CC
= Min.
2.4
--
V
-10
-12
-15
-17
-20
Symbol Parameter
Com'l. Com'l
Ind.
Com'l
Ind.
Com'l
Ind.
Com'l
Ind.
Unit
I
CC
Operating Current
CE = V
IL
140
130
130
120
120
120
120
110
110
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
45
40
35
35
35
35
35
30
30
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
V
CC
0.2V
10
10
15
10
15
10
15
10
15
mA
f = 0
V
CC
= Max.,
V
IN
V
CC
0.2V or
0.2V
PDM31256
4
Rev. 3.3 - 4/29/98
Capacitance
(1)
(T
A
= +25
C, f = 1.0 MHz)
NOTE: 1. This parameter is determined by device characterization but is not production
tested.
AC Test Conditions
Symbol
Parameter
Max.
Unit
C
IN
Input Capacitance
8
pF
C
OUT
Output Capacitance
8
pF
Input pulse levels
V
SS
to 3.0V
Input rise and fall times
2.5 ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
,
t
HZOE
)
353
319
30 pF
+3.3V
DATA
OUT
353
319
5 pF
+3.3V
DATA
OUT
5
4
3
2
1
0
0
30
60
90
120
Typical Delta tAA vs Capacitive Loading
Additional Lumped Capacitive Loading (pF)
Delta t
AA
- ns
Figure 3.
PDM31256
Rev. 3.3 - 4/29/98
5
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Read Cycle No. 1
(1)
Read Cycle No. 2
(2)
AC Electrical Characteristics
Description
-10
-12
-15
-17
-20
READ Cycle
Sym
Min. Max. Min. Max. Min. Max. Min
Max
Min
Max
Units
READ cycle time
t
RC
10
12
15
17
20
ns
Address access time
t
AA
10
12
15
17
20
ns
Chip enable access time
t
ACE
10
12
15
17
20
ns
Output hold from address change
t
OH
3
3
3
3
3
ns
Chip enable to output in low Z
(3,4,5)
t
LZCE
5
5
5
5
5
ns
Chip disable to output in high Z
(3,4,5)
t
HZCE
8
10
10
12
15
ns
Chip enable to power up time
(4)
t
PU
0
0
0
0
0
ns
Chip disable to power down time
(4)
t
PD
10
12
15
17
20
ns
Output enable access time
t
AOE
5
6
8
9
10
ns
Output enable to output in low Z
(4,5)
t
LZOE
0
0
0
0
0
ns
Output disable to output in high Z
(4,5)
t
HZOE
8
8
8
8
8
ns
tRC
tAA
tOH
PREVIOUS DATA VALID
DOUT
ADDR
DATA VALID
t
RC
t
ACE
t
AA
t
LZCE
t
HZCE
t
LZOE
t
HZOE
t
AOE
ADDR
CE
OE
D
OUT
DATA VALID
PDM31256
6
Rev. 3.3 - 4/29/98
Write Cycle No. 1 (Write Enable Controlled)
Write Cycle No. 2 (Chip Enable Controlled)
AC Electrical Characteristics
Description
-10
-12
-15
-17
-20
WRITE Cycle
Sym
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
WRITE cycle time
t
WC
10
12
15
17
20
ns
Chip enable to end of write
t
CW
10
10
12
12
13
ns
Address valid to end of write
t
AW
10
10
12
12
13
ns
Address setup time
t
AS
0
0
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
0
0
ns
Write pulse width
t
WP
8
10
11
11
12
ns
Data setup time
t
DS
7
7
7
8
9
ns
Data hold time
t
DH
0
0
0
0
0
ns
Write disable to output in low Z
(4,5)
t
LZWE
0
0
0
0
0
ns
Write enable to output in high Z
(4,5)
t
HZWE
3
3
3
3
3
ns
tWC
t AW
t CW
t AH
tAS
t HZWE
HIGH Z
DATA VALID
tLZWE
t DS
t DH
ADDR
CE
t WP
WE
DIN
DOUT
tWC
t AW
tCW
t WP
t DS
DATA VALID
t DH
tAS
ADDR
DIN
UNDEFINED
DON'T CARE
t AH
CE
WE
PDM31256
Rev. 3.3 - 4/29/98
7
1
2
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8
9
10
11
12
NOTES: (For two previous Electrical Characteristics tables)
1. The device is continuously selected. Chip Enable is held in its active state.
2. The address is valid prior to or coincident with the latest occuring Chip Enable.
3. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
.
4. This parameter is sampled.
5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured
200 mV from steady state voltage.
Ordering Information
Device Type
Power
Speed
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Commercial (0
to +70
C)
Industrial (40
C to +85
C)
10
Commercial Only
12
15
17
20
SA
Standard Power
Blank
I
A
Automotive ( 40
C to +105
C)
Blank Tubes
TR Tape & Reel
TY Tray
PDM31256 - 256K (32Kx8) Sync. Static RAM
XXXXX
X
XX
X
X
X
SO
28-pin 300-mil Plastic SOJ
T
28-pin Plastic TSOP (I)
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