Suites 2202-7, Tower 6, The Gateway,
9 Canton Road, Tsimshatsui,
Kowloon, Hong Kong
Tel: (852) 2123 3289 Fax: (852) 2123 3393
E-mail: sales@jesstech.com
Home Page: www.jesstech.com

HF88M02

Command Interface 2M-Bit Mask ROM with Expansion I/O

-1-

02/05/31

Product Name

Command Interface 2 M-Bit Mask ROM with Expansion I/O

Jtech Doc. No.

HF88M02

Jtech Product. No.

HF88M02

Table of Contents �

FUNCTION DESCRIPTION ...................................................................................................... 2

FEATURES ................................................................................................................................... 2

FUNCTIONAL BLOCK DIAGRAM ......................................................................................... 3

4 PIN DESCRIPTION..................................................................................................................... 4

4.1

OCATION

.................................................................................................................. 5

4.2

OORDINATION

.......................................................................................................... 6

DEVICE OPERATION ................................................................................................................ 7

5.1

ETRIEVE DATA IN

ATA

ILE

........................................................................................... 8

5.2

OADING THE

DDRESS

OUNTER

.................................................................................... 9

5.3

EQUENTIAL

EAD

ODE AND

UTO

NCREMENT OF

DDRESS

OUNTER

...................... 9

5.4

UTPUT DATA TO

XTERNAL

I/O..................................................................................... 10

5.5

EADING

NPUT PIN STATUS

............................................................................................. 10

5.6

ETRIEVING THE

ONTENTS OF

XPANSION

I/O

REGISTERS

............................................ 10

TIMING DIAGRAMS................................................................................................................ 11

ATA

ILE

EAD

YCLE

..................................................................................................................... 11

6.2

NTERRUPTED BY

I/O

WHEN

OADING

DDRESS

OUNTER

............................................ 11

6.3

ETTING AND

EADING THE

I/O M

ODE FOR

AND

P1 .................................................. 12

6.4

EADING

AND

IXED

-I/O M

ODE

..................................................................... 12

6.5

EADING THE INPUT PINS

................................................................................................ 12

6.6

UTPUT TO

AND

P1 .................................................................................................... 13

ABSOLUTE MAXIMUM RATING........................................................................................ 144

AC ELECTRICAL CHARACTERISTICS.............................................................................. 14

DC ELECTRICAL CHARACTERISTICS.............................................................................. 15

APPLICATION CIRCUIT DIAGRAM............................................................................... 15

Suites 2202-7, Tower 6, The Gateway,
9 Canton Road, Tsimshatsui,
Kowloon, Hong Kong
Tel: (852) 2123 3289 Fax: (852) 2123 3393
E-mail: sales@jesstech.com
Home Page: www.jesstech.com

HF88M02

Command Interface 2M-Bit Mask ROM with Expansion I/O

-2-

02/05/31

Function Description

The HF88M02is a command interfaced 256K x 8 bit Mask ROM. It features command mode
interface with external CPU or MCU. In other words, it uses only 8-bit data bus and a few
additional control pins to load addresses and provide the ROM access as well as expansion I/O
ports capability. This design not only reduces pin count required to access data in ROM
dramatically but also allows for systems expansion to higher capacity memories while using the
existing board design. The application areas include voice, graphic, data storage in consumer
product.

Features

Data File Mode with only 11 pin interface

Sixteen-bit Expansion I/O pins with three-state mode

Voltage range 2.4V ~ 5.5V

Organization

Memory Cell Array: 256K x 8

Sequential Read Operation in Data File Operation Mode

Sequential Access : 120ns (min.) at V

= 5.0V

Command/Address/Data Multiplexed I/O port

Low Operation Current (Typical)

�

A Standby mode Current

10mA Active Read Current

Package bare chip, PLCC32

Suites 2202-7, Tower 6, The Gateway,
9 Canton Road, Tsimshatsui,
Kowloon, Hong Kong
Tel: (852) 2123 3289 Fax: (852) 2123 3393
E-mail: sales@jesstech.com
Home Page: www.jesstech.com

HF88M02

Command Interface 2M-Bit Mask ROM with Expansion I/O

-4-

02/05/31

Pin Description

Symbol

Pin No. I/O

Description

VDD

P Positive power supply input pin.

VSS

P Gound pin.

CEn

The CEn (Chip Enable) input is the device selection and
power control for internal Mask ROM array. Whenever
CEn goes high, the internal Mask ROM will enter standby
(power saving) mode and accesses to internal registers are
inhibited. Otherwise, it is in active mode and the
contents of the ROM and registers can be accessed.
Please note that only accesses to the internal registers are
inhibited, but the status of I/O registers are not affected by
the CEn pin and will remain unchanged. CEn is also
useful to uniquely select a certain device for applications
where multiple-chip array is required.

WEn

WEn controls writing to internal registers such as the
Output Port Registers, Direction Registers, Address
Counter and Data on D7 ~ D0 are latched on the rising
edge of the WE pulse. The WEn (Write Enable) input is
internally pulled-up to VDD to prevent pin floating. So
this pin should stay at `1' state when inactive to prevent
unintended current consumption.

OEn

OEn (Output Enable) is the output control which gates
ROM array data, expansion I/O ports, Direction Registers
to the data I/O pins D7 ~ D0. The internal Address
Counter will automatically increment by one with each
rising edge of OEn pin in Sequentially Read mode.

HF88M02-PLCC32

29
28

14 15

18 19

P01

P02

P03

P04

P05

P06

P07

P16

P15

P10

P12

P13

D1 D2

D4 D5

P00

P11

Suites 2202-7, Tower 6, The Gateway,
9 Canton Road, Tsimshatsui,
Kowloon, Hong Kong
Tel: (852) 2123 3289 Fax: (852) 2123 3393
E-mail: sales@jesstech.com
Home Page: www.jesstech.com

HF88M02

Command Interface 2M-Bit Mask ROM with Expansion I/O

-5-

02/05/31

RS2~RS0

Register Select pins RS2 ~ RS0 for accessing ROM data,
Address Counter, as well as expansion I/O ports. The RS2
(Register Select) input is internally pulled-down to
Ground. So this pin should stay at `0' state when
inactive to prevent unintended current drain.

P17 ~ P10

I/O Bi-directional I/O port P1.

P07 ~ P00

I/O Bi-directional I/O port P0.

D7 ~ D0

21 ~ 17,

15 ~13

IO The Bi-directional Data I/O pins are used to input Starting

Address, setting the Expansion I/O direction and Output
Registers, and to output ROM array data during read
operations, contents of I/O Registers and status of input
pins. The D7 ~ D7 float to high-impedance when the chip
is deselected (CEn high) or when the outputs are disabled.

4.1

Pad Location

VSS

RS0

P00

CEN

P04

WEN

P05

VDD

P12

P01

P10

P16

P06

P14

OEN

P07

VDD

VSS

P17

P15

P11

P03

RS1

RS2

P13

VDD

P02

VSS

Электронный компонент: HF88M02