Suites 2202-7, 22/F, Tower 6, The Gateway,
9 Canton Road, Tsimshatsui,
Kowloon, Hong Kong
Tel (852) 2123 3289
Fax (852) 2123 3393
E-mail: sales@jesstech.com
HomePage: http://www.jesstech.com
WT65F4
USB
C with 8KB ISP
Flash memory & 12bit
ADC
V1.0
1
WT65F4
USB uC with 8KB ISP Flash Memory
12-bit A/D Converter
Data Sheet
REV.1.00
Nov.18, 2001
The information in this document is subject to change without notice.
Suites 2202-7, 22/F, Tower 6, The Gateway,
9 Canton Road, Tsimshatsui,
Kowloon, Hong Kong
Tel (852) 2123 3289
Fax (852) 2123 3393
E-mail: sales@jesstech.com
HomePage: http://www.jesstech.com
WT65F4
USB
C with 8KB ISP
Flash memory & 12bit
ADC
V1.0
2
Table of Content
1.
GENERAL DESCRIPTION............................................................................................................................1
2.
FEATURES......................................................................................................................................................1
3.
PACKAGE INFORMATION...........................................................................................................................2
4.
PIN ASSIGNMENT AND DESCRIPTION....................................................................................................3
4.1
PIN CONFIGURATION..................................................................................................................................5
5.
FUNCTION DESCRIPTION ..........................................................................................................................7
5.1
WT65F4 USB MODULE ................................................................................................................................7
5.2
MICROCONTROLLER ..................................................................................................................................9
5.3
ANALOG TO DIGITAL CONVERTER ( ADC )...........................................................................................11
5.4
PULSE WIDTH MODULATION( PWM ) .....................................................................................................13
5.5
ADPCM PUSH-PULL D/A.............................................................................................................................13
5.6
WT65F4 ADDRESS SPACE MAPPING........................................................................................................14
5.7
WT65F4 SPECIAL FUNCTION REGISTER ADDRESS SPACE ................................................................14
5.8
EXTERNAL FUNCTION REGISTER ADDRESS SPACE...........................................................................16
5.9
CLOCK UNIT .................................................................................................................................................17
5.10 RESET .............................................................................................................................................................19
5.11 POWERDOWN MODE AND IDLE MODE..................................................................................................19
5.12 INTERRUPT....................................................................................................................................................20
5.13 FUNCTION ENDPOINT ................................................................................................................................22
5.14 TRANSMIT FIFOS .........................................................................................................................................22
5.15 TRANSMIT FIFOS FEATURES ....................................................................................................................22
5.16 TRANSMIT DATA SET MANAGEMENT....................................................................................................23
5.17 TRANSMIT FIFO REGISTERS .....................................................................................................................24
5.18 RECEIVE FIFOS.............................................................................................................................................24
5.19 RECEIVE FIFO FEATURES ..........................................................................................................................24
5.20 RECEIVE DATA SET MANAGEMENT .......................................................................................................25
5.21 RECEIVE FIFO REGISTERS.........................................................................................................................26
5.22 SETUP TOKEN RECEIVE FIFO HANDLING .............................................................................................27
5.23 SUSPEND AND RESUME.............................................................................................................................27
5.24 ISP MODE .......................................................................................................................................................29
5.25 ICE MODE ......................................................................................................................................................29
5.26 NORMAL DOWNLOAD MODE...................................................................................................................29
6.
EXTERRNAL FUNCTION REGISTERS ......................................................................................................30
7.
TRAGERT AC AND DC SPECIFICATION...................................................................................................66
Suites 2202-7, 22/F, Tower 6, The Gateway,
9 Canton Road, Tsimshatsui,
Kowloon, Hong Kong
Tel (852) 2123 3289
Fax (852) 2123 3393
E-mail: sales@jesstech.com
HomePage: http://www.jesstech.com
WT65F4
USB
C with 8KB ISP
Flash memory & 12bit
ADC
V1.0
3
Index of Figures
Figure 1. WT65F4 40-pin DIP & 28-pin SOP / DIP package.................................................................................5
Figure 2. WT65F4 48-pin QFP package .................................................................................................................6
Figure 3. WT65F4 4General Block Diagram..........................................................................................................7
Figure 4. USB Interface Block Diagram .................................................................................................................9
Figure 5. Memory mapping of Flash ROM, boot ROM, and ICE ROM ..............................................................11
Figure 6. ADC Interface Diagram.........................................................................................................................12
Figure 7. ADC Timing Diagram............................................................................................................................12
Figure 8. PWM Output Waveform Diagram .........................................................................................................13
Figure 9. ADPCM block diagram .........................................................................................................................14
Figure 10. Clock circuit when USB function is used ............................................................................................18
Figure 11. Clock divided-by-2 circuit ...................................................................................................................19
Figure 12. Reset Signals........................................................................................................................................19
Figure 13. Block Diagram of INT0 .......................................................................................................................21
Figure 14. WT65F4 interrupt circuit .....................................................................................................................21
Figure 15. Transmit FIFO outline..........................................................................................................................22
Figure 16. Receive FIFO Outline ..........................................................................................................................25
Figure 17. Suspend and Resume State Diagram ...................................................................................................28
Figure 18. Port 2 circuit diagram...........................................................................................................................47
Figure 19. External Clock Drive Waveform..........................................................................................................67
Suites 2202-7, 22/F, Tower 6, The Gateway,
9 Canton Road, Tsimshatsui,
Kowloon, Hong Kong
Tel (852) 2123 3289
Fax (852) 2123 3393
E-mail: sales@jesstech.com
HomePage: http://www.jesstech.com
WT65F4
USB
C with 8KB ISP
Flash memory & 12bit
ADC
V1.0
4
Index of Tables
Table 1. WT65F4 Package Types ............................................................................................................................2
Table 2. Pin Descriptions.........................................................................................................................................3
Table 3. ADC Interface Description......................................................................................................................12
Table 4. Addressing mapping ................................................................................................................................14
Table 5. WT65F4 Special Function Register ( SFR ) layout.................................................................................15
Table 6. External Function Register ( XFR ) layout..............................................................................................16
Table 7. Internal clock generation map .................................................................................................................17
Table 8. Writing to the Byte Count Register .........................................................................................................23
Table 9. Truth table for transmit FIFO management.............................................................................................24
Table 10. Status of the receive FIFO data set........................................................................................................26
Table 11. Truth table for receive FIFO management.............................................................................................26
Table 12. Function Address Register ( FADDR, 00H ).........................................................................................30
Table 13. USB Interrupt Register ( USBI, 01H ) ..................................................................................................31
Table 14. USB / Key board / AD Interrupt Enable Register ( USBKAIIE, 02H ) ................................................32
Table 15. USB SIE Interface Register ( SIE1, 03H ) ............................................................................................33
Table 16. Endpoint Index Register ( EPINDEX, 05H ) ........................................................................................34
Table 17. Endpoint Control Register ( EPCON, 06H ) .........................................................................................35
Table 18. Speaker / Watch-dog Timer Control Register ( SPWDCTL, 07H ) ......................................................37
Table 19. Transmit FIFO Data Register ( TXDAT, 08H ) .....................................................................................38
Table 20. Transmit FIFO Control Register ( TXCON, 09H ) ...............................................................................39
Table 21. Transmit FIFO Flag Register ( TXFLG, 0AH ) ....................................................................................40
Table 22. Transmit FIFO Byte Count Register (TXCNT, 0BH ) ..........................................................................42
Table 23. Endpoint Transmit Status Register ( TXSTAT, 0CH )...........................................................................43
Table 24. PWM0 Duty Control Register ( PWM0, 0DH ) ....................................................................................45
Table 25. PWM1 Duty Control Register ( PWM1, 0EH ).....................................................................................46
Table 26. Port2 Current Control Register ( P2ODCTL, 0FH ) .............................................................................47
Table 27. ISP program control Register ( ISP_CTL, 11H ) ..................................................................................48
Table 28. ISP Address low byte Register ( ISPADDL, 12H ) ...............................................................................49
Table 29. ISP Address high byte Register ( ISPADDH, 13H ) .............................................................................50
Table 30. ISP program data Register ( ISPDATA, 14H ) ......................................................................................51
Table 31. AD / PWM function control Register ( ADPWM_C, 15H ) .................................................................52
Table 32. ADC Clock Control Register ( ADCLK, 16H ) ....................................................................................53
Table 33. Kay borad / AD Interrupt Register ( KYADI, 17H ) .............................................................................54
Table 34. Receive FIFO Data Register ( RXDAT, 18H ) ......................................................................................55
Table 35. Receive FIFO Control Register ( RXCON, 19H ).................................................................................56
Table 36. Receive FIFO Flag Register ( RXFLG, 1AH )......................................................................................57
Suites 2202-7, 22/F, Tower 6, The Gateway,
9 Canton Road, Tsimshatsui,
Kowloon, Hong Kong
Tel (852) 2123 3289
Fax (852) 2123 3393
E-mail: sales@jesstech.com
HomePage: http://www.jesstech.com
WT65F4
USB
C with 8KB ISP
Flash memory & 12bit
ADC
V1.0
5
Table 37. Receive FIFO Byte Count Register ( RXCNT, 1BH )...........................................................................59
Table 38. Endpoint Receive Status Register ( RXSTAT, 1CH )............................................................................60
Table 39. ADC Lower Byte Data Register ( ADL, 1DH ) ....................................................................................63
Table 40. ADC Higer Byte Data Register ( ADH, 1EH )......................................................................................64
Table 41. Push-pull DA speaker output envelope ( SPKENV0, 10H ) .................................................................65
Table 42. Push-pull DA speaker output envelope ( SPKENV1, 1FH ).................................................................65
Table 43. DC Electrical Characteristics.................................................................................................................66
Table 44. Absolute Maximum Rating ...................................................................................................................67
Table 45. AC Electrical Characteristics...................................................................................................................6
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