King Billion Electronics Co., Ltd

HE847721

HE80000 SERIES

April 29, 2003

Page 1 of 29

V1.0

This specification is subject to change without notice. Please contact sales person for the latest version before use.

- Table of Contents -

General Description ___________________________________________________________________1

Features _____________________________________________________________________________2

Functional Block Diagram______________________________________________________________3

Pin Description _______________________________________________________________________3

Pad Location _________________________________________________________________________6

LCD RAM Map ______________________________________________________________________8

LCD Power Supply___________________________________________________________________11

7.1.

LCDC Control register _____________________________________________________________14

Oscillators __________________________________________________________________________14

General Purpose I/O__________________________________________________________________16

10.

Key Scan Circuit___________________________________________________________________18

11.

Timer1 ___________________________________________________________________________19

12.

Timer2 ___________________________________________________________________________20

13.

Time Base Interrupt________________________________________________________________22

14.

Watch Dog Timer __________________________________________________________________22

15.

Digital-to-Analog Converter _________________________________________________________23

16.

Pulse-Width Modulation ____________________________________________________________24

17.

Low Voltage Detection ______________________________________________________________25

18.

Absolute Maximum Rating __________________________________________________________25

19.

Recommended Operating Conditions _________________________________________________25

20.

AC/DC Characteristics _____________________________________________________________26

21.

Application Circuit_________________________________________________________________27

22.

Important Note ____________________________________________________________________28

23.

Updated Record ___________________________________________________________________29

1. General Description

HE847721 is a member of 8-bit Micro-controller series developed by King Billion Electronics. Four LCD
driver configurations, 32 COM x 128 SEG, 48 COM x 112 SEG, 64 COM x 96 SEG or 80 COM x 80

King Billion Electronics Co., Ltd

HE847721

HE80000 SERIES

April 29, 2003

Page 2 of 29

V1.0

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SEG are available by mask option. 24 LCD segment driver pins multiplexed with I/O pins to provide
flexibility of wide variety of combinations to suit the needs of applications. The built-in LCD power
supply is equipped with voltage charge-pump circuit to generate the high voltage required by the high
duty LCD driver, bias voltage generating circuit and input voltage regulator circuit to supply stable LCD
display effect over the wide battery life. The built-in OP comparator can be used with (light, voice,
temperature, humility) sensor and used as battery low detection. 7-bit current-type D/A converter and
PWM device provide the complete speech output mechanism. The 512 KB ROM Size can be used in the
storage of speech, graphic, text, etc. It is ideal for applications such as Translator, Data Bank, Educational
Toy, Digital Voice Recording System, etc.

The instruction set of HE80000 series is easy to learn and simple to use. Only about thirty instructions
with four-type addressing mode are provided. Most of instructions take only 3 oscillator clocks to execute.
The processing power is enough to most of battery operation system.

2. Features

Operation Voltage:

2.4V ~ 3.6V

System Clock:

DC ~ 8 MHz @ 3.6V

DC ~ 4 MHz @ 2.4V

Internal ROM:

512K Bytes (256 KB Program ROM + 256 KB Data ROM)

Internal RAM:

16K Bytes

Dual Clock System: Fast clock:

32768 ~ 8M Hz (No Internal Clock)

Slow clock: 32768 Hz

Operation modes:

Fast, Slow, Idle and Sleep modes.

24 ~ 48 bit bi-directional general purpose I/O port with push-pull or Open-Drain output type

selectable for each I/O pin by mask option. 24 of them are multiplexed with LCD segment
pins.

Built-in 4x20 hardware keyboard scan circuit (multiplexed with LCD SEG pin) helps to

reduce the pin counts as well as the firmware effort.

Voltage Detector with two detecting thresholds.
Four LCD configurations: 32 COM x 128 SEG, 48 COM x 112 SEG, 64 COM x 96 SEG or

80 COM x 80 SEG. All of LCD configurations are B TYPE.

Built-in LCD power supply with input voltage regulator, voltage charge pump and bias

voltage generating circuit.

One 7-bit current-type DAC output.
Single-ended Pulse Width Modulation circuit for alternative voice output.
Built-in OP comparator.
Two 16-bit timers and one Time-Base timer.
Watch Dog Timer to prevent deadlock condition.
Two external interrupts and three internal timer interrupts.
Instruction set: 32 instructions with 4 addressing mode.

King Billion Electronics Co., Ltd

HE847721

HE80000 SERIES

April 29, 2003

Page 3 of 29

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3. Functional Block Diagram

SEG

FXI, FXO

COM

LCD

Driver

8 Bit CPU

Fast Clock

OSC.

LFR, LDL

512 KB ROM

SXI, SXO

LCD Extender

Interface

Slow Clock

OSC

16 KB RAM

LVL[1..5], LCDGS,

PWM

LCD Power

Supply

TC1

PWM

PRTC, PRTD, PRT10,

TC2

VO, DAO

PRT14, PRT15, PRT17

I/O Port

DAC

TBI

SGKY[43..24]

OPO,OPIN, OPIP

Key Scan

WDT

OP Amp

4. Pin Description

HE847721

1
2

4
5

7
8

12
13

15
16

18
19

20
21

23
24

26
27

30 31

32 33 34

35 36 37

38 39 40

41 42

43 44 45

46 47 48

49 50 51

52 53

54 55 56

57 58 59

60 61 62

63 64

65 66 67

68 69 70

71 72 73

74 75 76

77 78

79 80 81

82 83 84

85 86 87

88 89

90 91 92

93 94 95

96 97 98

99 100

101 102 103

104 105 106

107 108 109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

SEG48
SEG47

SEG46

SEG45
SEG44

SGKY43

SGKY42
SGKY41

SGKY40
SGKY39

SGKY38

SGKY37
SGKY36

SGKY35

SGKY34
SGKY33

SGKY32

SGKY31
SGKY30

SGKY29
SGKY28

SGKY27

SGKY26
SGKY25

SGKY24

PRT147
PRT146

PRT145
PRT144

1
43

1
42

1
41

1
40

1
57

1
56

1
55

1
54

1
53

1
52

1
51

1
50

1
77

1
76

1
75

1
74

1
73

1
72

1
71

1
70

LVL1 LVL2 LVL3

LVL4 LVL5 LC

AP4A

AP4B

AP3A

AP3B

AP2A

AP2B

AP1A

AP1B

VO DA

I
N

I
P

_
N

SXO

SXI

VDD

PRT107

PRT106

PRT105

PRT104

PRT103

PRT102

PRT101

PRT100

PRTD7

PRTD6

PRTD5

PRTD4

PRTD3

PRTD2

PRTD1

PRTD0

GND_PWM

PWM

PRTC7

PRTC6

PRTC5

PRTC4

PRTC3

PRTC2

PRTC1

PRTC0

VDD_RAM

SEG79

SEG78

SEG77

SEG76

SEG75

SEG74

SEG73

SEG72

SEG71

SEG70

SEG69

SEG68

SEG67

SEG66

SEG65

SEG64

SEG63

SEG62

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

Pin Name

Pin # I/O

Description

SEG[79..44]

188~218
, 1 ~ 5

O LCD segment SEG[79..44] driver outputs.

SGKY[43..24] 6 ~ 25 O

LCD segments share pads with key scan out SCNO[19..0]. The key scan function of
these pins can be disabled by mask option clearing MO_LCDKEY to `0', then
SGKY[43..24] function as LCD segment driver only. Setting MO_LCDKEY to `1'
will turn on the key scan function.

King Billion Electronics Co., Ltd

HE847721

HE80000 SERIES

April 29, 2003

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Pin Name

Pin # I/O

Description

PRT14[7..0] 26 ~ 33

B/
O

8-bit bi-directional I/O port 14 is shared with LCD segment pads SEG[23..16]. The
function of the pad can be selected individually by mask options MO_LIO14[7..0].
(`1' for LCD and `0' for I/O).
The output type of I/O pad can also be selected by mask option MO_14PP[7..0] (1
for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the
I/O as input, "1" must be outputted before reading.

PRT15[7..0] 34 ~ 41

B/
O

8-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[16..8]. The
function of the pad can be selected individually by mask options MO_LIO15[7..0].
(`1' for LCD and `0' for I/O).
The output type of I/O pad can also be selected by mask option MO_15PP[7..0] (1
for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the
I/O as input, "1" must be outputted before reading.

PRT17[7..0] 42 ~ 49

B/
O

8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[7..0]. The
function of the pad can be selected individually by mask options MO_LIO17[7..0].
(`1' for LCD and `0' for I/O).
The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1
for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the
I/O as input, "1" must be outputted before reading.

COM[31..0] 50 ~ 81 O LCD COMMON Driver pads.
LVL1

B LCD Bias Voltage 1

LVL2

B LCD Bias Voltage 2

LVL3

B LCD Bias Voltage 3

LVL4

B LCD Bias Voltage 4

LVL5

B LCD Bias Voltage 5

LCAP4A

B Charge Pump Capacitor Pin

LCAP4B 88 B

Charge Pump Capacitor Pin.

LCAP3A

B Charge Pump Capacitor Pin

LCAP3B

B Charge Pump Capacitor Pin

LCAP2A

B Charge Pump Capacitor Pin

LCAP2B

B Charge Pump Capacitor Pin

LCAP1A 93 B

Charge Pump Capacitor Pin

LCAP1B 94 B

Charge Pump Capacitor Pin

LCDGS

B LCD Voltage setting. Adjust Resistor between LCDGS and LVL2 to set LVL5.

LCDVX

B Charge Pump Capacitor Pin

LCDVTB 97 B

Charge Pump Capacitor Pin

LFR 98

LCD frame signal for interfacing with LCD segment extender KDS80.

LDL 99

LCD data load pin for interfacing with LCD segment extender KDS80.

GND

100

P Power ground Input.

VO 101

DAC Voice Output. Set the bit 1 and clear the bit 0 of VOC (DA = `1' and OP = `0')
register to turn on DAC with VO output.

DAO 102

Alternate output of DAC. Set both bit 1 and bit 0 of VOC register (DA = `1' and OP
= `1') to turn on DAC with DAO output as well as OP comparator.

OPIN 103

Inverting input of OP Amp. Set the bit 0 of VOC register (OP = `1') to turn on OP
comparator.

OPIP

104

Non-inverting input of OP Amp.

OPO

105

O Output of OP Amp.

RSTP_N 106 I

System Reset input pin. Level trigger, active low on this pin will put the chip in reset
state.

FXO,

107, 108 O, External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (`0'

King Billion Electronics Co., Ltd

HE847721

HE80000 SERIES

April 29, 2003

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Pin Name

Pin # I/O

Description

FXI

B for RC type and `1' for crystal type). For RC type oscillator, one resistor need to be

connected between FXI and GND. For crystal oscillator, one crystal need to be
placed between FXI and FXO. Please refer to application circuit for details.

TSTP_P 109

Test input pin. Please bond this pad and reserve a test point on PCB for debugging.
But for improving ESD, please connect this point with zero Ohm resistor to GND

SXO,
SXI

110, 111

O,
I

External slow clock pins. Slow clock is clock source for LCD display, TIMER1,
Time-Base and other internal blocks. Both crystal and RC oscillator are provided.
The slow clock type can be selected by mask option MO_SXTAL. Choose `0' for RC
type and `1' for crystal oscillator.

VDD 112

Positive power Input. 0.1 �F decoupling capacitors should be placed as close to IC
VDD and GND pads as possible for best decoupling effect.

PRT10[7..0] 113~120

8-bit bi-directional I/O port 10. The output type of I/O pad can be selected by mask
option MO_10PP[7..0] (`1' for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the
I/O pad as input pad, "1" must be outputted before reading.

PRTD[7..0] 121~128

8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by
mask option MO_DPP[7..0] (`1' for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the
I/O as input, `1' must be outputted before reading the pin.
PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt
sources.

GND_PWM 129

O Dedicated Ground for PWM output.

PWM 130

The PWM output can drive speaker or buzzer directly. Set the bit2 of VOC register
as one to turn on PWM. Using VDD & PWM to drive output device.

PRTC[7..0]

131 ~
138

8-bit bi-directional I/O port C. PRTC[7:4] is shared with Key Scan Dedicated Input
SCNI[3:0]. The Key Scan function can be disabled by clearing MO_LCDKEY mask
option to `0'.
The output type of I/O pad can also be selected by mask option MO_CPP[7..0] (`1'
for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the
I/O as input, `1' must be outputted before reading the pin.

VDD_RAM 139

P Dedicated power input for RAM

CMSG[32..79] 140~187 O

COM[32..79] pads are shared with SEG[127..80] outputs. The functions of the pads
to be COM drivers or SEG drivers can be selected by mask option MO_COM[0].
Please refer to LCD driver configuration for details.

I: Input, O: Output, B: Bidirectional, P: Power.

King Billion Electronics Co., Ltd

HE847721

HE80000 SERIES

April 29, 2003

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V1.0

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5. Pad Location

Pin No.

Pin name

X Coord. Y-Coord. Pin No.

Pin name

X Coord. Y-Coord.

1 SEG[48]

-4652.4

1615.02

110

SXO

4637.6

-1693.22

2 SEG[47]

-4652.4

1500.02

111

SXI

4637.6

-1578.22

3 SEG[46]

-4652.4

1385.02

112 VDD

4637.6 -1458.22

4 SEG[45]

-4652.4

1270.02

113

PRT10[7]

4637.6

-1343.22

5 SEG[44]

-4652.4

1155.02

114

PRT10[6]

4637.6

-1228.22

6 SGKY[43]

-4652.4

1040.02

115

PRT10[5]

4637.6

-1113.22

7 SGKY[42]

-4652.4

925.02

116

PRT10[4]

4637.6

-998.22

8 SGKY[41]

-4652.4

810.02

117

PRT10[3]

4637.6

-883.22

9 SGKY[40]

-4652.4

695.02

118

PRT10[2]

4637.6

-768.22

10 SGKY[39]

-4652.4

580.02

119

PRT10[1]

4637.6 -653.22

11 SGKY[38]

-4652.4

465.02

120

PRT10[0]

4637.6 -538.22

12 SGKY[37]

-4652.4

350.02

121

PRTD[7]

4637.6 -423.22

13 SGKY[36]

-4652.4

235.02

122

PRTD[6]

4637.6 -308.22

14 SGKY[35]

-4652.4

120.02

123

PRTD[5]

4637.6 -193.22

15 SGKY[34]

-4652.4

5.02

124

PRTD[4]

4637.6 -78.22

16 SGKY[33]

-4652.4

-109.98

125

PRTD[3]

4637.6 36.79

17 SGKY[32]

-4652.4

-224.98

126

PRTD[2]

4637.6 151.79

18 SGKY[31]

-4652.4

-339.98

127

PRTD[1]

4637.6 266.79

19 SGKY[30]

-4652.4

-454.98

128

PRTD[0]

4637.6 381.79

20 SGKY[29]

-4652.4

-569.98

129

GND_PWM 4637.6 496.79

21 SGKY[28]

-4652.4

-684.98

130

PWM

4637.6 621.74

22 SGKY[27]

-4652.4

-799.98

131

PRTC[7]

4637.6 744.24

23 SGKY[26]

-4652.4

-914.98

132

PRTC[6]

4637.6 859.24

24 SGKY[25]

-4652.4

-1029.98

133

PRTC[5]

4637.6 974.24

25 SGKY[24]

-4652.4

-1144.98

134

PRTC[4]

4637.6

1089.24

26 PRT14[7]

-4652.4

-1259.98

135

PRTC[3]

4637.6

1204.24

27 PRT14[6]

-4652.4

-1374.98

136

PRTC[2]

4637.6

1319.24

28 PRT14[5]

-4652.4

-1489.98

137

PRTC[1]

4637.6

1434.24

King Billion Electronics Co., Ltd

HE847721

HE80000 SERIES

April 29, 2003

Page 7 of 29

V1.0

This specification is subject to change without notice. Please contact sales person for the latest version before use.

Pin No.

Pin name

X Coord. Y-Coord. Pin No.

Pin name

X Coord. Y-Coord.

29 PRT14[4]

-4652.4

-1604.98

138

PRTC[0]

4637.6

1549.24

30 PRT14[3]

-4505.17

-1997.5

139 VDD_RAM

4630.6 1997.5

31 PRT14[2]

-4390.17

-1997.5

140

CMSG[32]

4477.6 1997.5

32 PRT14[1]

-4259.9

-1997.5

141

CMSG[33]

4362.6 1997.5

33 PRT14[0]

-4144.9

-1997.5

142

CMSG[34]

4247.6 1997.5

34 PRT15[7]

-4029.9

-1997.5

143

CMSG[35]

4132.6 1997.5

35 PRT15[6]

-3914.9

-1997.5

144

CMSG[36]

4017.6 1997.5

36 PRT15[5]

-3799.9

-1997.5

145

CMSG[37]

3902.6 1997.5

37 PRT15[4]

-3684.9

-1997.5

146

CMSG[38]

3787.6 1997.5

38 PRT15[3]

-3569.9

-1997.5

147

CMSG[39]

3672.6 1997.5

39 PRT15[2]

-3454.9

-1997.5

148

CMSG[40]

3557.6 1997.5

40 PRT15[1]

-3339.9

-1997.5

149

CMSG[41]

3442.6 1997.5

41 PRT15[0]

-3224.9

-1997.5

150

CMSG[42]

3327.6 1997.5

42 PRT17[7]

-3109.9

-1997.5

151

CMSG[43]

3212.6 1997.5

43 PRT17[6]

-2994.9

-1997.5

152

CMSG[44]

3097.6 1997.5

44 PRT17[5]

-2879.9

-1997.5

153

CMSG[45]

2982.6 1997.5

45 PRT17[4]

-2764.9

-1997.5

154

CMSG[46]

2867.6 1997.5

46 PRT17[3]

-2649.9

-1997.5

155

CMSG[47]

2752.6 1997.5

47 PRT17[2]

-2534.9

-1997.5

156

CMSG[48]

2637.6 1997.5

48 PRT17[1]

-2419.9

-1997.5

157

CMSG[49]

2522.6 1997.5

49 PRT17[0]

-2304.9

-1997.5

158

CMSG[50]

2407.6 1997.5

50 COM[31]

-2189.9

-1997.5

159

CMSG[51]

2292.6 1997.5

51 COM[30]

-2074.9

-1997.5

160

CMSG[52]

2177.6 1997.5

52 COM[29]

-1959.9

-1997.5

161

CMSG[53]

2062.6 1997.5

53 COM[28]

-1844.9

-1997.5

162

CMSG[54]

1947.6 1997.5

54 COM[27]

-1729.9

-1997.5

163

CMSG[55]

1832.6 1997.5

55 COM[26]

-1614.9

-1997.5

164

CMSG[56]

1717.6 1997.5

56 COM[25]

-1499.9

-1997.5

165

CMSG[57]

1602.6 1997.5

57 COM[24]

-1384.9

-1997.5

166

CMSG[58]

1487.6 1997.5

58 COM[23]

-1269.9

-1997.5

167

CMSG[59]

1372.6 1997.5

59 COM[22]

-1154.9

-1997.5

168

CMSG[60]

1257.6 1997.5

60 COM[21]

-1039.9

-1997.5

169

CMSG[61]

1142.6 1997.5

61 COM[20]

-924.9

-1997.5

170

CMSG[62]

1027.6 1997.5

62 COM[19]

-809.9

-1997.5

171

CMSG[63]

912.6 1997.5

63 COM[18]

-694.9

-1997.5

172

CMSG[64]

797.6 1997.5

64 COM[17]

-579.9

-1997.5

173

CMSG[65]

682.6 1997.5

65 COM[16]

-444.9

-1997.5

174

CMSG[66]

567.6 1997.5

66 COM[15]

-329.9

-1997.5

175

CMSG[67]

452.6 1997.5

67 COM[14]

-214.9

-1997.5

176

CMSG[68]

337.6 1997.5

68 COM[13]

-99.9

-1997.5

177

CMSG[69]

222.6 1997.5

69 COM[12]

15.1

-1997.5

178

CMSG[70]

107.6 1997.5

70 COM[11]

130.1

-1997.5

179

CMSG[71]

-7.4 1997.5

71 COM[10]

245.1

-1997.5

180

CMSG[72]

-122.4 1997.5

72 COM[9]

360.1

-1997.5

181

CMSG[73]

-237.4 1997.5

73 COM[8]

475.1

-1997.5

182

CMSG[74]

-352.4 1997.5

74 COM[7]

590.1

-1997.5

183

CMSG[75]

-467.4 1997.5

75 COM[6]

705.1

-1997.5

184

CMSG[76]

-602.4 1997.5

76 COM[5]

820.1

-1997.5

185

CMSG[77]

-717.4 1997.5

77 COM[4]

935.1

-1997.5

186

CMSG[78]

-832.4 1997.5

78 COM[3]

1050.1

-1997.5

187

CMSG[79]

-947.4 1997.5

79 COM[2]

1165.1

-1997.5

188

SEG[79]

-1062.4 1997.5

King Billion Electronics Co., Ltd

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HE80000 SERIES

April 29, 2003

Page 8 of 29

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Pin No.

Pin name

X Coord. Y-Coord. Pin No.

Pin name

X Coord. Y-Coord.

80 COM[1]

1280.1

-1997.5

189

SEG[78]

-1177.4 1997.5

81 COM[0]

1395.1

-1997.5

190

SEG[77]

-1292.4 1997.5

82 LVL1

1510.1

-1997.5

191

SEG[76]

-1407.4 1997.5

83 LVL2

1625.1

-1997.5

192

SEG[75]

-1522.4 1997.5

84 LVL3

1740.1

-1997.5

193

SEG[74]

-1637.4 1997.5

85 LVL4

1855.1

-1997.5

194

SEG[73]

-1752.4 1997.5

86 LVL5

1970.1

-1997.5

195

SEG[72]

-1867.4 1997.5

87 LCAP4A

2085.1

-1997.5

196

SEG[71]

-1982.4 1997.5

88 LCAP4B

2200.1

-1997.5

197

SEG[70]

-2097.4 1997.5

89 LCAP3A

2315.1

-1997.5

198

SEG[69]

-2212.4 1997.5

90 LCAP3B

2430.1

-1997.5

199

SEG[68]

-2327.4 1997.5

91 LCAP2A

2545.1

-1997.5

200

SEG[67]

-2442.4 1997.5

92 LCAP2B

2660.1

-1997.5

201

SEG[66]

-2557.4 1997.5

93 LCAP1A

2775.1

-1997.5

202

SEG[65]

-2672.4 1997.5

94 LCAP1B

2890.1

-1997.5

203

SEG[64]

-2787.4 1997.5

95 LCDGS

3005.1

-1997.5

204

SEG[63]

-2902.4 1997.5

96 LCDVX

3120.1

-1997.5

205

SEG[62] -3017.4

1997.5

97 LCDVTB

3235.1

-1997.5

206

SEG[61]

-3132.4 1997.5

98 LFR

3352.34

-1997.5

207

SEG[60]

-3247.4 1997.5

99 LDL

3467.34

-1997.5

208

SEG[59]

-3362.4 1997.5

100 GND:G

3585.1

-1997.5

209 SEG[58] -3477.4

1997.5

101 VO

3700.1

-1997.5

210 SEG[57]

-3592.4 1997.5

102 DAO

3815.1

-1997.5

211 SEG[56] -3707.4

1997.5

103 OPIN

3930.1

-1997.5

212 SEG[55]

-3822.4 1997.5

104 OPIP

4045.1

-1997.5

213 SEG[54]

-3937.4 1997.5

105 OPO

4160.1

-1997.5

214 SEG[53]

-4052.4 1997.5

106 RSTP_N

4275.1

-1997.5

215 SEG[52]

-4167.4 1997.5

107 FXO

4390.1

-1997.5

216 SEG[51]

-4282.4 1997.5

108 FXI

4505.1

-1997.5

217 SEG[50]

-4397.4 1997.5

109 TSTP_P

4620.1

-1997.5

218 SEG[49]

-4512.4 1997.5

6. LCD RAM Map

There are 4 LCD configurations as determined by mask option MO_COM[1..0]. The functions of
CMSG[79..32] are different in each configuration as listed in the following table.

MO_COM[1..0] Configuration CMSG[79..64] CMSG[63..48] CMSG[47..32]

32 x 128 SEG[80..95] SEG[96..111] SEG[112..127]

48 x 112 SEG[80..95] SEG[96..111] COM[47..32]

64 x 96

SEG[80..95] COM[63..48] COM[47..32]

80 x 80

COM[79..64] COM[63..48] COM[47..32]

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CMSG32

COM32

SEG127

CMSG33

COM33

SEG126

CMSG34

COM34

SEG125

CMSG35

COM35

SEG124

CMSG36

COM36

SEG123

CMSG37

COM37

SEG122

CMSG38

COM38

SEG121

CMSG39

COM39

SEG120

CMSG40

COM40

SEG119

CMSG41

COM41

SEG118

CMSG42

COM42

SEG117

CMSG43

COM43

SEG116

CMSG44

COM44

SEG115

CMSG45

COM45

SEG114

CMSG46

COM46

SEG113

CMSG47

COM47

SEG112

CMSG48

COM48

SEG111

CMSG49

COM49

SEG110

CMSG50

COM50

SEG109

CMSG51

COM51

SEG108

CMSG52

COM52

SEG107

CMSG53

COM53

SEG106

CMSG54

COM54

SEG105

CMSG55

COM55

SEG104

CMSG56

COM56

SEG103

CMSG57

COM57

SEG102

CMSG58

COM58

SEG101

CMSG59

COM59

SEG100

CMSG60

COM60

SEG99

CMSG61

COM61

SEG98

CMSG62

COM62

SEG97

CMSG63

COM63

SEG96

CMSG64

COM64

SEG95

CMSG65

COM65

SEG94

CMSG66

COM66

SEG93

CMSG67

COM67

SEG92

CMSG68

COM68

SEG91

CMSG69

COM69

SEG90

CMSG70

COM70

SEG89

CMSG71

COM71

SEG88

CMSG72

COM72

SEG87

CMSG73

COM73

SEG86

CMSG74

COM74

SEG85

CMSG75

COM75

SEG84

CMSG76

COM76

SEG83

CMSG77

COM77

SEG82

CMSG78

COM78

SEG81

CMSG79

COM79

SEG80

64X96

80X80

COMXSEG

32X128

48X112

The RAM Maps of all four different LCD configurations are as the following:

32 COM:

Page

SEG

[7:0]

SEG

[15:8]

SEG

[23:16]

SEG

[31:24]

SEG

[39:32]

SEG

[47:40]

SEG

[55:48]

SEG

[63:56]

COM0 7E0H 7C0H 7A0H 780H 760H 740H 720H 700H
COM1 7E1H 7C1H 7A1H 781H 761H 741H 721H 701H

: : : : : : : : :

COM15

7EFH 7CFH 7AFH 78FH 76FH 74FH 72FH 70FH

COM16 7F0H 7D0H 7B0H 790H 770H 750H 730H 710H

: : : : : : : : :

COM30 7FEH 7DEH 7BEH 79EH 77EH 75EH 73EH 71EH
COM31 7FFH 7DFH 7BFH 79FH 77FH 75FH 73FH 71FH

Page

SEG

[71:64]

SEG

[79:72]

SEG

[87:80]

SEG

[95:88]

SEG

[103:96]

SEG

[111:104]

SEG

[119:112]

SEG

[127:120]

COM0 6E0H 6C0H 6A0H 680H 660H 640H 620H 600H
COM1 6E1H 6C1H 6A1H 681H 661H 641H 621H 601H

: : : : : : : : :

COM15

6EFH 6CFH 6AFH 68FH 66FH 64FH 62FH 60FH

COM16 6F0H 6D0H 6B0H 690H 670H 650H 630H 610H

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: : : : : : : : :

COM30 6FEH 6DEH 6BEH 69EH 67EH 65EH 63EH 61EH
COM31 6FFH 6DFH 6BFH 69FH 67FH 65FH 63FH 61FH

48 COM:

Page 7,6

SEG[7:0] SEG[15:8] SEG[23:16] SEG[31:24] SEG[39:32] SEG[47:40] SEG[55:48]

COM0 7C0H 780H 740H 700H 6C0H 680H 640H
COM1 7C1H 781H 741H 701H 6C1H 681H 641h

: : : : : : : :

COM15

7CFH 78FH 74FH 70FH 6CFH 68FH 64FH

COM16

7D0H 790H 750H 710H 6D0H 690H 650H

: : : : : : : :

COM31

7DFH 79FH 75FH 71FH 6DFH 69FH 65FH

COM32 7E0H 7A0H 760H 720H 6E0H 6A0H 660H

: : : : : : : :

COM46 7EEH 7AEH 76EH 72EH 6EEH 6AEH 66EH
COM47 7EFH 7AFH 76FH 72FH 6EFH 6AFH 66FH

Page

6, 5, 4

SEG

[63:56]

SEG

[71:64]

SEG

[79:72]

SEG

[87:80]

SEG

[95:88]

SEG

[103:96]

SEG

[111:104]

COM0 600H 5C0H 580H 540H 500H 4C0H 480H
COM1 601H 5C1H 581H 541h 501H 4C1H 481H

: : : : : : : :

COM15 60FH 5CFH 58FH 54FH 50FH 4CFH 48FH
COM16 610H 5D0H 590H 550H 510H 4D0H 490H

: : : : : : : :

COM31 61FH 5DFH 59FH 55FH 51FH 4DFH 49FH
COM32 620H 5E0H 5A0H 560H 520H 4E0H 4A0H

: : : : : : : :

COM46 62EH 5EEH 5AEH 56EH 52EH 4EEH 4AEH
COM47 62FH 5EFH 5AFH 56FH 52FH 4EFH 4AFH

64 COM:

Page 7,6

SEG[7:0]

SEG[15:8]

SEG[23:16]

SEG[31:24]

SEG[39:32] SEG[47:40]

COM0 7C0H 780H 740H 700H 6C0H 680H
COM1 7C1H 781H 741H 701H 6C1H 681H

: : : : : : :

COM15

7CFH 78FH 74FH 70FH 6CFH 68FH

COM16

7D0H 790H 750H 710H 6D0H 690H

: : : : : : :

COM31

7DFH 79FH 75FH 71FH 6DFH 69FH

COM32 7E0H 7A0H 760H 720H 6E0H 6A0H

: : : : : : :

COM47 7EFH 7AFH 76FH 72FH 6EFH 6AFH
COM48 7F0H 7B0H 770H 730H 6F0H 6B0H

: : : : : : :

COM62 7FEH 7BEH 77EH 73EH 6FEH 6BEH
COM63 7FFH 7BFH 77FH 73FH 6FFH 6BFH

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Page 6, 5

SEG[55:48]

SEG[63:56]

SEG[71:64]

SEG[79:72]

SEG[87:80] SEG[95:88]

COM0 640H 600H 5C0H 580H 540H 500H
COM1 641H 601H 5C1H 581H 541H 501H

: : : : : : :

COM15 64FH 60FH 5CFH 58FH 54FH 50FH
COM16 650H 610H 5D0H 590H 550H 510H

: : : : : : :

COM31 65FH 61FH 5DFH 59FH 55FH 51FH
COM32 660H 620H 5E0H 5A0H 560H 520H

: : : : : : :

COM47 66FH 62FH 5EFH 5AFH 56FH 52FH
COM48 670H 630H 5F0H 5B0H 570H 530H

: : : : : : :

COM62 67EH 63EH 5FEH 5BEH 57EH 53EH
COM63 67FH 63FH 5FFH 5BFH 57FH 53FH

80 COM:

Page

7:3

SEG

[7:0]

SEG

[15:8]

SEG

[23:16]

SEG

[31:24]

SEG

[39:32]

SEG

[47:40]

SEG

[55:48]

SEG

[63:56]

SEG

[71:64]

SEG

[79:72]

COM0 780H 700H 680H 600H 580H 500H 480H 400H 380H 300H
COM1 781H 701H 681H 601H 581H 501H 481H 401H 381H 301H

: : : : : : : : : : :

COM15 78FH 70FH 68FH 60FH 58FH 50FH 48FH 40FH 38FH 30FH
COM16 790H 710H 690H 610H 590H 510H 490H 410H 390H 310H

: : : : : : : : : : :

COM31 79FH 71FH 69FH 61FH 59FH 51FH 49FH 41FH 39FH 31FH
COM32 7A0H 720H 6A0H 620H 5A0H

520H 4A0H

420H 3A0H

320H

: : : : : : : : : : :

COM47 7AFH 72FH 6AFH 62FH 5AFH

52FH 4AFH

42FH 3AFH

32FH

COM48 7B0H 730H 6B0H 630H 5B0H

530H 4B0H

430H 3B0H

330H

: : : : : : : : : : :

COM62 7BFH 73FH 6BFH 63FH 5BFH

53FH 4BFH

43FH 3BFH

33FH

COM63 7C0H 740H 6C0H 640H 5C0H

540H 4C0H

440H 3C0H

340H

: : : : : : : : : : :

COM78 7CEH 74EH 6CEH 64EH 5CEH

54EH 4CEH

44EH 3CEH

34EH

COM79 7CFH 74FH 6CFH 64FH 5CFH

54FH 4CFH

44FH 3CFH

34FH

7. LCD Power Supply

The built-in LCD power supply is equipped with input voltage regulator, voltage charge pump and bias
voltage generating circuit with active buffer instead of passive resistor voltage dividing network. The
input voltage is regulated to LVL2 using the internally generated reference voltage. LVL2 can be adjusted
by resistor between LCDGS and LVL2.

LVL2 adjustment guideline: First, the level of VDD must be 0.3 volt higher than LVL2 even at the end of
battery life for the regulator to function properly. For example, if the VDD is expected to drop to 2.2 volts
when battery is low, then the level of LVL2 can only be set at 1.9 volts max.

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Voltage charge pump: The LVL2 is then pumped to LVL5 based on the bias setting of MO_LBSR[3..0].
The formula for LVL5 is:

LVL5 = LVL2 / 2 x (1/Bias)

The potential difference between bias voltages LVL1 ~ LVL5 is determined by the bias settings, too.

LVL5

LVL4

LVL3

LVL2

LVL1

3 ~ 6.5

Voltage

Ratio

Difference

For example, if the bias setting is 1/7 bias and LVL2 is 2 volts, the LVL5 will be pumped to 7 volts when
the load is light.

Bias 5.0 5.5 6.0

6.5

7.0

7.5

8.0 8.5

9.0 9.5 10.0

Min. VDD LVL2

LVL5 = LCD Panel Operating Voltage

2.70

2.40 6.00 6.60 7.20 7.80 8.40

2.60

2.30 5.75 6.33 6.90 7.48 8.05

2.50

2.20 5.50 6.05 6.60 7.15 7.70 8.25

2.40

2.10 5.25 5.78 6.30 6.83 7.35 7.88 8.40

2.30

2.00 5.00 5.50 6.00 6.50 7.00 7.50 8.00 8.50

2.20

1.90 4.75 5.23 5.70 6.18 6.65 7.13 7.60 8.08 8.55

2.10

1.80 4.50 4.95 5.40 5.85 6.30 6.75 7.20 7.65 8.10 8.55

2.00

1.70 4.25 4.68 5.10 5.53 5.95 6.38 6.80 7.23 7.65 8.08 8.5

Please note that external connections of charge pump capacitors must be made according to the bias
setting, too. Please use the following figure as reference when designing application circuit and LVL5
must be lower than 8.5 volts to prevent chip from breaking down.

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LVL5

LVL4

LVL3

LCAPVTB

LCAP4B

LCAP4A

LCAP3B

LCAP3A

LCAP2B

LCAP2A

LCAP1B

LCAP1A

LCDGS

LVL2

LVL1

LCDVX

1uF

For bias: 5, 5.5, 6

For bias: 6.5, 7, 7.5, 8

For bias: 8.5, 9, 9.5, 10

Different duties require different bias settings. There is some theoretical correspondence between the
Duty and Bias Setting. However, it is better to use it as starting point and adjust it with real LCD panel
connected to it to determine the final setting. The theoretic relationship between the duty and bias setting
as following:

Duty Cycle Normal Bias Alternative Bias

32 duty

1/7

1/7.5

48 duty

1/8

1/7.5, 1/8.5

64 duty

1/9

1/8.5, 1/9.5

80 duty

1/10

1/9.5, 1/10.5

The bias setting is made by mask option MO_LBSR[3..0].

MO_LBSR[3:0] Bias Setting

0000 undefined
0001

1/5

0010 1/5.5
0011 1/6
0100 1/6.5
0101 1/7
0110 1/7.5
0111 1/8
1000 1/8.5
1001 1/9
1010 1/9.5
1011 1/10
1100 1/10.5
1101 1/11

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1110 1/11.5
1111 1/12

7.1. LCDC Control register

The gray scale of the LCD driver can be adjusted by GRAY field of LCD. The LCD panel can be blanked
by setting the BLANK field of LCDC register. LCD driver can be totally turned off by clearing LCDE bit
of LCDC.

LCDC

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Field

- - -

GRAY

BLANK

LCDE

Reset

- - - - - - 1 0

Field Value

Function

GRAY

000 LCD is darkest.

111 LCD is lightest.

BLANK 0 normal

display

LCD display blanked. The COM signals of LCD driver output inactive levels
(LVL4 and LVL1) while SEG signals output normal display patterns.

LCDE

LCD driver disabled, LCD driver has no output signal.

LCD driver Enabled

Please note that LCD driver must be turned off before the MCU goes into sleep mode. In other words,
user must clear the bit 0 (LCDE bit) of LCDC to turn off LCD driving circuit before setting bit6 of OP1
to enter sleep mode. Large current might happen if the procedure is not followed.

Please note that LCD driver uses slow clock as clock source. The LCD display would not display
normally if it worked in Fast clock only mode as the LCD refresh action would be too fast.

8. Oscillators

The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to

choose from. So that system designer can select oscillator types based on the cost target, timing accuracy

requirements etc. Crystal, Resonator or the RC oscillator can be used as fast clock source, components

should be placed as close to the pins as possible. The type of oscillator used is selected by mask option

MO_FXTAL.

MO_FXTAL Fast clock type

0 RC

Oscillator.

1 Crystal

Oscillator.

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FXI

FXO

22p

3579545Hz

Crystal Osc.

RC Osc.

The RC oscillator has a built-in capacitor. An external resistor is needed to connect from FXI to GND to

determine the oscillation frequency. The capacitance of internal RC oscillator is selected by mask option

MO_RCAP[2..0].

MO_RCAP[2..0] Internal RC Cap. OSC. (pF)

000 2
001 4
010 7
011 14
100 20
101 40
110 50
111 60

The following table shows the combinations of R and C, and the resulting frequency. Please note that

oscillation frequency in the table only represents oscillation frequencies of certain samples. The actual

oscillation frequency may vary up to �15% from lot to lot due to process parameter variations. User must

take this into consideration when using this chip in applications.

Ring Oscillator Frequency Table

R(K ohm )\

(pF)

7 4 2

30.20

0.8

1.5

2.0

3.0

4.0

5.0 MHz

19.92

1.2

2.2

2.8

4.4

5.6

7.0 MHz

9.98

2.3

4.0

5.1

7.5

9.4 11.4 MHz

Two types of oscillator, crystal and RC, can be used as slow clock by mask option MO_SXTAL. If used

for time keeping function or other applications that required the accurate timing, crystal oscillator is

recommended. If the timing accuracy is not important, then RC type oscillator can be used to reduce cost.

MO_SXTAL Slow clock type

0 R/C

oscillator

1 Crystal

oscillator

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SXI

SXO

Crystal Osc.

RC Osc.

With two clock sources available, the system can switch among operation modes of Fast, Slow, Idle, and
Sleep modes by the setting of OP1 and OP2 registers as shown in tables below to suit the needs of
application such as power saving, etc.

OP1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Field DRDY STOP SLOW

INTE T2E T1E

Mode R/W R/W R/W R/W R/W R/W R/W R/W

Reset

1 0 0 0 0 0 - -

OP2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Field IDLE PNWK

TCWK

TBE

TBS[3..0]

Mode

R/W R R R/W W W W W

Reset

0 - - 0 - - - -

If the dual clock mode is used, the LCD display, Timer1 and Timer Base will derive its clock source from

slow clock while the other blocks will operate with the fast clock.

9. General Purpose I/O

There are three dedicated general purpose I/O port, PRTC, PRTD and PRT10, while PRT14, PRT15 and

PRT17 are multiplexed with LCD segment driver pins. All the I/O Ports are bi-directional and of non-

tri-state output structure. The output has weak sourcing (50 �A) and stronger sinking (1 mA) capability

and each can be configured as push-pull or open-drain output structure individually by mask option.

When the I/O port is used as input, the weakly high sourcing can be used as weakly pull-up. Open drain

can be used if the pull-up is not required and let the external driver to drive the pin. Please note that a

floating pad could cause more power consumption since the noise could interfere with the circuit and

cause the input to toggle. A `1' needs to be written to port first before reading the input data from the I/O

pin. If the PMOS is used as pull-up, care should be taken to avoid the constant power drain by DC path

between pull-up and external circuit.

The input port has built-in Schmidt trigger to prevent it from chattering. Hysteresis level of Schmidt

trigger is 1/3*VDD.

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10. Key Scan Circuit

The built-in 4x20 hardware keyboard scan circuit helps to reduce the pin counts where application
requires large key matrix and high LCD pixel count as well as the firmware effort. As key-scan pins are
shared with LCD segment and PRTC4 ~ PRTC7 pins, it is advisable to put resistors between segment pins
and key matrix to avoid shorting the segment pins when two or more keys in the same row are pressed
simultaneously. Two key can be detected simultaneously and the first detected key code is stored in
KEY0 register and the second in KEY1 register respectively. The key code for each key location is listed
in the following table.

Key Loc SCNI0 SCNI1 SCNI2 SCNI3
SCNO0 0x80

0xA0 0xC0 0xE0

SCNO1 0x81

0xA1 0xC1 0xE1

SCNO2 0x82

0xA2 0xC2 0xE2

SCNO3 0x83

0xA3 0xC3 0xE3

SCNO4 0x84

0xA4 0xC4 0xE4

SCNO5 0x85

0xA5 0xC5 0xE5

SCNO6 0x86

0xA6 0xC6 0xE6

SCNO7 0x87

0xA7 0xC7 0xE7

SCNO8 0x88

0xA8 0xC8 0xE8

SCNO9 0x89

0xA9 0xC9 0xE9

SCNO10 0x8A 0xAA 0xCA 0xEA
SCNO11 0x8B 0xAB 0xCB 0xEB
SCNO12 0x8C 0xAC 0xCC 0xEC
SCNO13 0x8D 0xAD 0xCD 0xED
SCNO14 0x8E 0xAE 0xCE 0xEE
SCNO15 0x8F 0xAF 0xCF 0xEF
SCNO16 0x90

0xB0 0xD0 0xF0

SCNO17 0x91

0xB1 0xD1 0xF1

SCNO18 0x92

0xB2 0xD2 0xF2

SCNO19 0x93

0xB3 0xD3 0xF3

KEY0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0x22

Row Index

Column Index

KEY1 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0x23

Row Index

Column Index

The bit 7 of KEY0 and KEY1 is repeat indicator when the same key is scanned for the second time, the R
bit will be cleared to indicate the key is not released yet.

The key-scan function can be turned on/off by mask option MO_LCDKEY.

MO_LCDKEY SGKY[43..24]

Function

as SEG only

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as SEG as well as KEY_SCAN

The pulse width of key-scan signal can be selected by mask options MO_SNCK[1..0].

MO_SNCK[1..0]

Key Scan Pulse Width

00 0.5

sck

01 1

sck

10 1.5

sck

11 2

sck

The strength of key-scan signal can also be selected by mask options MO_SNCK[1..0].

MO_SCDRV[1..0]

Key Scan Signal Strength

00 weakest
01
10
11 strongest

SGKY24

SCNO0

SGKY25

SCNO1

SGKY26

SCNO2

SGKY27

SCNO3

SGKY41

SCNO17

SGKY42

SCNO18

SGKY43

SCNO19

PRTC4

SCNI0

PRTC5

SCNI1

PRTC6

SCNI2

PRTC7

SCNI3

47K

....

11. Timer1

The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If
Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt
will be generated when the counter underflows - counts down to FFFFH. And the counter will be
automatically reloaded with the value of T1H and T1L.

The clock source of Timer1 is derived from slow clock "SCK" at dual clock or slow clock only mode.
And it comes from the fast clock "FCK" at fast clock only mode.

Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of

T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero

when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately

and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be

set before enabling Timer1.

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T1H

T1L

"Timer1 Counter"

decreases 1

Count TO

0xFFFFh

Auto reload when

Timer1 underflow

Start Timer1

Interrupt Request.

Yes

The contents of T1H and

T1L almost loaded into

Timer1 immediately

when Timer1 is turned on

after reset.

T1_INT

The Timer1 related control registers are list as below:

Address Field Bit

position Mode

Description

IER

0x02 TC1_IER

R/W 0: TC1 interrupt is disabled. (default)

1: TC1 interrupt is enabled.

T1L

0x03

T1L[7:0]

7~0

W Low byte of TC1 pre-load value

T1H

0x04

T1H[7:0]

7~0

W High byte of TC1 pre-load value

OP1

0x09

TC1E

R/W 0: TC1 is disabled. (default)

1: TC1 is enabled.

12. Timer2

Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock

"Fsys"/1.5. The system clock "Fsys" varies depending on the operation modes of the MCU.

The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If
Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will
be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded

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with the value of T2H and T2L.

Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value

of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when

system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and

value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value

should be set before enabling Timer2.

T2H

T2L

"Timer2 Counter"

decreases 1

Count TO

0xFFFFh

Auto reload when

Timer2 underflow

Start Timer2

Interrupt Request.

Yes

The contents of T2H and

T2L almost loaded into

Timer2 immediately

when Timer2 is turned on

after reset.

T2_INT

The Timer2 related control registers are list as below:

Address Field Bit

position Mode

Description

IER

0x02 TC2_IER

R/W 0: TC2 interrupt is disabled. (default)

1: TC2 interrupt is enabled.

T2L

0x05

T2L[7:0]

7~0

W Low byte of TC2 pre-load value

T2H

0x06

T2H[7:0]

7~0

W High byte of TC2 pre-load value

OP1

0x09

TC2E

R/W 0: TC2 is disabled. (default)

1: TC2 is enabled.

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13. Time Base Interrupt

The TB timer is used to generate time-out interrupt at fixed period. The time-out frequency of TB is
determined by dividing slow clock with a factor selected in OP2[3..0]. TBE (Time Base Enable) bit
controls enable or disable of the circuit.

OP2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Field IDLE PNWK

TCWK

TBE

TBS[3..0]

Mode

R/W R R R/W W W W W

Reset

0 - - 0 - - - -

TBE Function

0 Disable

Time

Base

1 Enable

Time

Base

For example, if the slow clock is 32768 Hz, then the interrupt frequency is as shown in following table.

TBS[3..0] Interrupt Frequency

0000 16.384

KHz

0001 8.192

KHz

0010 4.096

KHz

0011 2.048

KHz

0100 1.024

KHz

0101 512

0110 256

0111 128

1000 64

1001 32

1010 16

1011 8

1100 4

1101 2

1110 1

1111

0.5 Hz

14. Watch Dog Timer

Watch Dog Timer (WDT) is designed to reset system automatically prevent system dead lock caused by

abnormal hardware activities or program execution. WDT needs to be enabled in Mask Option.

MO_WDTE Function

0 WDT

disable

1 WDT

enable

To use WDT function, "CLRWDT" instruction needs to be executed in every possible program path

when the program runs normally in order to clears the WDT counter before it overflows, so that the

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program can operate normally. When abnormal conditions happen to cause the MCU to divert from

normal path, the WDT counter will not be cleared and reset signal will be generated.

WDT is the enabling signal generated by calculating 32768-clock overflow. Reset Register content is

same as TC1 (Timer1 clock), which uses the same clock count source. WDT function can be generated in

Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1 clock has

stopped.)

15. Digital-to-Analog Converter

The Digital-to-Analog converter (DAC) converts the 7-bit unsigned speech data written to PWMC to
proportional current output.

PWMC register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DA & PWM Data

DA and PWM output value

Control

PWM O/P driver

PWME

There are two output paths for the DAC. Either VO or DAO can be selected as output port of DAC by
VOC register when it is enabled. The VO output is primarily intended for speech generation, although it
is not necessary so, while the DAO output path can be used in conjunction with built-in OP comparator to
function as an Analog-to-Digital Converter as required in applications such as speech recording, speech
recognition or sensor interfaces.

OPO

OPIP

OPIN

DAO

PWMC[DATA]

VOC[DAC]

VOC[OP]

DAC

The DAC is enabled by DAC bit of VOC register. Please note that the DAC bit of VOC register will be
automatically cleared when the system enter Idle or Sleep mode. So it needs to be set again when
returning to Normal mode.

VOC
VOC register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Initial

- - - - - 0 0 0

- - - - -

PWM

DAC

Bit Name Value Function

description

1 DAC 1

Enable

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0 DA

Disable

The output current of the DAC is programmable by mask option MO_DACISEL:

MO_DACISEL[1:0] DAC output current

00 0.375

01 0.75

10 1.5

11 3

16. Pulse-Width Modulation

The pulse-width modulator (PWM) converts 7-bit unsigned speech data written to PWMC data register to
proportional duty cycle of PWM output. PWM module shares the PWMC data register with
Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM circuit is
enabled, it generates signal with duty ratio in proportion to the DA value.

DA = 0x20

DA = 0x80

DA = 0xE0

1 subframe

The PWM bit of VOC register controls register to enable the circuit and output driver. When PWM bit of
VOC is `0', PWME bit and output drivers settings are both cleared. To use PWM for voice output, PWM
bit has to be set to `1' first, then set PWME bit and enable output driver by setting the driver number. If
PWM bit is disabled and enabled again, the setting for driver and PWME bit will be clear.

The Fast Clock is gated through PWME bit of PWMC command register to provide the clock source of
PWM circuit when it is enabled. As PWM needs higher frequency to operate, it cannot generate correct
PWM signal in Slow clock only mode.

When the program enters into Sleep mode or Idle mode, it will automatically turn off all voice outputs by
clearing VOC[2..1] to "00". To activate voice output again when returning to Normal Mode, the VOC
register needs to be set again.

The PWM output volume can be adjusted by command register PWMC[6..4]. The bit 6 and 5 control 2
time driver, while bit 4 controls 1 time driver, thus it has 5 levels of driver output. By turning on/off the
internal drivers, the sound level of PWM output can be turned up and down. Please note that this
adjustment apply only to PWM, but not DA output.

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PWM output driver selection

PWMC[6..4] Number of Driver

000 off

001 1

010 2

011 3

100 2

101 3

110 4

111 5

17. Low Voltage Detection

The low voltage detection is used to detect low battery or low power condition. There are 2 options on the
detection level selectable by DLVL[1..0] of PRT11. The low voltage detection circuit can be turned off by
setting both DLVL1 and DLVL0 bits, and the status of supply power can be read out at bit LVDO of
PRT11.

PRT11

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Field - - - - -

LVDO DLVL1

DLVL0

Mode - - - - - R W

Reset - - - - - - 1 1

DLVL[1..] Function

00 reserved
01

Detection level 2.2 volts

Detection level 2.4 volts

Voltage detector off

LVDO Function

0 Battery

level

low

1 Battery

level

high

18. Absolute Maximum Rating

Item Sym.

Rating

Condition

Supply Voltage

-0.5V ~ 4.0V

Input Voltage

-0.5V

+0.5V

Output Voltage

-0.5V

+0.5V

Operating Temperature

C ~ 70

Storage Temperature

-50

C ~ 100

19. Recommended Operating Conditions

Item Sym.

Rating

Condition

Supply Voltage

2.4V ~ 3.6V

0.9

~ V

Input Voltage

0.0V ~ 0.1V

8MHz V

=3.0V

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8MHz V

=3.0V

Operating Frequency

Fmax

6MHz V

=2.4V

Operating Temperature

C ~ 70

Storage Temperature

-50

C ~ 100

20. AC/DC Characteristics

Testing Condition : TEMP=25, VDD=3V�10%

Parameters Symbol

Min.

Typ.

Max.

Unit

Condition

Power consumption
Normal mode current

FAST

1.5

2M external R/C fast clock

Slow mode Current

SLOW

15 25

�A

32768 Hz slow clock with LCD
disabled

Idle mode Current

IDLE

�A

32768 Hz slow clock with LCD
disabled

Sleep mode Current

SLEEP

1 �A

Additional Current if LCD
ON

LCD

150

220

�A

1/7 bias, no load on SEG and COM pins

I/O specification
Input High Voltage

0.8

VDD Input

Pins

Input Low Voltage

0.2

VDD Input

Pins

Input Hysteresis Width

HYS

1/3

VDD

I/O, RSTP_N Threshold = 2/3xVDD
(Input from low to high), Threshold =
1/3xVDD (Input from high to low)

Output Source Current

�A

Output drive high

*1,

=2.0V

Output Sink Current

OL1

1.0

Output drive low, V

=0.4V

Input Low Current

IL1

20 �A

RSTP_N, V

= GND, Pull high

Internally

Input Low Current

IL2

100 �A

I/O, V

=GND, if pull high Internally by

user

PWM and DAC

10 14 mA

PWM

With 32 Loading

6 8 mA

With

64 Loading

PWM Output Current

PWM

4 5 mA

With

100 Loading

DAC Output Current

oVO

2.5 3 mA

VO, DAO@ VDD=3V,VO=0~2V, Data
= 7F

Notes:
1.

The "Output Source Current" specification is applicable only to the Push-Pull I/O type.

This specification indicates only one PWM driving capability, and there are totally five built-in drivers, user
can multiply the actual number of driver to get the actual current. (I

PWM

x N; where N = 0, 1, 2, 3, 4, 5)

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21. Application Circuit

VDD

CMSG42

CMSG47

LGS2

COM3

SEG78

SEG152

SEG134

PRT171

SEG129

PRT150

RD6

SEG119

SEG54

SEG117

SEG49

SEG113

SEG109

SEG82

SXI

SEG34

SEG35

LCAP4A

LVL3

COM1

COM23

SEG151

SEG138

SEG67

SEG131

RD1

SEG59

RD5

PRT156

PRT140

LVL2

SEG81

SEG107

SEG

145

SEG37

OPO

LVAG

CMSG53

CMSG56

CMSG60

CMSG63

COM19

SEG77

SEG139

SEG159

SEG58

SEG111

SEG80

SEG83

SEG

SGKY

4
2

CNO

1
8

SEG96

106

CMSG44

LVREG

COM8

SEG141

SEG140

PRT176

SEG60

RD4

DCN

LVL5

SEG106

SEG90

I
3

146

SEG39

SEG46

CMSG35

OPIP

CMSG48

CMSG70

CMSG78

COM24

COM25

COM27

SEG66

SEG56

PRT155

SEG118

LVP

SEG84

SEG88

SEG98

SEG41

FXI

RST

CMSG39

CMSG40

LVL4

COM5

CMSG67

CMSG75

SEG75

SEG158

PRT172

RD2

SEG123

SEG55

SEG110

SEG105

SEG101

SGKY

4
3

CNO

1
9

SEG93

SXO

103

CMSG43

CMSG62

CMSG64

CMSG65

CMSG72

COM17

SEG76

SEG73

SEG71

SEG127

SEG62

SEG51

SEG85

SEG89

I
0

SGKY

2
7

SGKY

2
5

SEG25

SEG36

CMSG49

CMSG59

COM2

COM16

CMSG76

SEG150

COM31

PRT177

SEG124

PRT153

SEG112

SEG104

SEG100

SEG

SEG97

102

CMSG32

LDL

LCAP2A

COM0

COM9

COM12

COM20

SEG69

RD3

SEG86

SEG91

SEG24

SEG26

SEG43

SEG44

SEG47

CMSG34

LCAP3A

LVL2

CMSG61

CMSG68

CMSG71

CMSG79

SEG157

SEG61

RD7

SEG53

LDL

SEG103

SEG99

SEG

105

101

SEG30

DAO

LGS1

LCAP2B

CMSG55

CMSG57

COM21

SEG133

PRT173

RD0

SEG126

PRT151

PRT152

SEG122

SEG57

PRT157

SEG52

SEG115

SEG50

SEG87

144

147

SEG27

FXO

CMSG41

LFR

COM14

COM18

SEG153

SEG137

PRT170

SEG64

PRT154

PRT142

LVL3

I
2

SGKY

4
1

CNO

1
7

107

100

SEG31

OPIN

CMSG37

CMSG38

CMSG73

CMSG77

COM28

COM30

SEG68

RES

PRT175

SEG120

SEG102

I
1

SEG28

SEG40

SEG45

CMSG45

LVP

CMSG52

COM13

COM15

SEG72

SEG155

SEG65

REN

LFR

SEG95

SEG32

SEG42

CMSG33

CMSG46

LCAP1B

CMSG50

LVL5

LVL1

COM7

COM10

CMSG74

SEG154

SEG135

SEG125

SEG121

SEG116

SEG114

SEG92

SGKY

2
6

SGKY

2
4

104

SEG29

SEG38

CMSG36

CMSG51

CMSG54

CMSG58

CMSG69

SEG79

COM26

SEG136

SEG70

PRT174

SEG128

SEG63

PRT141

SEG94

SEG33

LCAP1A

COM4

COM6

CMSG66

COM11

COM22

SEG74

COM29

SEG156

SEG132

SEG130

STBN

RWN

PRT143

SEG108

SEG

SEG48

3.0V

0.1uF

1uF

4.7uF

HE847721

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

SEG

KY43

KY42

KY41

KY40

KY39

KY38

KY37

KY36

KY35

KY34

KY33

KY32

KY31

KY30

KY29

KY28

KY27

KY26

KY25

KY24

147

146

145

144

PRT143

PRT142

PRT141

PRT140

PRT157

PRT156

PRT155

PRT154

PRT153

PRT152

PRT151

PRT150

PRT177

PRT176

PRT175

PRT174

PRT173

PRT172

PRT171

PRT170

COM31

COM30

COM29

COM28

COM27

COM26

COM25

C0M24

C0M23

C0M22

C0M21

C0M20

C0M19

C0M18

C0M17

C0M16

C0M15

C0M14

C0M13

C0M12

C0M11

C0M10

C0M9

C0M8

C0M7

C0M6

C0M5

C0M4

C0M3

COM2

COM1

COM0

LVL1

LVL2

LVL3

LVL4

LVL5

LCAP4A

LCAP4B

LCAP3A

LCAP3B

LCAP2A

LCAP2B

LCAP1A

LCAP1B

LCDGS

LCDVX

LCDVTB

LFR

LDL

GND

DAO

OPIN

OPIP

OPO

RSTP_N

FXO

FXI

TSTP

SXO

SXI

1
0
7

1
0
6

1
0
5

1
0
4

1
0
3

1
0
2

1
0
1

1
0
0

ND_

_
R

CMSG32

CMSG33

CMSG34

CMSG35

CMSG36

CMSG37

CMSG38

CMSG39

CMSG40

CMSG41

CMSG42

CMSG43

CMSG44

CMSG45

CMSG46

CMSG47

CMSG48

CMSG49

CMSG50

CMSG51

CMSG52

CMSG53

CMSG54

CMSG55

CMSG56

CMSG57

CMSG58

CMSG59

CMSG60

CMSG61

CMSG62

CMSG63

CMSG64

CMSG65

CMSG66

CMSG67

CMSG68

CMSG69

CMSG70

CMSG71

CMSG72

CMSG73

CMSG74

CMSG75

CMSG76

CMSG77

CMSG78

CMSG79

SEG79

SEG78

SEG77

SEG76

SEG75

SEG74

SEG73

SEG72

SEG71

SEG70

SEG69

SEG68

SEG67

SEG66

SEG65

SEG64

SEG63

SEG62

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

0.1uF

47K

0.1uF

260K

47K

33p

0.1uF

47K

0.1uF

10uF

0.1uF

22p

4.7uF

22p

560K

0.1uF

47K

33p

0.1uF

BUZZER

32768Hz

4MHz

47uF

4.7uF

KDS80

1 2 3 4 5 6 7 8

100

101

SEG

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

LVP

LVL5

LVL3

LVL2

LFR

LDL

REN

R_WN

D_CN

STBN

GND

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

RES_N

VDD

SEG79

SEG78

SEG77

SEG76

SEG75

SEG74

SEG73

SEG72

SEG71

SEG70

SEG

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG20

SEG19

and 80 SE

G Extender KDS8

....

This applic

ation assumes 8

0
COMX80 SEG con

figuration,

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22. Important Note

1. For accessing any address large than 64KB, users must update TPP first, TPH then TPL. Only by this

order, the pre-charge circuit of ROM will work correctly. 5us waiting is necessary before LDV
instruction is executed since Data ROM is a low speed ROM. Users can not emulate accessing delay
with ICE. So 5us delay should be added by firmware.

2. LCD driving circuit must be turned off before MCU goes into sleep mode.
3. Please bond the TSTP_P, RSTP_N and PRTD[7:0] with test points on PCB, which can be soldered

and probed. Connect TSTP_P pin with zero ohm resistor to GND (or copper wire which can be cut
easily on PCB) for good ESD protection. So that IC testing can be done on PCB, if necessary, by
removing the 0-ohm resistor and driving TSTP_P pin to high.

4. LVP must small than 8.5 Volt. Otherwise IC may breakdown.
5. Users must call the library "swap_page" in the file swappage.asm of AN029. The real IC register is

different from ICE4.x or ICE5.x. This subroutine make sure that users can run on both real IC and
ICE for page swapping. The program of swappage.asm as following:

.area swapping_variable(data)

_mapreg1:: .ds 1 ;store page register(R1Bh)

_mapreg2:: .ds 1 ;store page register(R1Ch)

.area

swapping_page(code,pag0)

;======================================================

;swap page function

;======================================================

swap_page::

lda #10h

sta _mapreg1

lda #00h

; P1E_O[2] <--0 to enable Port R1Fh

sta r_iceco

; R_ICECO is write only

lda _mapreg2

sta r_iced

lda _mapreg2

anda #0fh

ora

#20h

;Mapping

_mapreg2

low nibble to Logical segment2

;

sta r1Ch

sta r_ps1

lda _mapreg2

Электронный компонент: HE847721