Eastman Kodak Company Image Sensor Solutions - Rochester, NY 14650-2010
Phone (716) 722-4385 Fax (716) 477-4947
Web: www.kodak.com/go/ccd E-mail: ccd@kodak.com
2
Revision No. 1
KAF-1001E
Performance Specification
TABLE OF CONTENTS
1.1 Features ........................................................................................................................................... 3
1.2 Description ...................................................................................................................................... 3
1.3 Architecture..................................................................................................................................... 4
1.4 Image Acquisition ........................................................................................................................... 4
1.5 Charge Transport............................................................................................................................. 4
1.6 Output Structure .............................................................................................................................. 4
2.1 Package Configuration .................................................................................................................... 5
2.2 Pin Description................................................................................................................................ 6
3.1 Absolute Maximum Ratings ........................................................................................................... 8
3.2 DC Operating Conditions................................................................................................................ 8
3.3 AC Clock Level Conditions ............................................................................................................ 9
3.4 AC Timing..................................................................................................................................... 10
4.1 Image Specifications ..................................................................................................................... 12
4.2 Defect Classification ..................................................................................................................... 14
4.3 Typical Performance Data............................................................................................................. 15
5.1 Quality Assurance and Reliability................................................................................................. 17
5.2 Ordering Information .................................................................................................................... 17
6.1 Revision Changes.......................................................................................................................... 18
FIGURES
Figure 1 Functional Block Diagram ...................................................................................................... 3
Figure 2 Package Configuration............................................................................................................ 5
Figure 3 Pinout Diagram ....................................................................................................................... 7
Figure 4 Timing Diagram.................................................................................................................... 12
Figure 5 Typical Spectral Response .................................................................................................... 15
Figure 6 Dark Current as a Function of Temperature ......................................................................... 16
Eastman Kodak Company Image Sensor Solutions - Rochester, NY 14650-2010
Phone (716) 722-4385 Fax (716) 477-4947
Web: www.kodak.com/go/ccd E-mail: ccd@kodak.com
3
Revision No. 1
KAF-1001E
Performance Specification
1.1 Features
Front Illuminated Full-Frame Architecture
with Blue Plus Transparent Gate True Two
Phase Technology for high sensitivity
1024(H) x 1024(V) Photosensitive Pixels
24m(H) x 24m(V) Pixel Size
24.5 mm x 24.5 mm Photo active Area
1:1 Aspect Ratio
100% Fill Factor
Single Readout Register
2 Clock Selectable Outputs
High Gain Output (11 V/e-) for low noise
Low Gain Output (2.0 V/e-) for high
dynamic range
Low Dark Current (<30 pA/cm2 @ T=25oC)
1.2 Description
The KAF-1001E is a high-performance, silicon
charge-coupled device (CCD) designed for a wide
range of image sensing applications in the 0.4mm to
1.1mm wavelength band.
Common applications include medical, scientific,
military, machine and industrial vision.
The sensor is built with a true two-phase CCD
technology employing a transparent gate. This
technology simplifies the support circuits that drive
the sensor and reduces the dark current without
compromising charge capacity. The transparent gate
results in spectral response increased ten times at
400nm, compared to a front side illuminated standard
polysilicon gate technology. The sensitivity is
increased 50% over the rest of the visible
wavelengths.
The clock selectable on-chip output amplifiers have
been specially designed to meet two different needs.
The first is a high sensitivity 2-stage output with
11V/e
-
charge to voltage conversion ratio. The
second is a single-stage output with 2V/e- charge to
voltage conversion ratio.
KAF-1001E
Usable Active Image Area
1024(H) x 1024(V)
24
m x 24
m pixels
4 Dark Lines
V1
V2
Guard
4 Dark Lines
1024 Active Pixels/Line
8 Dark
2 Inactive
4 Dark
4 Inactive
H22
H21
R
Vog
Vrd
Vout 1
Vdd 1
Vss
Vout 2
Vdd 2
Sub
FD 1
FD 2
H1
H2
Figure 1 - Functional Block Diagram
(Shaded areas represent 4 non-imaging pixels at the beginning and 8 non-imaging pixels at the end of each line.
There are also 4 non-imaging lines at the top and bottom of each frame.)
Eastman Kodak Company Image Sensor Solutions - Rochester, NY 14650-2010
Phone (716) 722-4385 Fax (716) 477-4947
Web: www.kodak.com/go/ccd E-mail: ccd@kodak.com
4
Revision No. 1
KAF-1001E
Performance Specification
1.3 Architecture
Refer to the block diagram in Figure 1. The KAF-
1001E consists of one vertical (parallel) CCD shift
register, one horizontal (serial) CCD shift register and
a selectable high or low gain output amplifier. Both
registers incorporate true two-phase buried channel
technology. The vertical register consists of 24
m x
24
m photo-capacitor sensing elements (pixels)
which also serves as the transport mechanism. The
pixels are arranged in a 1024(H) x 1024(V) array; an
additional 12 columns (4 at the left and 8 at the right)
and 8 rows (4 each at top and bottom) of non-imaging
pixels are added as dark reference. Because there is
no storage array, this device must be synchronized
with strobe illumination or shuttered during readout.
1.4 Image Acquisition
An image is acquired when incident light, in the form
of photons, falls on the array of pixels in the vertical
CCD register and creates electron-hole pairs (or
simply electrons) within the silicon substrate. This
charge is collected locally by the formation of
potential wells created at each pixel site by induced
voltages on the vertical register clock lines (
V1,
V2). These same clock lines are used to implement
the transport mechanism as well. The amount of
charge collected at each pixel is linearly dependent on
light level and exposure time and non-linearly
dependent on wavelength until the potential well
capacity is exceeded. At this point charge will 'bloom'
into vertically adjacent pixels.
1.5 Charge Transport
Integrated charge is transported to the output in a two
step process. Rows of charge are first shifted line by
line into the horizontal CCD. 'Lines' of charge are
then shifted to the output pixel by pixel. Referring to
the timing diagram, integration of charge is
performed with
V1 and
V2 held low. Transfer to
horizontal CCD begins when
V1 is brought high
causing charge from the
V1 and
V2 gates to
combine under the
V1 gate.
V1 and
V2 now reverse their polarity causing the
charge packets to 'spill' forward under the
V2 gate of
the next pixel. The rising edge of
V2 also transfers
the first line of charge into the horizontal CCD. A
second phase transition places the charge packets
under the
V1 electrode of the next pixel. The
sequence completes when
V1 is brought low.
Clocking of the vertical register in this way is known
as accumulation mode clocking. Next, the horizontal
CCD reads out the first line of charge using
traditional complementary clocking (using
H1 and
H2 pins) as shown. The falling edge of
H2 forces a
charge packet over the output gate (OG) onto one of
the output nodes (floating diffusion) which controls
the output amplifier. The cycle repeats until all lines
are read.
1.6 Output Structure
The final gate of the horizontal register is split into
two sections,
H21 and
H22. The split gate structure
allows the user to select either of the two output
amplifiers. To use the high dynamic range single-
stage output (Vout1), tie
H22 to a negative voltage
to block charge transfer, and tie
H21 to
H2 to
transfer charge. To use the high sensitivity two-stage
output (Vout2), tie
H21 to a negative voltage and
H22 to
H2. The charge packets are then dumped
onto the appropriate floating diffusion output node
whose potential varies linearly with the quantity of
charge in each packet. The amount of potential
change is determined by the simple expression
Vfd=
Q/Cfd. The translation from electrons to
voltages is called the output sensitivity or charge-to-
voltage conversion. After the output has been sensed
off-chip, the reset clock (
R) removes the charge
from the floating
diffusion via the reset drain (VRD).
This, in turn, returns the floating diffusion potential to
the reference level determined by the reset drain
voltage.
PDF 
ZIP
