KAI-1003M
Performance Specification
Eastman Kodak Company Image Sensor Solutions - Rochester, NY 14650-2010
Phone (585) 722-4385 Fax (585) 477-4947
Web: www.kodak.com/go/imagers E-mail: imagers@kodak.com
2 Revision
4.0
CONTENTS
1.1 Features.................................................................................................................................................................................3
1.2 Description............................................................................................................................................................................3
1.3 Image Acquisition.................................................................................................................................................................4
1.4 Charge Transport ..................................................................................................................................................................4
1.5 Output Structure ...................................................................................................................................................................4
1.6 Non-Imaging Pixels..............................................................................................................................................................4
2.1 Package Drawing..................................................................................................................................................................7
2.3 Cover Glass Specification.....................................................................................................................................................9
3.1 Absolute Maximum Ratings ...............................................................................................................................................10
3.2 DC Operating Conditions ...................................................................................................................................................11
3.3 AC Clock Level Conditions................................................................................................................................................11
3.4 Electronic Shutter Operation ..............................................................................................................................................11
3.5 Calculated Clock Capacitance ............................................................................................................................................12
3.6 AC Timing Requirements...................................................................................................................................................12
3.7 CCD Clock Waveform Conditions.....................................................................................................................................13
Non-binning...........................................................................................................................................................................13
2 x 2 Binning .........................................................................................................................................................................13
4.1 Performance Specifications ................................................................................................................................................23
4.3 Defect Specifications ..........................................................................................................................................................25
Defect Test Conditions ..........................................................................................................................................................25
Defect Definitions..................................................................................................................................................................25
Defect Proximity....................................................................................................................................................................25
5.1 Quality Assurance and Reliability ......................................................................................................................................26
5.2 Ordering Information..........................................................................................................................................................26
Appendix 1 Part Number Availability ......................................................................................................................................27
Appendix 2 Revision History ...................................................................................................................................................27
FIGURES
Figure 1 - KAI-1003M Sensor Architecture................................................................................................................................3
Figure 2 - Horizontal CCD Registers ..........................................................................................................................................5
Figure 3 - Package Drawing ........................................................................................................................................................7
Figure 4 - Package Pin Designations - Top View........................................................................................................................8
Figure 5 - CCD Clock Waveform..............................................................................................................................................13
Figure 6 - Frame Timing - 1 x 1 ................................................................................................................................................14
Figure 7 - Line Timing - 1 x 1 - Dual Outputs, In-phase...........................................................................................................15
Figure 8 - Line Timing - 1 x 1 - Dual Outputs, Out-of-phase ...................................................................................................16
Figure 9 - Line Timing - 1 x 1 - Single Output .........................................................................................................................17
Figure 10 - Pixel Timing - 1 x 1 ................................................................................................................................................18
Figure 11 - Frame Timing - 2 x 2 ..............................................................................................................................................19
Figure 12 - Line Timing - 2 x 2 .................................................................................................................................................20
Figure 13 - Pixel Timing - 2 x 2 ................................................................................................................................................21
Figure 14 - Electronic Shutter Timing.......................................................................................................................................22
Figure 15 - Quantum Efficiency Spectrum................................................................................................................................24
Figure 16 - Angular Dependence of Quantum Efficiency.........................................................................................................24
TABLES
Table 1 - KAI-1003M Calculated Clock Parameters..................................................................................................................6
KAI-1003M
Performance Specification
Eastman Kodak Company Image Sensor Solutions - Rochester, NY 14650-2010
Phone (585) 722-4385 Fax (585) 477-4947
Web: www.kodak.com/go/imagers E-mail: imagers@kodak.com
3 Revision
4.0
1.1 Features
1 Megapixel Progressive Scan Interline CCD
1024 (H) x 1024 (V) Imaging Pixels
12.8
m Square Pixels
13.1 mm Square Imaging Area
Microlenses for Increased Sensitivity
Large capacity (170ke)
Split Horizontal Register for 1 or 2 Outputs
Binning to 1 x 2 or 2 x 2
1.2 Description
The KAI-1003M is a high performance interline
charge-coupled device (CCD) designed for a wide
range of medical imaging and machine vision
applications. The device is built using an advanced
two-phase, double-polysilicon, NMOS CCD
technology. The p+npn- photodiodes eliminate image
lag while providing antiblooming protection and
electronic shutter capability. The 12.8
m square pixels
with microlenses provide high sensitivity and large
dynamic range. The two output, split horizontal register
and several binning modes enable a 15 to 60 frame per
second (fps) video rate with this megapixel progressive
scan imager.
2 light shielded rows
2 buffer rows
1
4
li
g
h
t
sh
ield
ed
co
lu
mn
s
2 buffer col
u
mns
1024 x 1024
imaging pixels
2 buffer rows
2 buffer col
u
mns
1024
2
14
14
2
2
2 empt
y p
i
xel
s
Single Output
1
4
li
g
h
t
sh
ield
ed
co
lu
mn
s
2 light shielded rows
2 empt
y p
i
xel
s
512
2
14
14
2
2
Video A
Dual Output
Video B
512
or
2
Figure 1 - KAI-1003M Sensor Architecture
KAI-1003M
Performance Specification
Eastman Kodak Company Image Sensor Solutions - Rochester, NY 14650-2010
Phone (585) 722-4385 Fax (585) 477-4947
Web: www.kodak.com/go/imagers E-mail: imagers@kodak.com
4 Revision
4.0
1.3 Image Acquisition
An electronic representation of an image is formed
when incident photons falling on the sensor plane
create electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally
by the formation of potential wells at each photodiode.
Below photodiode saturation, the number of
photoelectrons collected at each pixel is linearly
dependent on light level and integration time and
nonlinearly dependent on wavelength. When the
photodiode's charge capacity is reached, excess
electrons are discharged into the substrate to prevent
blooming. The integration time can be decreased below
the frame time by using an electronic shutter, which is a
voltage pulse applied to the substrate to empty the
photodiodes.
1.4 Charge Transport
The integrated charge from each photodiode is
transported to the output by a three step process. The
charge is first transferred from the photodiodes to the
vertical shift registers by applying a large positive
voltage to one of the vertical CCD phases. This transfer
occurs simultaneously for all photodiodes. The charge
is then transported from the vertical CCD registers to
the horizontal CCD line by line in parallel. Finally, the
horizontal CCD register transports each line of charge
pixel by pixel serially to one or both of the output
structures.
The single horizontal CCD register is split into two
halves to allow a variety of line readout modes, as
shown in Figures 1 and 2. The A output half of the
register is a true two-phase design, which results in
unidirectional transport using phases H1A and H2A.
The B output half of the register is a pseudo two-phase
design, which allows bi-directional transport using
phases H1B, H2B, H1C and H2C. Dual output is
achieved with all of the first phases identical and all the
second phases identical. If the clocks of H1A and H2A
phases are shifted by one half cycle, the output remains
dual with the outputs alternating, so that only one
analog-to-digital converter is necessary. Finally, single
output of the entire image from the A output is obtained
by complementing the C phases, which reverses
transport in the B half of the horizontal CCD.
Binning can be used in a 1x2 and a 2x2 mode. Two
successive vertical transfers vertically bin the charge
directly onto the horizontal CCD, as shown in Figures
11 and 12. Horizontal binning is accomplished by two
successive horizontal transfers onto the H22 gate,
which then transfers the charge to the output structure,
as shown in Figure 13.
Combinations of output modes, binning and horizontal
clock frequency allow the range of frame rates listed in
Table 1.
1.5 Output Structure
Charge presented to the floating diffusion (FD) is
converted into a voltage and current amplified in order
to drive off-chip loads. The resulting voltage change
seen at the output is linearly related to the amount of
charge placed on the FD. Once the signal has been
sampled by the system electronics, the reset gate (
R) is
clocked to remove the signal and the FD is reset to the
potential applied by the reset drain (RD). More signal
at the floating diffusion reduces the voltage seen at the
output pin. In order to activate the output structure, an
off-chip load must be added to the output pin of the
device.
1.6 Non-Imaging Pixels
In addition to the 1024 (H) by 1024 (V) imaging pixels,
there are active buffer, light shielded and empty pixels,
as shown in Figure 1. A two pixel border of active
buffer pixels surrounds the imaging area. These buffer
pixels respond to illumination but are not tested for
defects and non-uniformities. Two light shielded rows
lead and follow each frame, and 14 light shielded
columns lead and follow each line. The light shielded
columns are tested for column defects and can be used
for dark reference. Only the center 10 columns by 1028
rows of light shielded region on each side can be used
for dark reference due to light leakage into the border
of two pixels at the edges. Finally, two empty pixels
occur at the beginning of each line, which are empty
shift register cycles not associated with any vertical
CCD columns. Empty pixels may also occur at the end
of the line, depending on the timing.
PDF 
ZIP
