Eastman Kodak Company

Technical Data

Kodak Digital Science KLI-2113 Image Sensor

Eastman Kodak Company - Image Sensor Solutions - Rochester, NY 14650-2010

Phone (716) 722-4385 Fax (716) 477-4947

Web:

www.kodak.com/go/imagers

E-mail: imagers@kodak.com

Revision No. 4

TABLE OF CONTENTS

1.1 Features ................................................................................................................................. 3
1.2 Description ............................................................................................................................ 3
1.3 Imaging.................................................................................................................................. 4
1.4 Exposure Control .................................................................................................................. 4
1.5 Charge Transport and Sensing .............................................................................................. 5
1.6 Pixel Summing...................................................................................................................... 5
1.7 Package Configuration .......................................................................................................... 6
2.1 Pin Description...................................................................................................................... 7
2.2 Maximum Ratings................................................................................................................. 8
2.3 DC Conditions....................................................................................................................... 9
2.4 AC Clock Level Conditions ................................................................................................ 10
2.5 AC Timing........................................................................................................................... 10
3.1 Image Specifications ........................................................................................................... 13
3.2 Defect Classification ........................................................................................................... 14
4.1 Quality Assurance and Reliability....................................................................................... 15
4.2 Ordering Information .......................................................................................................... 15
Revision Changes

FIGURES

Figure 1 Single Channel Schematic ............................................................................................ 3
Figure 2 Packaging Diagram ....................................................................................................... 6
Figure 3 ESD Protection Circuit ................................................................................................. 8
Figure 4 Typical Output Bias/Buffer Circuit............................................................................... 9
Figure 5 Output Waveforms...................................................................................................... 16
Figure 6 Typical Responsivity................................................................................................... 16

Eastman Kodak Company

Technical Data

Kodak Digital Science KLI-2113 Image Sensor

Eastman Kodak Company - Image Sensor Solutions - Rochester, NY 14650-2010

Phone (716) 722-4385 Fax (716) 477-4947

Web:

www.kodak.com/go/imagers

E-mail: imagers@kodak.com

Page 3 of 17

Revision No. 4

1.1 Features

Improved Tri-linear Color Array

High Resolution: 2098 pixels

Wide Dynamic Range

High

Sensitivity

High Operating Speed

High Charge Transfer Efficiency

No Image Lag

Electronic Exposure Control

Pixel Summing Capability

Up to 2.0V peak-peak Output

5.0V Clock Inputs

Two-Phase Register Clocking

On-chip Dark Reference

1.2 Description

The KLI-2113 is a high resolution, linear array
designed for color scanning applications. Each device
contains 3 rows of 2098 active photoelements,
consisting of high performance 'pinned diodes' for
improved sensitivity, lower noise and the elimination of
lag. Each row is selectively covered with an improved
red, green or blue integral filter stripe for spectral
separation. The pixel height and pitch is 14

m and the

center-to-center spacing between color channels is 112

m, giving an effective eight line delay between

adjacent channels during imaging. Readout of the pixel
data for each channel is accomplished through the use
of a single CCD shift register allowing for a single
output per channel with no multiplexing artifacts.
Twelve light shielded photoelements are supplied at the
beginning of each channel to act as a dark reference.
The devices are manufactured using NMOS, buried
channel processing and utilize dual layer polysilicon
and dual layer metal technologies. The die size is 31.15
mm X 1.73 mm and the chip is housed in a 28-pin,
0.600" wide, dual in-line package. Cover glass is multi-
layer AR coated on both sides.

SUB

VDD

VIDn

BlankCCD

Cells

BlankCCD

Cells

2098 Active Pixels

12 Test

12 Dark

TG2

TG1

LOGn

Photodiode Array

SUB

Figure 1 - Single Channel Schematic

Eastman Kodak Company

Technical Data

Kodak Digital Science KLI-2113 Image Sensor

Eastman Kodak Company - Image Sensor Solutions - Rochester, NY 14650-2010

Phone (716) 722-4385 Fax (716) 477-4947

Web:

www.kodak.com/go/imagers

E-mail: imagers@kodak.com

Page 4 of 17

Revision No. 4

1.3 Imaging

During the integration period, an image is obtained by
gathering electrons generated by photons incident
upon the photodiodes. The charge collected in the
photodiode array is a linear function of the local
exposure. The charge is stored in the photodiode
itself and is isolated from the CCD shift registers
during the integration period by the transfer gates
TG1 and TG2, which are held at barrier potentials. At
the end of the integration period, the CCD register
clocking is stopped with the

1 and

2 gates being

held in a 'high' and 'low' state respectively. Next, the
TG gates are turned 'on' causing the charge to drain
from the photo-diode into the TG1 storage region. As
TG1 is turned back 'off', charge is transferred through
TG2 and into the

storage region. The TG2 gate is

then turned 'off', isolating the shift registers from the
accumulation region once again. Complementary
clocking of the

1 and

2 phases now resumes for

readout of the current line of data while the next line
of data is integrated.

1.4 Exposure Control

Exposure control is implemented by selectively
clocking the LOG gates during portions of the
scanning line time. By applying a large enough
positive bias to the LOG gate, the channel potential is
increased to a level beyond the 'pinning level' of the
photodiode. (The 'pinning' level is the maximum
channel potential that the photodiode can achieve

and is fixed by the doping levels of the structure.)
With TG1 in an 'off' state and LOG strongly biased,
all of the photocurrent will be drawn off to the LS
drain. Referring to the timing diagrams, one notes that

the exposure can be controlled by pulsing the LOG
gate to a 'high' level while TG1 is turning 'off' and
then returning the LOG gate to a 'low' bias level
sometime during the line scan. The effective exposure
(t

exp

) is net time between the falling edge of the LOG

gate and the falling edge of the TG1 gate (end of the
line). Separate LOG connections for each channel are
provided enabling on-chip light source and image
spectral color balancing. As a cautionary note, the
switching transients of the LOG gates during line
readout may inject an artifact at the sensor output.
Rising edge artifacts can be avoided by switching
LOG during the photodiode-to-CCD transfer period,
preferably, during the TG1 falling edge. Depending
on clocking speeds, the falling edge of the LOG
should be synchronous with the

2 shift register

readout clocks. For very fast applications, the falling
edge of the LOG gate may be limited by on-chip RC
delays across the array. In this case artifacts may
extend across one or more pixels. Correlated double
sampling (CDS) processing of the output waveform
can remove the first order magnitude of such artifacts.
In high dynamic range applications, it may be
advisable to limit the LOG fall times to minimize the
current transients in the device substrate and limit the
magnitude of the artifact to an acceptable level.

Eastman Kodak Company

Technical Data

Kodak Digital Science KLI-2113 Image Sensor

Eastman Kodak Company - Image Sensor Solutions - Rochester, NY 14650-2010

Phone (716) 722-4385 Fax (716) 477-4947

Web:

www.kodak.com/go/imagers

E-mail: imagers@kodak.com

Page 5 of 17

Revision No. 4

1.5 Charge Transport and Sensing

Readout of the signal charge is accomplished by two-
phase, complementary clocking of the

1 and

gates. The register architecture has been designed for
high speed clocking with minimal transport and
output signal degradation, while still maintaining low
(4.75V

p-p

min) clock swings for reduced power

dissipation, lower clock noise and simpler driver
design. The data in all registers is clocked
simultaneously toward the output structures. The
signal is then transferred to the output structures in a
parallel format at the falling edge of the

2 clock.

Resettable floating diffusions are used for the charge
to voltage conversion while source followers provide
buffering to external connections. The potential
change on the floating diffusion is dependent on the
amount of signal charge and is given by

Q/C

. Prior to each pixel output, the floating

diffusion is returned to the RD level by the reset
clock,

1.6 Pixel Summing

The effective resolution of this sensor can be varied
by enabling the pixel summing feature. A separate pin
is provided for the last shift register gate labeled

2s.

This gate, when clocked appropriately, stores the
summation of signal from adjacent pixels. This
combined charge packet is then transferred onto the
sense node. As an example, the sensor can be
operated in 2-pixel summing mode (1049 pixels), by
supplying a

2s clock which is a 75% duty cycle

signal at 1/2 the frequency of the

2 signal, and

modifying the

R clock as depicted in the timing

diagram section. Applications that require full
resolution mode (2098 pixels), must tie the

2s pin to

the

2 pin. Refer to the timing diagram section for

additional details.

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