ispLSI

and pLSI

1032E

High-Density Programmable Logic

Functional Block Diagram

Features

· HIGH DENSITY PROGRAMMABLE LOGIC

-- 6000 PLD Gates
-- 64 I/O Pins, Eight Dedicated Inputs
-- 192 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

-- Small Logic Block Size for Random Logic

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

max = 125 MHz Maximum Operating Frequency

pd = 7.5 ns Propagation Delay

-- TTL Compatible Inputs and Outputs
-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- 100% Tested at Time of Manufacture
-- Unused Product Term Shutdown Saves Power

· ispLSI OFFERS THE FOLLOWING ADDED FEATURES

-- In-System Programmable (ISPTM) 5-Volt Only
-- Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

-- Reprogram Soldered Devices for Faster Prototyping

· OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS

-- Complete Programmable Device Can Combine Glue

Logic and Structured Designs

-- Enhanced Pin Locking Capability
-- Four Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control to

Minimize Switching Noise

-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global

Interconnectivity

· ispEXPERTTM LOGIC COMPILER AND COMPLETE

ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS
THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZERTM

-- PC and UNIX Platforms

Output Routing Pool

D7 D6 D5 D4 D3 D2 D1 D0

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

CLK

Global Routing Pool (GRP)

0139A(A1)-isp

Logic
Array

D Q

GLB

Description

The ispLSI and pLSI 1032E are High Density Program-
mable Logic Devices containing 192 Registers, 64
Universal I/O pins, eight Dedicated Input pins, four Dedi-
cated Clock Input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 1032E features 5-Volt
in-system programmability and in-system diagnostic ca-
pabilities. The ispLSI 1032E device offers non-volatile
reprogrammability of the logic, as well as the intercon-
nects to provide truly reconfigurable systems. It is
architecturally and parametrically compatible to the pLSI
1032E device, but multiplexes four input pins to control
in-system programming. A functional superset of the
ispLSI and pLSI 1032 architecture, the ispLSI and pLSI
1032E devices add two new global output enable pins.

The basic unit of logic on the ispLSI and pLSI 1032E
devices is the Generic Logic Block (GLB). The GLBs are
labeled A0, A1...D7 (see Figure 1). There are a total of 32
GLBs in the ispLSI and pLSI 1032E devices. Each GLB
has 18 inputs, a programmable AND/OR/Exclusive OR
array, and four outputs which can be configured to be
either combinatorial or registered. Inputs to the GLB
come from the GRP and dedicated inputs. All of the GLB
outputs are brought back into the GRP so that they can
be connected to the inputs of any GLB on the device.

1032E_06

Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

October 1998

Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

Specifications

ispLSI and pLSI 1032E

Functional Block Diagram

Figure 1. ispLSI and pLSI 1032E Functional Block Diagram

The devices also have 64 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.

Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. Each ispLSI
and pLSI 1032E device contains four Megablocks.

The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI and pLSI 1032E devices are se-
lected using the Clock Distribution Network. Four
dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into
the distribution network, and five clock outputs (CLK 0,
CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to
route clocks to the GLBs and I/O cells. The Clock Distri-
bution Network can also be driven from a special clock
GLB (C0 on the ispLSI and pLSI 1032E devices). The
logic of this GLB allows the user to create an internal
clock from a combination of internal signals within the
device.

I/O 63

I/O 62

I/O 61

I/O 60

RESET

Global

Routing

Pool

(GRP)

CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1

Clock

Distribution

Network

Generic

Logic Blocks

(GLBs)

Megablock

Output Routing Pool (ORP)

Input Bus

*ispEN/NC

lnput Bus

*ISP Control Functions for ispLSI 1032E Only

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

IN 7

IN 6

I/O 16

I/O 17

I/O 18

I/O 19

*SDO/IN 2

*SCLK/IN 3

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 35

I/O 34

I/O 33

I/O 32

I/O 0

I/O 1

I/O 2

I/O 3

I/O 12

I/O 13

I/O 14

I/O 15

*SDI/IN 0

*MODE/IN 1

I/O 8

I/O 9

I/O 10

I/O 11

I/O 4

I/O 5

I/O 6

I/O 7

I/O 47

I/O 46

I/O 45

I/O 44

GOE 1/IN 5

GOE 0/IN 4

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

Specifications

ispLSI and pLSI 1032E

Absolute Maximum Ratings

Supply Voltage V

.................................. -0.5 to +7.0V

Input Voltage Applied ........................ -2.5 to V

+1.0V

Off-State Output Voltage Applied ..... -2.5 to V

+1.0V

Storage Temperature ................................ -65 to 150

Case Temp. with Power Applied .............. -55 to 125

Max. Junction Temp. (T

) with Power Applied ... 150

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

= 0

C to + 70

= -40

C to + 85

SYMBOL

Table 2-0005/1032E

PARAMETER

Supply Voltage

Input High Voltage

Input Low Voltage

MIN.

MAX.

UNITS

4.75

4.5

2.0

5.25

5.5

0.8

Commercial

Industrial

Capacitance (T

=25

C, f=1.0 MHz)

Data Retention Specifications

Table 2-0008/1032E

PARAMETER

pLSI Erase/Reprogram Cycles

100

Data Retention

MINIMUM

MAXIMUM

UNITS

ispLSI Erase/Reprogram Cycles

10000

Cycles

Years

Cycles

SYMBOL

Table 2-0006/1032E

PARAMETER

Y0 Clock Capacitance

UNITS

TYPICAL

TEST CONDITIONS

Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)

V = 5.0V, V = 2.0V

Specifications

ispLSI and pLSI 1032E

Output Load Conditions (see Figure 2)

Switching Test Conditions

TEST CONDITION

470

390

35pF

390

35pF

470

390

35pF

Active High

Active Low

470

390

5pF

390

5pF

Active Low to Z
at V +0.5V

Active High to Z
at V -0.5V

Table 2-0004/1032E

Figure 2. Test Load

+ 5V

Device

Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

0213a

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at V = 5V and T = 25

4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .

Table 2-0007/1032E

IL-isp

PARAMETER

IL-PU

2, 4

Output Low Voltage

Output High Voltage

Input or I/O High Leakage Current

Input or I/O Low Leakage Current

ispEN Input Low Leakage Current

I/O Active Pull-Up Current

Output Short Circuit Current

Operating Power Supply Current

I = 8 mA

I = -4 mA

3.5V

V (Max.)

V = 5V, V = 0.5V

V = 0.5V, V = 3.0V

f = 1 MHz

IN IL

IN CC

IN IL

CC OUT

CLOCK

CONDITION

MIN.

TYP.

MAX.

UNITS

2.4

190

0.4

-10

-150

-200

OUT

Commercial

Industrial

Input Pulse Levels

Table 2-0003/1032E

Input Rise and Fall Time
10% to 90%

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to 3.0V

1.5V

See Figure 2

3-state levels are measured 0.5V from
steady-state active level.

-125

Others

2 ns

3 ns

Specifications

ispLSI and pLSI 1032E

pd1

UNITS

TEST

COND.

1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model

in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.

Table 2-0030A/1032E

1
tsu2 + tco1

( )

-100

MIN. MAX.

DESCRIPTION

PARAMETER

Data Propagation Delay, 4PT Bypass, ORP Bypass

10.0

pd2

Data Propagation Delay, Worst Case Path

max (Int.)

Clock Frequency with Internal Feedback

100

MHz

max (Ext.)

Clock Frequency with External Feedback

MHz

max (Tog.)

Clock Frequency, Max. Toggle

MHz

su1

GLB Reg. Setup Time before Clock,4 PT Bypass

co1

GLB Reg. Clock to Output Delay, ORP Bypass

GLB Reg. Hold Time after Clock, 4 PT Bypass

su2

GLB Reg. Setup Time before Clock

co2

GLB Reg. Clock to Output Delay

GLB Reg. Hold Time after Clock

Ext. Reset Pin to Output Delay

rw1

Ext. Reset Pulse Duration

ptoeen

Input to Output Enable

ptoedis

Input to Output Disable

External Synchronous Clock Pulse Duration, High

4.0

External Synchronous Clock Pulse Duration, Low

4.0

su3

I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)

I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

71.0

125

7.0

0.0

8.0

0.0

6.5

3.5

0.0

12.5

6.0

7.0

13.5

15.0

( )

1
twh + tw1

goeen

Global OE Output Enable

9.0

goedis

Global OE Output Disable

9.0

-125

MIN. MAX.

7.5

125

3.0

91.0

167

5.0

0.0

6.0

0.0

5.0

3.0

0.0

10.0

5.0

6.0

10.0

12.0

7.0

External Timing Parameters

Over Recommended Operating Conditions

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 1032E-70LT

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 1032E-70LT