ispLSI

1032EA

In-System Programmable High Density PLD

1032ea_03

Functional Block Diagram

Features

· HIGH DENSITY PROGRAMMABLE LOGIC

-- 6000 PLD Gates
-- 64 I/O Pins, Four Dedicated Inputs
-- 192 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

-- Small Logic Block Size for Random Logic
-- Functionally Compatible with ispLSI 1032E

· NEW FEATURES

-- 100% IEEE 1149.1 Boundary Scan Testable
-- ispJTAGTM In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

-- User Selectable 3.3V or 5V I/O Supports Mixed-

Voltage Systems (V

CCIO

Pin)

-- Open-Drain Output Option

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

max = 200 MHz Maximum Operating Frequency

pd = 4.5 ns Propagation Delay

-- TTL Compatible Inputs and Outputs
-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- 100% Tested at Time of Manufacture
-- Unused Product Term Shutdown Saves Power

· IN-SYSTEM PROGRAMMABLE

-- Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

-- Reprogram Soldered Devices for Faster Prototyping

· OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS

-- Complete Programmable Device Can Combine Glue

Logic and Structured Designs

-- Enhanced Pin Locking Capability
-- Four Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control to

Minimize Switching Noise

-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global

Interconnectivity

· ispDesignEXPERTTM LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZERTM

-- PC and UNIX Platforms

Output Routing Pool

D7 D6 D5 D4 D3 D2 D1 D0

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

CLK

Global Routing Pool (GRP)

0139A/1032EA

Logic
Array

D Q

GLB

Description

The ispLSI 1032EA is a High Density Programmable
Logic Device containing 192 Registers, 64 Universal I/O
pins, four Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1032EA features 5V in-system
programmability (ISPTM) and in-system diagnostic capa-
bilities via IEEE 1149.1 Test Access Port. The ispLSI
1032EA device offers non-volatile reprogrammability of
the logic, as well as the interconnects to provide truly
reconfigurable systems. A functional superset of the
ispLSI 1032 architecture, the ispLSI 1032EA device adds
user selectable 3.3V or 5V I/O and open-drain output
options.

The basic unit of logic on the ispLSI 1032EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1...D7 (Figure 1). There are a total of 32 GLBs in the
ispLSI 1032EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

June 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Specifications

ispLSI 1032EA

Functional Block Diagram

Figure 1. ispLSI 1032EA Functional Block Diagram

The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered
input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source
2mA or sink 8mA. Each output can be programmed
independently for fast or slow output slew rate to
minimize overall output switching noise. By connecting
the VCCIO pin to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V-compat-
ible voltages.

Eight GLBs, 16 I/O cells, dedicated inputs (if available)
and one ORP are connected together to make a
Megablock (Figure 1). The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1032EA device contains four Megablocks.

The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 1032EA device are selected using
the Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1032EA device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 1032EA are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.

I/O 63

I/O 62

I/O 61

I/O 60

RESET

Global

Routing

Pool

(GRP)

CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1

Clock

Distribution

Network

Generic

Logic Blocks

(GLBs)

Megablock

Output Routing Pool (ORP)

Input Bus

VCCIO

lnput Bus

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

IN 7

IN 6

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 35

I/O 34

I/O 33

I/O 32

I/O 0

I/O 1

I/O 2

I/O 3

I/O 12

I/O 13

I/O 14

I/O 15

TDI

TDO

TMS

TCK

I/O 8

I/O 9

I/O 10

I/O 11

I/O 4

I/O 5

I/O 6

I/O 7

I/O 47

I/O 46

I/O 45

I/O 44

GOE 1/IN 5

GOE 0/IN 4

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

0139B/1032EA

Specifications

ispLSI 1032EA

Symbol

Parameter

Min

Max

Units

btcp

TCK [BSCAN test] clock pulse width

100

btch

TCK [BSCAN test] pulse width high

tbtcl

TCK [BSCAN test] pulse width low

tbtsu

TCK [BSCAN test] setup time

tbth

TCK [BSCAN test] hold time

trf

TCK [BSCAN test] rise and fall time

mV/ns

tbtco

TAP controller falling edge of clock to valid output

tbtoz

TAP controller falling edge of clock to data output disable

tbtvo

TAP controller falling edge of clock to data output enable

tbtcpsu

BSCAN test Capture register setup time

tbtcph

BSCAN test Capture register hold time

tbtuco

BSCAN test Update reg, falling edge of clock to valid output

tbtuoz

BSCAN test Update reg, falling edge of clock to output disable

tbtuov

BSCAN test Update reg, falling edge of clock to output enable

Figure 2. Boundary Scan Waveforms and Timing Specifications

TMS

TDI

TCK

TDO

Data to be

captured

Data to be

driven out

Valid Data

Data Captured

btsu

bth

btcl

btch

btcp

btvo

btco

btoz

btcpsu

btcph

btuov

btuco

btuoz

Boundary Scan

Specifications

ispLSI 1032EA

Absolute Maximum Ratings

Supply Voltage V

.................................. -0.5 to +7.0V

Input Voltage Applied ........................ -2.5 to V

+1.0V

Off-State Output Voltage Applied ..... -2.5 to V

+1.0V

Storage Temperature ................................ -65 to 150

Case Temp. with Power Applied .............. -55 to 125

Max. Junction Temp. (T

) with Power Applied ... 150

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

= 0

C to + 70

SYMBOL

Table 2-0005/1032EA

CCIO

PARAMETER

Supply Voltage

Supply Voltage: Output Drivers

Input High Voltage

Input Low Voltage

MIN.

MAX.

UNITS

4.75

3.0

2.0

5.25

3.6

0.8

Commercial

3.3V

Capacitance (T

=25

C, f=1.0 MHz)

Erase/Reprogram Specifications

Table 2-0008/1032EA

PARAMETER

Erase/Reprogram Cycles

MINIMUM

MAXIMUM

UNITS

10000

Cycles

SYMBOL

Table 2-0006/1032EA

PARAMETER

Y0 Clock Capacitance

UNITS

TYPICAL

TEST CONDITIONS

Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)

V = 5.0V, V = 2.0V

Specifications

ispLSI 1032EA

Output Load Conditions (see Figure 3)

Switching Test Conditions

TEST CONDITION

470

390

35pF

390

35pF

470

390

35pF

Active High

Active Low

470

390

5pF

390

5pF

Active Low to Z
at V +0.5V

Active High to Z
at V -0.5V

Table 2-0004/1032EA

Figure 3. Test Load

+ 5V

Device

Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

0213a

DC Electrical Characteristics

Over Recommended Operating Conditions

Input Pulse Levels

Table 2-0003/1032EA

Input Rise and Fall Time 10% to 90%

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to 3.0V

1.5V

See Figure 3

3-state levels are measured 0.5V from
steady-state active level.

1.5ns

SYMBOL

1. One output at a time for a maximum duration of one second. V

OUT

= 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at V

= 5V and T

= 25

4. Unused inputs held at 0.0V.
5. Maximum I

varies widely with specific device configuration and operating frequency. Refer to the

Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book CD-ROM to estimate maximum I

Table 2-0007/1032EA

PARAMETER

IL-PU

2, 4, 5

Output Low Voltage

Input or I/O Low Leakage Current

Operating Power Supply Current

= 8 mA

(Max.)

= 0.0V, V

= 3.0V

CONDITION

MIN.

TYP.

MAX. UNITS

0.4

-10

Output High Voltage

= -2 mA, V

CCIO

= 3.0V

= -4 mA, V

CCIO

= 4.75V

2.4

Input or I/O High Leakage Current

CCIO

5.25V

CCIO

- 0.2)V

CCIO

I/O Active Pull-Up Current

-200

Output Short Circuit Current

CCIO

= 5.0V or 3.3V, V

OUT

= 0.5V

-240

153

TOGGLE

= 1 MHz

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