Document Outline
- Table of Contents
- ispLSI 2032E Data Sheet
- DC Electrical Characteristics
- AC Characteristics
- Pin Configuration: 44 PLCC
- Pin Configuration: 44 TQFP
- Pin Configuration: 48 TQFP
- Ordering Information
2032e_03
1
ispLSI
2032E
In-System Programmable
SuperFASTTM High Density PLD
Features
SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
-- 1000 PLD Gates
-- 32 I/O Pins, Two Dedicated Inputs
-- 32 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
-- Small Logic Block Size for Random Logic
-- 100% Functionally and JEDEC Upward Compatible
with ispLSI 2032 Devices
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
--
f
max = 225 MHz Maximum Operating Frequency
--
t
pd = 3.5 ns Propagation Delay
-- TTL Compatible Inputs and Outputs
-- 5V Programmable Logic Core
-- ispJTAGTM In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
-- User-Selectable 3.3V or 5V I/O (48-Pin Package Only)
Supports Mixed Voltage Systems
-- PCI Compatible Outputs (48-Pin Package Only)
-- Open-Drain Output Option
-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- Unused Product Term Shutdown Saves Power
ispLSI OFFERS THE FOLLOWING ADDED FEATURES
-- Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
-- Reprogram Soldered Devices for Faster Prototyping
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
-- Complete Programmable Device Can Combine Glue
Logic and Structured Designs
-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control to
Minimize Switching Noise
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERTTM LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZERTM
-- PC and UNIX Platforms
Copyright 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 1999
Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
A7
A6
A5
A4
Input Bus
Output Routing Pool (ORP)
A2
GLB
Logic
Array
D Q
D Q
D Q
D Q
0139Bisp/2000
Description
The ispLSI 2032E is a High Density Programmable Logic
Device. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2032E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2032E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
Specifications
ispLSI 2032E
2
Functional Block Diagram
Figure 1. ispLSI 2032E Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
A7
A6
A5
A4
Input Bus
Output Routing Pool (ORP)
A2
CLK 0
CLK 1
CLK 2
GOE 0
Notes:
*Y1 and RESET are multiplexed on the same pin
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
TDI/IN 0
TDO/IN 1
I/O 4
I/O 5
Y0
Y1*
TCK/Y2
BSCAN
TMS
0139/2032E
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro-
grammed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat-
ible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive (48-pin device
only).
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032E device contains one Megablock.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2032E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2032E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Specifications
ispLSI 2032E
3
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150
C
Case Temp. with Power Applied .............. -55 to 125
C
Max. Junction Temp. (T
J
) with Power Applied ... 150
C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
Capacitance (T
A
=25
C, f=1.0 MHz)
C
SYMBOL
Table 2-0006/2032E
C
PARAMETER
I/O Capacitance
UNITS
TEST CONDITIONS
1
2
Dedicated Input Capacitance
pf
pf
V = 5.0V, V = 2.0V
V = 5.0V, V = 2.0V
CC
CC
I/O
IN
C
Clock Capacitance
7
TYP
6
10
3
pf
V = 5.0V, V = 2.0V
CC
Y
Table 2-0008/2032E
PARAMETER
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
10,000
Cycles
T
A
= 0
C to +70
C
SYMBOL
Table 2-0005/2032E
V
CC
V
IH
V
IL
PARAMETER
Supply Voltage: Logic Core, Input Buffers
Input High Voltage
Input Low Voltage
1. 3.3V I/O operation not available for 44-pin packages.
MIN.
MAX.
UNITS
4.75
2.0
0
5.25
V
cc
+1
0.8
V
V
CCIO
1
Supply Voltage: Output Drivers
4.75
5.25
V
3.3V
5V
3.0
3.6
V
V
V
Erase/Reprogram Specification
Specifications
ispLSI 2032E
4
+ 5V
R1
R2
CL
*
Device
Output
Test
Point
*
CL includes Test Fixture and Probe Capacitance.
0213A
DC Electrical Characteristics
Over Recommended Operating Conditions
1
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
R2
CL
A
470
390
35pF
B
390
35pF
470
390
35pF
Active High
Active Low
C
470
390
5pF
390
5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2 - 0004A
Input Pulse Levels
Table 2-0003/2032E
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
1.5 ns
Figure 2. Test Load
V
OL
SYMBOL
1. One output at a time for a maximum duration of one second (V
OUT
= 0.5V). Characterized, but not 100% tested.
2. Meaured using two 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25
C.
4. Unused inputs held at 0.0V.
5. Available in 48-pin package only.
6. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum I
CC
.
Table 2-0007/2032E
V
OH
I
IH
I
IL
PARAMETER
I
IL-PU
I
OS
1
I
CC
2,4,6
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
I/O Active Pull-Up Current, non-PCI
Output Short Circuit Current, non-PCI
Operating Power Supply Current
I
OL
= 8 mA
I
OH
= -4 mA
0V
V
IN
V
IL
(Max.)
0V
V
IN
2.0V
V
CCIO
= 5V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 3.0V
CONDITION
MIN.
TYP.
3
MAX. UNITS
2.4
-10
0.4
10
-10
10
-150
-200
V
V
A
Input or I/O High Leakage Current
V
CCIO
V
IN
5.25V
(V
CCIO
- 0.2)V
V
IN
V
CCIO
A
A
A
I/O Active Pull-Up Current, PCI
5
0V
V
IN
2.0V
-10
-250
A
mA
Output Short Circuit Current, PCI
5
V
CCIO
= 5.0V or 3.3V, V
OUT
= 0.5V
-240
mA
85
mA
65
-225/-200
Others
mA
f
TOGGLE
= 1 MHz
Switching Test Conditions
Specifications
ispLSI 2032E
5
U
S
E
2
0
3
2
E
-2
2
5
F
O
R
N
E
W
D
E
S
IG
N
S
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
-200
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/2032E
1
1
tsu2 + tco1
( )
-180
MIN.
MAX.
MAX.
DESCRIPTION
#
2
4
PARAMETER
A
1
Data Prop. Delay, 4PT Bypass, ORP Bypass
3.5
5.0
ns
t
pd2
A
2
Data Prop. Delay
ns
f
max
A
3
Clk Frequency with Int. Feedback
3
200
180
MHz
f
max (Ext.)
4
Clk Frequency with Ext. Feedback
MHz
f
max (Tog.)
5
Clk Frequency, Max. Toggle
MHz
t
su1
6
GLB Reg. Setup Time before Clk, 4 PT Bypass
ns
t
co1
A
7
GLB Reg. Clk to Output Delay, ORP Bypass
ns
t
h1
8
GLB Reg. Hold Time after Clk, 4 PT Bypass
0.0
ns
t
su2
9
GLB Reg. Setup Time before Clk
3.5
ns
t
co2
10 GLB Reg. Clk to Output Delay
ns
t
h2
11 GLB Reg. Hold Time after Clk
0.0
ns
t
r1
A
12 Ext. Reset Pin to Output Delay, ORP Bypass
ns
t
rw1
13 Ext. Reset Pulse Duration
3.5
ns
t
ptoeen
B
14 Input to Output Enable
ns
t
ptoedis
C
15 Input to Output Disable
ns
t
goeen
B
16 Global OE Output Enable
ns
t
goedis
C
17 Global OE Output Disable
ns
t
wh
18 Ext. Synch. Clk Pulse Duration, High
2.0
ns
t
wl
19 Ext. Synch. Clk Pulse Duration, Low
2.0
ns
167
250
2.5
2.5
3.5
5.0
7.0
7.0
3.5
3.5
5.5
-225
MIN. MAX.
3.5
225
0.0
3.5
0.0
3.5
2.0
2.0
167
250
2.5
2.5
3.5
5.0
7.0
7.0
3.5
3.5
5.5
125
200
3.0
0.0
4.0
0.0
4.0
2.5
2.5
7.5
4.0
4.5
6.5
10.0
10.0
5.0
5.0
Specifications
ispLSI 2032E
6
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
-135
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B/2032E
1
1
tsu2 + tco1
( )
-110
MIN.
MAX.
MAX.
DESCRIPTION
#
2
4
PARAMETER
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
7.5
10.0
ns
t
pd2
A
2
Data Propagation Delay
ns
f
max
A
3
Clock Frequency with Internal Feedback
3
137
111
MHz
f
max (Ext.)
4
Clock Frequency with External Feedback
MHz
f
max (Tog.)
5
Clock Frequency, Max. Toggle
MHz
t
su1
6
GLB Register Setup Time before Clock, 4 PT Bypass
ns
t
co1
A
7
GLB Register Clock to Output Delay, ORP Bypass
ns
t
h1
8
GLB Register Hold Time after Clock, 4 PT Bypass
0.0
ns
t
su2
9
GLB Register Setup Time before Clock
5.5
ns
t
co2
10 GLB Register Clock to Output Delay
ns
t
h2
11 GLB Register Hold Time after Clock
0.0
ns
t
r1
A
12 External Reset Pin to Output Delay, ORP Bypass
ns
t
rw1
13 External Reset Pulse Duration
5.0
ns
t
ptoeen
B
14 Input to Output Enable
ns
t
ptoedis
C
15 Input to Output Disable
ns
t
goeen
B
16 Global OE Output Enable
ns
t
goedis
C
17 Global OE Output Disable
ns
t
wh
18 External Synchronous Clock Pulse Duration, High
3.0
ns
t
wl
19 External Synchronous Clock Pulse Duration, Low
3.0
ns
100
167
4.0
4.5
5.5
9.0
12.0
12.0
6.0
6.0
10.0
77.0
125
5.5
0.0
7.5
0.0
6.5
4.0
4.0
13.0
5.5
6.5
12.5
14.5
14.5
7.0
7.0
Specifications
ispLSI 2032E
7
U
S
E
2
0
3
2
E
-2
2
5
F
O
R
N
E
W
D
E
S
IG
N
S
Over Recommended Operating Conditions
Internal Timing Parameters
1
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2032E
Inputs
UNITS
-200
MIN.
-180
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
20 Input Buffer Delay
0.6
ns
t
din
21 Dedicated Input Delay
1.3
ns
t
grp
22 GRP Delay
0.7
ns
GLB
t
1ptxor
25 1 Product Term/XOR Path Delay
3.8
ns
t
20ptxor
26 20 Product Term/XOR Path Delay
3.8
ns
t
xoradj
27 XOR Adjacent Path Delay
3.8
ns
t
gbp
28 GLB Register Bypass Delay
0.0
ns
t
gsu
29 GLB Register Setup Time before Clock
0.3
ns
t
gh
30 GLB Register Hold Time after Clock
2.7
ns
t
gco
31 GLB Register Clock to Output Delay
0.7
ns
3
t
gro
32 GLB Register Reset to Output Delay
1.1
ns
t
ptre
33 GLB Product Term Reset to Register Delay
2.9
ns
t
ptoe
34 GLB Product Term Output Enable to I/O Cell Delay
5.9
ns
t
ptck
35 GLB Product Term Clock Delay
1.5
3.7
ns
ORP
t
ob
38 Output Buffer Delay
1.3
ns
0.4
1.3
GRP
0.7
t
4ptbpc
23 4 Product Term Bypass Path Delay (Combinatorial)
1.8
ns
t
4ptbpr
24 4 Product Term Bypass Path Delay (Registered)
2.8
ns
2.8
2.8
2.8
0.0
1.8
1.8
0.8
1.7
0.7
2.9
2.5
4.4
0.7
3.2
t
orp
36 ORP Delay
1.1
ns
t
orpbp
37 ORP Bypass Delay
0.6
ns
1.0
0.0
Outputs
0.6
t
sl
39 Output Slew Limited Delay Adder
1.5
ns
1.5
t
oen
40 I/O Cell OE to Output Enabled
2.8
ns
t
odis
41 I/O Cell OE to Output Disabled
2.8
ns
1.5
1.5
t
goe
42 Global Output Enable
2.2
ns
2.0
t
gy0
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
1.2
1.4
1.4
ns
t
gy1/2
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.4
1.6
1.6
ns
Clocks
1.2
1.4
t
gr
45 Global Reset to GLB
3.5
ns
Global Reset
2.7
-225
MIN. MAX.
0.6
1.3
0.7
2.2
2.2
2.2
0.0
1.2
1.2
0.8
1.7
0.7
1.3
2.5
4.2
0.3
2.8
1.0
0.0
1.0
1.5
1.5
1.5
2.0
0.8
1.0
0.8
1.0
2.7
Specifications
ispLSI 2032E
8
Internal Timing Parameters
1
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036B/2032E
Inputs
UNITS
-135
MIN.
-110
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
20 Input Buffer Delay
1.7
ns
t
din
21 Dedicated Input Delay
3.4
ns
t
grp
22 GRP Delay
1.7
ns
GLB
t
1ptxor
25 1 Product Term/XOR Path Delay
6.2
ns
t
20ptxor
26 20 Product Term/XOR Path Delay
6.8
ns
t
xoradj
27 XOR Adjacent Path Delay
7.5
ns
t
gbp
28 GLB Register Bypass Delay
0.1
ns
t
gsu
29 GLB Register Setup Time before Clock
0.5
ns
t
gh
30 GLB Register Hold Time after Clock
4.0
ns
t
gco
31 GLB Register Clock to Output Delay
0.6
ns
3
t
gro
32 GLB Register Reset to Output Delay
1.8
ns
t
ptre
33 GLB Product Term Reset to Register Delay
5.9
ns
t
ptoe
34 GLB Product Term Output Enable to I/O Cell Delay
7.1
ns
t
ptck
35 GLB Product Term Clock Delay
4.0
7.0
ns
ORP
t
ob
38 Output Buffer Delay
1.2
ns
1.1
2.4
GRP
1.3
t
4ptbpc
23 4 Product Term Bypass Path Delay (Combinatorial)
4.9
ns
t
4ptbpr
24 4 Product Term Bypass Path Delay (Registered)
4.8
ns
5.0
5.1
5.6
0.0
3.6
3.6
0.3
3.0
0.7
1.1
4.4
6.4
2.9
5.2
t
orp
36 ORP Delay
1.5
ns
t
orpbp
37 ORP Bypass Delay
0.5
ns
1.3
0.3
Outputs
1.2
t
sl
39 Output Slew Limited Delay Adder
10.0
ns
10.0
t
oen
40 I/O Cell OE to Output Enabled
4.0
ns
t
odis
41 I/O Cell OE to Output Disabled
4.0
ns
3.2
3.2
t
goe
42 Global Output Enable
3.0
ns
2.8
t
gy0
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
2.3
3.2
3.2
ns
t
gy1/2
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.3
3.2
3.2
ns
Clocks
2.3
2.3
t
gr
45 Global Reset to GLB
9.0
ns
Global Reset
6.4
Specifications
ispLSI 2032E
9
ispLSI 2032E Timing Model
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
=
t
su
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.6 + 0.7 + 2.2) + (0.8) - (0.6 + 0.7 + 0.3)
=
=
=
=
t
h
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2)
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 2.8) + (0.7) + (1.0 + 1.0)
Table 2-0042/2032E
Note: Calculations are based upon timing specifications for the ispLSI 2032E-225L
2.7
2.3
6.8
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
I/O Pin
(Input)
Y0,1,2
GRP
GLB Reg Bypass
ORP Bypass
D
Q
RST
RE
OE
CK
I/O Delay
I/O Cell
ORP
GLB
GRP
I/O Cell
#24
#25, 26, 27
#33, 34,
35
#43, 44
#36
Reset
Ded. In
#21
#20
#28
#29, 30,
31, 32
#38,
#39
GOE 0
#42
#40, 41
0491/2032E
#22
Comb 4 PT Bypass #23
#37
#45
Specifications
ispLSI 2032E
10
Power consumption in the ispLSI 2032E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3 shows the relationship between power and
operating speed.
Figure 3. Typical Device Power Consumption vs fmax
Power Consumption
0127A/2032E
I
CC
can be estimated for the ispLSI 2032E using the following equation:
For 2032E-225 and -200: ICC = 4.5 + (# of PTs * 1.3) + (# of nets * Max freq * 0.0035)
For 2032E-180 and Slower: ICC
= 4.5 + (# of PTs * 1.02) + (# of nets * Max freq * 0.0035)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I
CC
estimate is based on typical conditions (V
CC
= 5.0V, room temperature) and an assumption of two GLB
loads on average exists. These values are for estimates only. Since the value of I
CC
is sensitive to operating
conditions and the program in the device, the actual I
CC
should be verified.
60
80
100
1
20
40
60
80
100 120 140 160 180
200 220 240
f
max (MHz)
I
CC (mA)
Notes: Configuration of two 16-bit counters
Typical current at 5V, 25
C
90
70
40
50
110
120
130
140
150
ispLSI 2032E-225 and -200
ispLSI 2032E-180
and Slower
Specifications
ispLSI 2032E
11
Pin Description
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, V
CC
or GND.
Input/Output Pins -- These are the general purpose
I/O pins used by the logic array.
NAME
Table 2-0002/2032E
44-PIN PLCC
PIN NUMBERS
DESCRIPTION
15,
19,
25,
29,
37,
41,
3,
7,
16,
20,
26,
30,
38,
42,
4,
8,
17,
21,
27,
31,
39,
43,
5,
9,
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
18,
22,
28,
32,
40,
44,
6,
10
Global Output Enable input pin.
2
GOE 0
1,
23
GND
V
CC
12, 34
17, 39
6,
28
24, 48
6,
30
VCC
Supply voltage for output drivers, 5V or 3.3V. All
VCCIO pins must be connected to the same voltage
level.
12, 18, 36, 42
VCCIO
Ground (GND)
Input -- This pin performs two functions. When
BSCAN
is logic low, it functions as an input pin to load
programming data into the device. TDI/IN0 also is used
as one of the two control pins for the ISP state
machine. When
BSCAN
is high, it functions as a
dedicated input pin.
Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
This pin performs two functions:
Input -- Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The TMS, TDI, TDO and TCK
controls become active.
RESET
/Y1
Y0
TDI/IN 0
1
BSCAN
TMS/NC
2
Input -- When in ISP mode, controls operation of ISP
state machine.
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
Output/Input -- This pin performs two functions. When
BSCAN
is logic low, it functions as an output pin to
read serial shift register data. When
BSCAN
is high, it
functions as a dedicated input pin.
TDO/IN 1
1
Input -- This pin performs two functions. When
BSCAN
is logic low, it functions as a clock pin for the
Serial Shift Register. When
BSCAN
is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
TCK/Y2
1
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
35
11
14
13
36
24
33
44-PIN TQFP
PIN NUMBERS
48-PIN TQFP
PIN NUMBERS
9,
13,
19,
23,
31
35,
41,
1,
10,
14,
20,
24,
32,
36,
42,
2,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
40
5
29
7
8
30
18
27
9,
14,
20,
25,
33,
38,
44,
1,
10,
15,
21,
26,
34,
39,
45,
2,
11,
16,
22,
27,
35,
40,
46,
3,
13,
17,
23,
28,
37,
41,
47,
4
43
5
31
7
8
32
19
29
Specifications
ispLSI 2032E
12
Pin Configuration
ispLSI 2032E 44-Pin PLCC Pinout Diagram
ispLSI 2032E 44-Pin TQFP Pinout Diagram
I/O 18
I/O 17
I/O 16
TMS/NC
2
RESET/Y1
1
VCC
TCK/Y2
1
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
BSCAN
1
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1
TDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
7
8
9
10
12
11
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6
18
5
19
4
20
3
21
2
22
1
23
44
24
43
25
42
26
41
27
40
28
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, V
CC
or GND.
ispLSI 2032E
Top View
44PLCC/2032E
I/O 18
I/O 17
I/O 16
TMS/NC
2
RESET/Y1
1
VCC
TCK/Y2
1
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
BSCAN
1
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1
TDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 2032E
Top View
1
2
3
4
6
5
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
44TQFP/2032E
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, V
CC
or GND.
Specifications
ispLSI 2032E
13
Pin Configuration
ispLSI 2032E 48-Pin TQFP Pinout Diagram
I/O 18
I/O 17
I/O 16
TMS/NC
2
RESET/Y1
1
VCC
TCK/Y2
1
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
BSCAN
1
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1
TDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 2032E
Top View
1
2
3
4
6
5
7
8
9
10
11
35
34
33
32
31
30
29
28
27
26
25
47
13
46
14
45
15
44
16
43
17
42
18
41
19
40
20
39
21
38
22
37
23
48TQFP/2032E
GND
12
VCCIO
24
GND
36
VCCIO
48
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, V
CC
or GND.
Specifications
ispLSI 2032E
14
ispLSI 2032E Ordering Information
180
180
44-Pin TQFP
5.0
5.0
ispLSI 2032E-180LT44
48-Pin TQFP
ispLSI 2032E-180LT48
Table 2-0041/2032E
FAMILY
fmax (MHz)
225
225
225
ORDERING NUMBER
PACKAGE
44-Pin PLCC
44-Pin TQFP
tpd (ns)
3.5
3.5
3.5
ispLSI
ispLSI 2032E-225LJ44
ispLSI 2032E-225LT44
48-Pin TQFP
ispLSI 2032E-225LT48
180
44-Pin PLCC
5.0
ispLSI 2032E-180LJ44
110
110
*2032E-225 recommended for new designs.
44-Pin TQFP
10.0
10.0
ispLSI 2032E-110LT44
48-Pin TQFP
ispLSI 2032E-110LT48
135
135
135
44-Pin PLCC
44-Pin TQFP
7.5
7.5
7.5
ispLSI 2032E-135LJ44
ispLSI 2032E-135LT44
48-Pin TQFP
ispLSI 2032E-135LT48
110
44-Pin PLCC
10.0
ispLSI 2032E-110LJ44
200
200
200
44-Pin PLCC
44-Pin TQFP
3.5
3.5
3.5
ispLSI 2032E-200LJ44*
ispLSI 2032E-200LT44*
48-Pin TQFP
ispLSI 2032E-200LT48*
COMMERCIAL
Part Number Description
Device Number
ispLSI 2032E
XXX
X
XXX
Grade
Blank = Commercial
X
Speed
225 = 225 MHz
f
max
200 = 200 MHz
f
max
180 = 180 MHz
f
max
135 = 135 MHz
f
max
110 = 110 MHz
f
max
Power
L = Low
Package
J44 = PLCC
T44 = TQFP
T48 = TQFP
Device Family
0212/2032E
PDF 
ZIP