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Электронный компонент: 2032VE

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ispLSI
2032VE
3.3V In-System Programmable
High Density SuperFASTTM PLD
2032ve_07
1
Features
SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
-- 1000 PLD Gates
-- 32 I/O Pins, Two Dedicated Inputs
-- 32 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
-- Small Logic Block Size for Random Logic
-- 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2032V Devices
3.3V LOW VOLTAGE 2032 ARCHITECTURE
-- Interfaces With Standard 5V TTL Devices
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
--
f
max = 225 MHz Maximum Operating Frequency
--
t
pd = 4.0 ns Propagation Delay
-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- 100% Tested at Time of Manufacture
-- Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
-- 3.3V In-System Programmability Using Boundary
Scan Test Access Port (TAP)
-- Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
-- Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
-- Reprogram Soldered Devices for Faster Prototyping
100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERTTM LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZERTM
-- PC and UNIX Platforms
Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
A7
A6
A5
A4
Input Bus
Output Routing Pool (ORP)
A2
GLB
Logic
Array
D Q
D Q
D Q
D Q
0139Bisp/2000
Description
The ispLSI 2032VE is a High Density Programmable
Logic Device that can be used in both 3.3V and 5V
systems. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides
complete interconnectivity between all of these elements.
The ispLSI 2032VE features in-system programmability
through the Boundary Scan Test Access Port (TAP) and
is 100% IEEE 1149.1 Boundary Scan Testable. The
ispLSI 2032VE offers non-volatile reprogrammability of
the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 2032VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
September 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Specifications
ispLSI 2032VE
2
Functional Block Diagram
Figure 1. ispLSI 2032VE Functional Block Diagram
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro-
grammed independently for fast or slow output slew rate
to minimize overall output switching noise. Device pins
can be safely driven to 5 Volt signal levels to support
mixed-voltage systems.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032VE device contains one Megablock.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2032VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock
can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2032VE are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
A7
A6
A5
A4
Input Bus
Output Routing Pool (ORP)
A2
CLK 0
CLK 1
CLK 2
GOE 0
Note: *Y1 and RESET are multiplexed on the same pin
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
TDI/IN 0
TDO/IN 1
I/O 4
I/O 5
Y0
Y1*
TCK/Y2
BSCAN
TMS/NC
0139B/2032VE
Generic Logic
Blocks (GLBs)
Specifications
ispLSI 2032VE
3
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature .............................. -65 to +150
C
Case Temp. with Power Applied .............. -55 to 125
C
Max. Junction Temp. (T
J
) with Power Applied ... 150
C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
C
SYMBOL
Table 2-0006/2032VE
C
PARAMETER
I/O Capacitance
6
UNITS
TYPICAL
TEST CONDITIONS
1
2
8
Dedicated Input Capacitance
pf
pf
V = 3.3V, V = 0.0V
V = 3.3V, V = 0.0V
CC
CC
I/O
IN
C
Clock Capacitance
10
3
pf
V = 3.3V, V = 0.0V
CC
Y
T
A
= 0
C to + 70
C
T
A
= -40
C to + 85
C
SYMBOL
Table 2-0005/2032VE
V
CC
V
IH
V
IL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN.
MAX.
UNITS
3.0
3.0
2.0
V 0.5
3.6
3.6
5.25
0.8
V
V
V
V
SS
Commercial
Industrial
Erase Reprogram Specifications
Table 2-0008A/2032VE
PARAMETER
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
10,000
Cycles
Capacitance (T
A
=25
C, f=1.0 MHz)
DC Recommended Operating Condition
Specifications
ispLSI 2032VE
4
Switching Test Conditions
Input Pulse Levels
Table 2-0003/2032VE
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
1.5 ns
Output Load Conditions (see Figure 2)
DC Electrical Characteristics
Over Recommended Operating Conditions
Figure 2. Test Load
+ 3.3V
R1
R2
CL
*
Device
Output
Test
Point
*
CL includes Test Fixture and Probe Capacitance.
0213A/2032VE
TEST CONDITION
R1
R2
CL
A
316
348
35pF
B
348
35pF
316
348
35pF
Active High
Active Low
C
316
348
5pF
348
5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004A/2032VE
V
OL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using two 16-bit counters.
3. Typical values are at V = 3.3V and T = 25
C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to Power Consumption section
of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum I .
5. Unused inputs at V = 0V.
Table 2-0007/2032VE
1
V
OH
I
IH
I
IL
I
IL-isp
PARAMETER
I
IL-PU
I
OS
2, 4, 5
I
CC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
BSCAN
Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
V
V
5.25V
0V
V
V (Max.)
0V
V
V
0V
V
V
V = 3.3V, V = 0.5V
V = 0.0V, V = 3.0V
f = 1 MHz
OL
OH
IN IL
IN
IL
IN IL
CC OUT
TOGGLE
IL IH
CONDITION
MIN.
TYP.
MAX.
UNITS
3
2.4
80
-300/-225
0.4
10
-10
10
-150
-150
-100
V
V
A
A
A
A
A
mA
mA
CC
IL
A
OUT
Others
mA
65
CC
IN
CC
CC
(V - 0.2)V
V
V
CC
IN
CC
Specifications
ispLSI 2032VE
5
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
4. -225 speed grade supercedes earlier -200. All parameters other than fmax (internal) are the same.
Table 2-0030A/2032VE
1
4
3
2
1
tsu2 + tco1
( )
DESCRIPTION
#
PARAMETER
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
ns
t
pd2
A
2
Data Propagation Delay
ns
f
max
A
3
Clock Frequency with Internal Feedback
MHz
f
max (Ext.)
4
Clock Frequency with External Feedback
MHz
f
max (Tog.)
5
Clock Frequency, Max. Toggle
MHz
t
su1
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
ns
t
co1
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
ns
t
h1
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
ns
t
su2
9
GLB Reg. Setup Time before Clock
ns
t
co2
A
10
GLB Reg. Clock to Output Delay
ns
t
h2
11
GLB Reg. Hold Time after Clock
ns
t
r1
A
12
Ext. Reset Pin to Output Delay, ORP Bypass
ns
t
rw1
13
Ext. Reset Pulse Duration
ns
t
ptoeen
B
14
Input to Output Enable
ns
t
ptoedis
C
15
Input to Output Disable
ns
t
goeen
B
16
Global OE Output Enable
ns
t
goedis
C
17
Global OE Output Disable
ns
t
wh
18
External Synchronous Clock Pulse Duration, High
ns
t
wl
19
External Synchronous Clock Pulse Duration, Low
ns
-225
MIN. MAX.
4.0
225
0.0
3.5
0.0
3.5
2.0
2.0
154
250
2.5
3.0
4.0
5.0
7.0
7.0
3.5
3.5
6.0
-180
MIN. MAX.
5.0
180
125
200
3.0
0.0
4.0
0.0
4.0
2.5
2.5
7.5
4.0
5.0
6.0
10.0
10.0
5.0
5.0