GAL16LV8
Low Voltage E
2
CMOS PLD
Generic Array LogicTM
1
Features
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
-- 3.5 ns Maximum Propagation Delay
-- Fmax = 250 MHz
-- 2.5 ns Maximum from Clock Input to Data Output
-- UltraMOS
Advanced CMOS Technology
3.3V LOW VOLTAGE 16V8 ARCHITECTURE
-- JEDEC-Compatible 3.3V Interface Standard
-- 5V Compatible Inputs
-- I/O Interfaces with Standard 5V TTL Devices
(GAL16LV8C)
ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
E
2
CELL TECHNOLOGY
-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention
EIGHT OUTPUT LOGIC MACROCELLS
-- Maximum Flexibility for Complex Logic Designs
-- Programmable Output Polarity
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-- 100% Functional Testability
APPLICATIONS INCLUDE:
-- Glue Logic for 3.3V Systems
-- DMA Control
-- State Machine Control
-- High Speed Graphics Processing
-- Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
Copyright 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
December 1997
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
I/CLK
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
CLK
8
8
8
8
8
8
8
8
OE
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
PROGRAMMABLE
AND-ARRAY
(64 X 32)
I/OE
GAL16LV8
Top View
PLCC
2
20
I/CLK
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
4
6
8
9
11
13
14
16
18
16lv8_04
New 5V
Tolerant
Inputs on
16L
V8D
Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL16LV8C can interface with both 3.3V and 5V
signal levels. The GAL16LV8 is manufactured using Lattice
Semiconductor's advanced 3.3V E
2
CMOS process, which com-
bines CMOS with Electrically Erasable (E
2
) floating gate technology.
High speed erase times (<100ms) allow the devices to be repro-
grammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 archi-
tecture as its 5V counterpart and supports all architectural features
such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
Pin Configuration
Specifications
GAL16LV8
2
Commercial Grade Specifications
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2
Blank = Commercial
Grade
Package
Power
L = Low Power
Speed (ns)
XXXXXXXX
XX
X
X X
Device Name
_
J = PLCC
GAL16LV8D
GAL16LV8C
GAL16LV8 Ordering Information
Part Number Description
Specifications
GAL16LV8
3
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
are illustrated in the following pages. Two global bits, SYN and
AC0, control the mode configuration for all macrocells. The XOR
bit of each macrocell controls the polarity of the output in any of the
three modes, while the AC1 bit of each of the macrocells controls
the input/output configuration. These two global and 16 individ-
ual architecture bits define all possible configurations in a
GAL16LV8. The information given on these architecture bits is only
to give a better understanding of the device. Compiler software will
transparently set these architecture bits from the pin definitions, so
the user should not need to directly manipulate these architecture
bits.
The following is a list of the PAL architectures that the GAL16LV8
can emulate. It also shows the OLMC mode under which the
GAL16LV8 emulates the PAL architecture.
PAL Architectures
GAL16LV8
Emulated by GAL16LV8
Global OLMC Mode
16R8
Registered
16R6
Registered
16R4
Registered
16RP8
Registered
16RP6
Registered
16RP4
Registered
16L8
Complex
16H8
Complex
16P8
Complex
10L8
Simple
12L6
Simple
14L4
Simple
16L2
Simple
10H8
Simple
12H6
Simple
14H4
Simple
16H2
Simple
10P8
Simple
12P6
Simple
14P4
Simple
16P2
Simple
Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft-
ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 11 are permanently configured
as clock and output enable, respectively. These pins cannot be con-
figured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
Registered
Complex
Simple
Auto Mode Select
ABEL
P16V8R
P16V8C
P16V8AS
P16V8
CUPL
G16V8MS
G16V8MA
G16V8AS
G16V8
LOG/iC
GAL16V8_R
GAL16V8_C7
GAL16V8_C8
GAL16V8
OrCAD-PLD
"Registered"
1
"Complex"
1
"Simple"
1
GAL16V8A
PLDesigner
P16V8R
2
P16V8C
2
P16V8C
2
P16V8A
TANGO-PLD
G16V8R
G16V8C
G16V8AS
3
G16V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
Output Logic Macrocell (OLMC)
Compiler Support for OLMC
Specifications
GAL16LV8
4
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to the
common 16R8 and 16RP4 devices with various permutations of
polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub-
sets of the I/O function.
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common
OE
for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE
for registered output configuration.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE
for registered output configuration.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
D
Q
Q
CLK
OE
XOR
XOR
Registered Mode
Specifications
GAL16LV8
5
PLCC Package Pinout
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
0000
0224
0256
0480
0512
0736
0768
0992
1024
1248
1280
1504
1536
1760
1792
2016
19
XOR-2048
AC1-2120
XOR-2049
AC1-2121
XOR-2050
AC1-2122
XOR-2051
AC1-2123
XOR-2052
AC1-2124
XOR-2053
AC1-2125
XOR-2054
AC1-2126
XOR-2055
AC1-2127
28
24
20
16
12
8
4
0
PTD
2128
2191
OE
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
SYN-2192
AC0-2193
Registered Mode Logic Diagram
PDF 
ZIP