GAL18V10
High Performance E
2
CMOS PLD
Generic Array LogicTM
1
2
20
I/CLK
I
I
I
I
I
I
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
GND
I/O/Q I/O/Q
I/O/Q
I/O/Q
4
6
8
9
11
13
14
16
18
1
10
11
20
I/CLK
I
I
I
I
I
I
I
I/O/Q
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
5
15
GAL18V10
Top View
GAL
18V10
DIP
PLCC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/CLK
RESET
PRESET
8
8
8
8
10
10
8
8
8
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I
I
I
I
I
I
I
PROGRAMMABLE
AND-ARRAY
(96X36)
Copyright 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
July 1997
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
18v10_03
Features
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
-- 7.5 ns Maximum Propagation Delay
-- Fmax = 111 MHz
-- 5.5 ns Maximum from Clock Input to Data Output
-- TTL Compatible 16 mA Outputs
-- UltraMOS
Advanced CMOS Technology
LOW POWER CMOS
-- 75 mA Typical Icc
ACTIVE PULL-UPS ON ALL PINS
E
2
CELL TECHNOLOGY
-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention
TEN OUTPUT LOGIC MACROCELLS
-- Uses Standard 22V10 Macrocell Architecture
-- Maximum Flexibility for Complex Logic Designs
PRELOAD AND POWER-ON RESET OF REGISTERS
-- 100% Functional Testability
APPLICATIONS INCLUDE:
-- DMA Control
-- State Machine Control
-- High Speed Graphics Processing
-- Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL18V10, at 7.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
2
) floating gate technology to provide a very flexible 20-pin
PLD. CMOS circuitry allows the GAL18V10 to consume much less
power when compared to its bipolar counterparts. The E
2
technol-
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
By building on the popular 22V10 architecture, the GAL18V10
eliminates the learning curve usually associated with using a new
device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V10 OLMC is fully com-
patible with the OLMC in standard bipolar and CMOS 22V10 de-
vices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
Pin Configuration
Specifications
GAL18V10
2
)
s
n
(
d
p
T
)
s
n
(
u
s
T
)
s
n
(
o
c
T
)
A
m
(
c
c
I
#
g
n
i
r
e
d
r
O
e
g
a
k
c
a
P
5
.
7
6
5
.
5
5
1
1
0
1
V
8
1
L
A
G
B-7 P
L
P
I
D
c
i
t
s
a
l
P
n
i
P
-
0
2
5
1
1
0
1
V
8
1
L
A
G
B-7 J
L
C
C
L
P
d
a
e
L
-
0
2
0
1
7
7
5
1
1
0
1
V
8
1
L
A
G
B 1
- 0 P
L
P
I
D
c
i
t
s
a
l
P
n
i
P
-
0
2
5
1
1
0
1
V
8
1
L
A
G
B 1
- 0 J
L
C
C
L
P
d
a
e
L
-
0
2
5
1
8
0
1
5
1
1
0
1
V
8
1
L
A
G
B
P
L
5
1
-
P
I
D
c
i
t
s
a
l
P
n
i
P
-
0
2
5
1
1
0
1
V
8
1
L
A
G
B
J
L
5
1
-
C
C
L
P
d
a
e
L
-
0
2
5
1
1
P
L
5
1
-
0
1
V
8
1
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
0
2
5
1
1
J
L
5
1
-
0
1
V
8
1
L
A
G
C
C
L
P
d
a
e
L
-
0
2
0
2
2
1
2
1
5
1
1
0
1
V
8
1
L
A
G
B
P
L
0
2
-
P
I
D
c
i
t
s
a
l
P
n
i
P
-
0
2
5
1
1
0
1
V
8
1
L
A
G
B
J
L
0
2
-
C
C
L
P
d
a
e
L
-
0
2
5
1
1
P
L
0
2
-
0
1
V
8
1
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
0
2
5
1
1
J
L
0
2
-
0
1
V
8
1
L
A
G
C
C
L
P
d
a
e
L
-
0
2
Blank = Commercial
Grade
Package
Power
L = Low Power
Speed (ns)
XXXXXXXX
XX
X
X X
Device Name
_
P = Plastic DIP
J = PLCC
GAL18V10B
GAL18V10
GAL18V10 Ordering Information
Commercial Grade Specifications
Part Number Description
Specifications
GAL18V10
3
GAL18V10 OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the GAL18V10 has two primary functional
modes: registered, and combinatorial I/O. The modes and the
output polarity are set by two bits (SO and S1), which are normally
controlled by the logic compiler. Each of these two primary modes,
and the bit settings required to enable them, are described below
and on the the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC's D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop's /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
"on" (dedicated output), "off" (dedicated input), or "product-term
driven" (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
The GAL18V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registered outputs to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers
to a logic one on the rising edge of the next clock pulse after this
product term is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
The GAL18V10 has a variable number of product terms per OLMC.
Of the ten available OLMCs, two OLMCs have access to ten prod-
uct terms (pins 14 and 15), and the other eight OLMCs have eight
product terms each. In addition to the product terms available for
logic, each OLMC has an additional product-term dedicated to out-
put enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
A R
S P
D
Q
Q
C L K
4 T O 1
M U X
2 T O 1
M U X
Output Logic Macrocell (OLMC)
Output Logic Macrocell Configurations
Specifications
GAL18V10
4
ACTIVE HIGH
ACTIVE LOW
ACTIVE HIGH
ACTIVE LOW
S
0
= 1
S
1
= 1
S
0
= 0
S
1
= 1
S
0
= 0
S
1
= 0
S
0
= 1
S
1
= 0
A R
S P
D
Q
Q
C L K
A R
S P
D
Q
Q
C L K
Registered Mode
Combinatorial Mode
Specifications
GAL18V10
5
DIP and PLCC Package Pinouts
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
1
0036
.
.
.
0324
19
OLMC
S0
3456
S1
3457
18
17
16
15
14
13
12
11
9
0
4
8
12
16
20
24
28
32
OLMC
S0
3458
S1
3459
OLMC
SO
3460
S1
3461
OLMC
S0
3462
S1
3463
OLMC
S0
3464
S1
3465
OLMC
S0
3466
S1
3467
OLMC
S0
3468
S1
3469
OLMC
S0
3470
S1
3471
OLMC
S0
3472
S1
3473
OLMC
S0
3474
S1
3475
0000
0360
.
.
.
0648
0684
.
.
.
0972
1008
.
.
.
1296
1332
.
.
.
.
1692
2448
.
.
.
2736
1728
.
.
.
.
2088
2124
.
.
.
2412
2772
.
.
.
3060
3096
.
.
.
3384
2
3
4
5
6
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
3420
7
8
Electronic Signature
3476, 3477 ...
... 3538, 3539
L
S
B
M
S
B
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
8
8
8
8
10
10
8
8
8
8
GAL18V10 Logic Diagram/JEDEC Fuse Map
Specifications
GAL18V10B
6
COMMERCIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V
L -7/-10/-15/-20
--
75
115
mA
Supply Current
f
toggle
= 15MHz Outputs Open
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
3
MAX.
UNITS
V
IL
Input Low Voltage
Vss 0.5
--
0.8
V
V
IH
Input High Voltage
2.0
--
Vcc+1
V
I
IL
1
Input or I/O Low Leakage Current
0V
V
IN
V
IL
(MAX.)
--
--
100
A
I
IH
Input or I/O High Leakage Current
3.5V
V
IN
V
CC
--
--
10
A
V
OL
Output Low Voltage
I
OL
= MAX. Vin = V
IL
or V
IH
--
--
0.5
V
V
OH
Output High Voltage
I
OH
= MAX. Vin = V
IL
or V
IH
2.4
--
--
V
I
OL
Low Level Output Current
--
--
16
mA
I
OH
High Level Output Current
--
--
3.2
mA
I
OS
2
Output Short Circuit Current
V
CC
= 5V
V
OUT
= 0.5V T
A
= 25
C
30
--
130
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and T
A
= 25
C
Absolute Maximum Ratings
(1)
Supply voltage V
CC
....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to V
CC
+1.0V
Off-state output voltage applied .......... -2.5 to V
CC
+1.0V
Storage Temperature ................................. -65 to 150
C
Ambient Temperature with
Power Applied ......................................... -55 to 125
C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (T
A
) ............................. 0 to +75
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.75 to +5.25V
Specifications
GAL18V10B
7
t
pd
A
Input or I/O to Comb. Output
--
7.5
--
10
--
15
--
20
ns
t
co
A
Clock to Output Delay
--
5.5
--
7
--
10
--
12
ns
t
cf
2
--
Clock to Feedback Delay
--
3.5
--
3.5
--
7
--
10
ns
t
su
--
Setup Time, Input or Fdbk before Clk
5.5
--
6
--
8
--
12
--
ns
t
h
--
Hold Time, Input or Fdbk after Clk
0
--
0
--
0
--
0
--
ns
A
Maximum Clock Frequency with
90.9
--
76.9
--
55.5
--
41.6
--
MHz
External Feedback, 1/(tsu + tco)
f
max
3
A
Maximum Clock Frequency with
111
--
105
--
66.7
--
45.4
--
MHz
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
111
--
105
--
66.7
--
62.5
--
MHz
No Feedback
t
wh
--
Clock Pulse Duration, High
4
--
4
--
6
--
8
--
ns
t
wl
--
Clock Pulse Duration, Low
4
--
4
--
6
--
8
--
ns
t
en
B
Input or I/O to Output Enabled
--
8
--
10
--
15
--
20
ns
t
dis
C
Input or I/O to Output Disabled
--
8
--
9
--
15
--
20
ns
t
ar
A
Input or I/O to Asynch. Reset of Reg.
--
13
--
13
--
20
--
20
ns
t
arw
--
Asynch. Reset Pulse Duration
8
--
8
--
10
--
15
--
ns
t
arr
--
Asynch. Reset to Clk
Recovery Time
8
--
8
--
10
--
15
--
ns
t
spr
--
Synch. Preset to Clk
Recovery Time
10
--
10
--
10
--
12
--
ns
UNITS
PARAM.
TEST
COND.
1
DESCRIPTION
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 5.0V, V
I
= 2.0V
C
I/O
I/O Capacitance
8
pF
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested.
COM
COM
COM
COM
-7
MIN. MAX.
-10
MIN. MAX.
-15
MIN. MAX.
-20
MIN. MAX.
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (T
A
= 25
C, f = 1.0 MHz)
Specifications
GAL18V10
8
COMMERCIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V
L -15/-20
--
75
115
mA
Supply Current
f
toggle
= 15MHz Outputs Open
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (T
A
) ............................. 0 to +75
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.75 to +5.25V
Absolute Maximum Ratings
(1)
Supply voltage V
CC
....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to V
CC
+1.0V
Off-state output voltage applied .......... -2.5 to V
CC
+1.0V
Storage Temperature ................................. -65 to 150
C
Ambient Temperature with
Power Applied ......................................... -55 to 125
C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
3
MAX.
UNITS
V
IL
Input Low Voltage
Vss 0.5
--
0.8
V
V
IH
Input High Voltage
2.0
--
Vcc+1
V
I
IL
1
Input or I/O Low Leakage Current
0V
V
IN
V
IL
(MAX.)
--
--
100
A
I
IH
Input or I/O High Leakage Current
3.5V
V
IN
V
CC
--
--
10
A
V
OL
Output Low Voltage
I
OL
= MAX. Vin = V
IL
or V
IH
--
--
0.5
V
V
OH
Output High Voltage
I
OH
= MAX. Vin = V
IL
or V
IH
2.4
--
--
V
I
OL
Low Level Output Current
--
--
16
mA
I
OH
High Level Output Current
--
--
3.2
mA
I
OS
2
Output Short Circuit Current
V
CC
= 5V
V
OUT
= 0.5V T
A
= 25
C
50
--
135
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and T
A
= 25
C
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
Specifications
GAL18V10
9
t
pd
A
Input or I/O to Combinatorial Output
--
15
--
20
ns
t
co
A
Clock to Output Delay
--
10
--
12
ns
t
cf
2
--
Clock to Feedback Delay
--
7
--
10
ns
t
su
--
Setup Time, Input or Feedback before Clock
10
--
12
--
ns
t
h
--
Hold Time, Input or Feedback after Clock
0
--
0
--
ns
A
Maximum Clock Frequency with
50
--
41.6
--
MHz
External Feedback, 1/(tsu +tco)
f
max
3
A
Maximum Clock Frequency with
58.8
--
45.4
--
MHz
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
62.5
--
62.5
--
MHz
No Feedback
t
wh
--
Clock Pulse Duration, High
8
--
8
--
ns
t
wl
--
Clock Pulse Duration, Low
8
--
8
--
ns
t
en
B
Input or I/O to Output Enabled
--
15
--
20
ns
t
dis
C
Input or I/O to Output Disabled
--
15
--
20
ns
t
ar
A
Input or I/O to Asynchronous Reset of Register
--
20
--
20
ns
t
arw
--
Asynchronous Reset Pulse Duration
10
--
15
--
ns
t
arr
--
Asynchronous Reset to Clock
Recovery Time
15
--
15
--
ns
t
spr
--
Synchronous Preset to Clock
Recovery Time
10
--
12
--
ns
PARAMETER
UNITS
-20
MIN. MAX.
-15
MIN. MAX.
TEST
COND.
1
DESCRIPTION
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 5.0V, V
I
= 2.0V
C
I/O
I/O Capacitance
10
pF
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested.
COM
COM
Capacitance (T
A
= 25
C, f = 1.0 MHz)
AC Switching Characteristics
Over Recommended Operating Conditions
Specifications
GAL18V10
10
Input or I/O to Output Enable/Disable
Registered Output
Combinatorial Output
VALID INPUT
INPUT or
I/O F EEDB ACK
t
p d
CO MB INA T O RI AL
O U T P U T
INPU T or
I/O F EED B ACK
R EG I ST E R E D
O U T P U T
C L K
VALID IN PU T
t
su
t
co
t
h
(external fdbk)
1/
f
ma x
t
en
t
dis
INPU T or
I/O F EED B ACK
O U T P U T
CLK
(w/o fdbk)
t
wh
1/
f
ma x
t
wl
Clock Width
R EG I ST E R E D
O U T P U T
CLK
INPU T or
I/O F EED B ACK
DRIVI NG SP
t
su
t
h
t
co
t
spr
R EG I ST E R E D
O U T P U T
C L K
t
arw
t
arr
INPU T or
I/O F EED B ACK
DRIVI NG AR
t
ar
f
max with Feedback
C L K
R EG I ST E R E D
F E E D B A C K
t
cf
t
s u
1/
f
max (internal fdbk)
Synchronous Preset
Asynchronous Reset
Switching Waveforms
Specifications
GAL18V10
11
f
max with Internal Feedback 1/(
t
su+
t
cf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
f
max with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
f
max with External Feedback 1/(
t
su+
t
co)
REGISTER
LOGIC
ARRAY
CLK
t
su +
t
h
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
Output Load Conditions (see figure)
Test Condition
R
1
R
2
C
L
A
300
390
50pF
B
Active High
390
50pF
Active Low
300
390
50pF
C
Active High
390
5pF
Active Low
300
390
5pF
Input Pulse Levels
GND to 3.0V
Input Rise and
-7/-10
2ns 10% 90%
Fall Times
-15/-20
3ns 10% 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
f
max Descriptions
Switching Test Conditions
Specifications
GAL18V10
12
Electronic Signature
An electronic signature is provided in every GAL18V10 device. It
contains 64 bits of reprogrammable memory that can contain user-
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
Security Cell
A security cell is provided in every GAL18V10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.
Latch-Up Protection
GAL18V10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.
Device Programming
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
part of the programming cycle.
Typical Input Current
1 . 0
2 . 0
3 . 0
4 . 0
5 . 0
- 6 0
0
- 2 0
- 4 0
0
In p u t V o lt ag e ( V o lt s)
I
nput
C
u
r
r
e
nt
(
u
A
)
Output Register Preload
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
The GAL18V10 device includes circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing test vectors
perform output register preload automatically.
Input Buffers
GAL18V10 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
The input and I/O pins also have built-in active pull-ups. As a result,
floating inputs will float to a TTL high (logic 1). However, Lattice
Semiconductor recommends that all unused inputs and tri-stated
I/O pins be connected to an adjacent active input, Vcc, or ground.
Doing so will tend to improve noise immunity and reduce Icc for the
device.
Specifications
GAL18V10
13
Typical Input
Typical Output
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
(Vref Typical = 3.2V)
(Vref Typical = 3.2V)
Circuitry within the GAL18V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1
s MAX). As a result,
the state on the registered output pins (if they are enabled) will
be either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
conditions must be met to provide a valid power-up reset of the
device. First, the V
CC
rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Device Pin
Reset to Logic "0"
V c c
C L K
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Power-Up Reset
Input/Output Equivalent Schematics
Specifications
GAL18V10
14
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
9
10
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
9
10
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-4
-2
0
2
4
6
8
10
0
50
100
150
200
250
300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-4
-2
0
2
4
6
8
10
0
50
100
150
200
250
300
RISE
FALL
GAL18V10B: Typical AC and DC Characteristic Diagrams
Specifications
GAL18V10
15
Vol vs Iol
Iol (mA)
Vol (V)
0
0.25
0.5
0.75
1
0
10
20
30
40
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0
10
20
30
40
50
60
Voh vs Ioh
Ioh(mA)
Voh (V)
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
0
1
2
3
4
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.8
0.9
1
1.1
1.2
-55
-25
0
25
50
75
100
125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.8
0.9
1
1.1
1.2
1.3
1.4
0
25
50
75
100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
1
2
3
4
5
6
7
8
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
-120
-100
-80
-60
-40
-20
0
-2.00
-1.50
-1.00
-0.50
0.00
GAL18V10B: Typical AC and DC Characteristic Diagrams
Specifications
GAL18V10
16
Normalized Icc vs. Temperature
Ambient Temperature (C)
Normalized Icc
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Icc vs. Temperature
Isb vs. Temperature
4
I
OH
vs. V
OH
V
OH
(V)
I
OH
(mA)
0
-50
-100
-150
0
1
2
3
0
50
100
150
200
250
0
1
2
3
4
I
OL
vs. V
OL
V
OL
(V)
I
OL
(mA)
Delta Tpd vs. Output Loading
Output Loading Capacitance (pf)
Delta Tpd (ns)
-2
0
2
4
6
8
10
0
100
200
300
400
Normalized Icc vs. Vcc
Supply Voltage (V)
Normalized Icc
0.7
0.8
0.9
1
1.1
1.2
1.3
4.5
4.75
5
5.25
5.5
Delta Tpd vs. # of Outputs Switching
# of Outputs
Delta Tpd (ns)
-3
-2
-1
0
0
Max. - 8
Max. - 4
Max.
Normalized Tco vs. Temperature
Ambient Temperature (C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Tsu vs. Temperature
Ambient Temperature (C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Tpd vs. Temperature
Ambient Temperature (C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-50
-25
0
25
50
75
100
125
Normalized Tsu vs. Vcc
Supply Voltage (V)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
4.5
4.75
5
5.25
5.5
PT L -> H
PT H -> L
Normalized Tco vs. Vcc
Supply Voltage (V)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
4.5
4.75
5
5.25
5.5
0.7
0.8
0.9
1
1.1
1.2
1.3
4.5
4.75
5
5.25
5.5
PT L -> H
PT H -> L
Normalized Tpd vs. Vcc
Supply Voltage (V)
Normalized Tpd
GAL18V10B: Typical AC and DC Characteristic Diagrams
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