GAL20LV8

Low Voltage E

CMOS PLD

Generic Array LogicTM

20lv8_05

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

March 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Features

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

-- 3.5 ns Maximum Propagation Delay
-- Fmax = 250 MHz
-- 2.5 ns Maximum from Clock Input to Data Output
-- UltraMOS

Advanced CMOS Technology

-- TTL-Compatible Balanced 8mA Output Drive

· 3.3V LOW VOLTAGE 20V8 ARCHITECTURE

-- JEDEC-Compatible 3.3V Interface Standard
-- 5V Compatible Inputs

· ACTIVE PULL-UPS ON ALL PINS

· E

CELL TECHNOLOGY

-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention

· EIGHT OUTPUT LOGIC MACROCELLS

-- Maximum Flexibility for Complex Logic Designs
-- Programmable Output Polarity

· PRELOAD AND POWER-ON RESET OF ALL REGISTERS

-- 100% Functional Testability

· APPLICATIONS INCLUDE:

-- Glue Logic for 3.3V Systems
-- DMA Control
-- State Machine Control
-- High Speed Graphics Processing
-- Standard Logic Speed Upgrade

· ELECTRONIC SIGNATURE FOR IDENTIFICATION

I/CLK

GND

I/OE

I/O/Q

Vcc

I/O/Q

GAL20LV8D

Top View

CLK

I/O/Q

I/OE

I/CLK

OLMC

IMUX

PROGRAMMABLE

AND-ARRAY

(64 X 40)

OLMC

PLCC

New 5V

Tolerant

Inputs on

20L

V8D

Description

The GAL20LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL20LV8D is manufactured using Lattice
Semiconductor's advanced 3.3V E

CMOS process, which com-

bines CMOS with Electrically Erasable (E

) floating gate technology.

High speed erase times (<100ms) allow the devices to be repro-
grammed quickly and efficiently.

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL20LV8D are the PAL

architectures listed

in the table of the macrocell description section. GAL20LV8D
devices are capable of emulating any of these PAL architectures
with full function/fuse map compatibility.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Functional Block Diagram

Pin Configuration

Specifications

GAL20LV8

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in-
put/output configuration. These two global and 16 individual archi-
tecture bits define all possible configurations in a GAL20LV8D . The
information given on these architecture bits is only to give a bet-
ter understanding of the device. Compiler software will transpar-
ently set these architecture bits from the pin definitions, so the user
should not need to directly manipulate these architecture bits.

The following is a list of the PAL architectures that the GAL20LV8D
can emulate. It also shows the OLMC mode under which the
devices emulate the PAL architecture.

Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft-
ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 2 and pin 16 are permanently configured

as clock and output enable, respectively. These pins cannot be con-
figured as dedicated inputs in the registered mode.

In complex mode pin 2 and pin 16 become dedicated inputs and
use the feedback paths of pin 26 and pin 18 respectively. Because
of this feedback path usage, pin 26 and pin 18 do not have the
feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
21 and 23) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

Registered

Complex

Simple

Auto Mode Select

ABEL

P20V8R

P20V8C

P20V8AS

P20V8

CUPL

G20V8MS

G20V8MA

G20V8AS

G20V8

LOG/iC

GAL20V8_R

GAL20V8_C7

GAL20V8_C8

GAL20V8

OrCAD-PLD

"Registered"

"Complex"

"Simple"

GAL20V8A

PLDesigner

P20V8R

P20V8C

P20V8A

TANGO-PLD

G20V8R

G20V8C

G20V8AS

G20V8

1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.

PAL Architectures

GAL20LV8D

Emulated by GAL20LV8D

Global OLMC Mode

20R8

Registered

20R6

Registered

20R4

Registered

20RP8

Registered

20RP6

Registered

20RP4

Registered

20L8

Complex

20H8

Complex

20P8

Complex

14L8

Simple

16L6

Simple

18L4

Simple

20L2

Simple

14H8

Simple

16H6

Simple

18H4

Simple

20H2

Simple

14P8

Simple

16P6

Simple

18P4

Simple

20P2

Simple

Output Logic Macrocell (OLMC)

Compiler Support for OLMC

Specifications

GAL20LV8

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity, I/O and register placement.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.

Dedicated input or output functions can be implemented as sub-
sets of the I/O function.

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 2 controls common CLK for the registered outputs.
- Pin 16 controls common

for the registered outputs.

- Pin 2 & Pin 16 are permanently configured as CLK &

for registered output configuration.

Combinatorial Configuration for Registered Mode

- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 2 & Pin 16 are permanently configured as CLK &

for registered output configuration.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

CLK

XOR

Registered Mode

Specifications

GAL20LV8

In the Complex mode, macrocells are configured as output only or
I/O functions.

Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 18 & 26) do not have input capability. De-

signs requiring eight I/Os can be implemented in the Registered
mode.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 2 and
16 are always available as data inputs into the AND array.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 19 through Pin 25 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 18 and Pin 26 are configured to this function.

XOR

Complex Mode

Specifications

GAL20LV8

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- All OLMC except pins 21 & 23 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- Pins 21 & 23 are permanently configured to this
function.

Dedicated Input Configuration for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 21 & 23 can be configured to
this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

In the Simple mode, pins are configured as dedicated inputs or as
dedicated, always active, combinatorial outputs.

Architecture configurations available in this mode are similar to the
common 14L8 and 16P6 devices with many permutations of ge-
neric output polarity or input choices.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro-
grammable polarity.

Pins 2 and 16 are always available as data inputs into the AND
array. The "center" two macrocells (pins 21 & 23) cannot be used
in the input configuration.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Vcc

XOR

Vcc

XOR

Simple Mode

Specifications

GAL20LV8

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 3.3V and T

= 25

COMMERCIAL

Operating Power

= 0V V

= 3.0V Unused Inputs at V

Supply Current

toggle

= 1MHz Outputs Open

Input Low Voltage

Vss 0.3

0.8

Input High Voltage

2.0

5.25

I/O High Voltage

2.0

Vcc+0.5

Input or I/O Low Leakage Current

(MAX.)

100

Input or I/O High Leakage Current

(Vcc-0.2)V

Input High Leakage Current

Vcc

5.25V

I/O High Leakage Current

Vcc

4.6V

Output Low Voltage

= MAX. Vin = V

or V

0.4

= 500

A Vin = V

or V

0.2

Output High Voltage

= MAX. Vin = V

or V

2.4

= -100

A Vin = V

or V

Vcc-0.2V

Low Level Output Current

High Level Output Current

Output Short Circuit Current

= 3.3V

OUT

= 0.5V T

= 25

Recommended Operating Conditions

Commercial Devices:
Ambient Temperature (T

) ............................... 0 to 75

Supply voltage (V

)

with Respect to Ground ......................... +3.0 to +3.6V

Absolute Maximum Ratings

(1)

Supply voltage V

................................... 0.5 to +4.6V

Input voltage applied ................................ 0.5 to +5.6V
I/O voltage applied ................................... 0.5 to +4.6V
Off-state output voltage applied ............... 0.5 to +4.6V
Storage Temperature ................................ 65 to 150

Ambient Temperature with

Power Applied ........................................ 55 to 125

1.Stresses above those listed under the "Absolute Maximum

Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.

MAX.

UNITS

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

Specifications

GAL20LV8

COM

Input or I/O to Combinational Output

3.5

7.5

Clock to Output Delay

2.5

Clock to Feedback Delay

Setup Time, Input or Feedback before Clock

Hold Time, Input or Feedback after Clock

Maximum Clock Frequency with

180

142.8 --

100

MHz

External Feedback, 1/(tsu + tco)

max

Maximum Clock Frequency with

200

166

125

MHz

Internal Feedback, 1/(tsu + tcf)

Maximum Clock Frequency with

250

166

125

MHz

No Feedback

Clock Pulse Duration, High

Clock Pulse Duration, Low

Input or I/O to Output Enabled

4.5

7.5

OE to Output Enabled

3.5

6.5

dis

Input or I/O to Output Disabled

4.5

7.5

OE to Output Disabled

3.5

6.5

-5

MIN. MAX.

-7

MIN. MAX.

UNITS

PARAMETER

TEST

COND

DESCRIPTION

1) Refer to Switching Test Conditions section.
2) Minimum values for

pd and

co are not 100% tested but established by characterization.

3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
4) Refer to fmax Descriptions section. Characterized but not 100% tested.

SYMBOL

PARAMETER

TYPICAL

UNITS

TEST CONDITIONS

Input Capacitance

= 3.3V, V

= 0V

I/O

I/O Capacitance

= 3.3V, V

I/O

= 0V

-3

MIN. MAX.

COM

AC Switching Characteristics

Over Recommended Operating Conditions

Capacitance (T

= 25

C, f = 1.0 MHz)

Specifications

GAL20LV8

max with Internal Feedback 1/(

su+

cf)

Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

max with External Feedback 1/(

su+

co)

Note: fmax with external feedback is calculated from measured
tsu and tco.

R E G I S T E R

L O G I C
A R R A Y

c o

s u

C L K

CLK

LOGIC
ARRAY

max with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.

TEST POINT

= 50

, C

= 35pF*

FROM OUTPUT (O/Q)
UNDER TEST

+1.45V

includes test fixture and probe capacitance.

LOGIC
ARRAY

CLK

su +

Output Load Conditions (see figure)

Test Condition

35pF

High Z to Active High at 1.9V

35pF

High Z to Active Low at 1.0V

35pF

Active High to High Z at 1.9V

35pF

Active Low to High Z at 1.0V

35pF

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

1.5ns 10% 90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

See Figure

max Descriptions

Switching Test Conditions

Specifications

GAL20LV8

Input Voltage (V)

-80

-70

-60

-50

-40

-30

-20

-10

0.5

1.5

2.5

3.5

Input Current (

Electronic Signature

An electronic signature is provided in every GAL20LV8D device.
It contains 64 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.

NOTE: The electronic signature is included in checksum calcula-
tions. Changing the electronic signature will alter the checksum.

Security Cell

A security cell is provided in the GAL20LV8D devices to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.

Latch-Up Protection

GAL20LV8D devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential of latch-up caused by negative input undershoots.

Device Programming

GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.

GAL20LV8D devices include circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing text vectors
perform output register preload automatically.

Input Buffers

GAL20LV8D devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.

The GAL20LV8D input and I/O pins have built-in active pull-ups.
As a result, unused inputs and I/Os will float to a TTL "high"
(logical "1"). Lattice Semiconductor recommends that all unused
inputs and tri-stated I/O pins be connected to another active input,
V

, or Ground. Doing this will tend to improve noise immunity

and reduce I

for the device.

Typical Input Pull-up Characteristic

Specifications

GAL20LV8

Typ. Vref = Vcc

Typical Output

Typ. Vref = Vcc

Typical Input

Vcc

Vref

Tri-State
Control

Active Pull-up
Circuit

Feedback
(To Input Buffer)

Feedback

Data
Output

Circuitry within the GAL20LV8D provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q outputs
set low after a specified time (

pr, 1

s MAX). As a result, the state

on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. Because of the asynchro-
nous nature of system power-up, some conditions must be met to

provide a valid power-up reset of the device. First, the V

rise must

be monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will re-
set within a maximum of

pr time. As in normal system operation,

avoid clocking the device until all input and feedback path setup
times have been met. The clock must also meet the minimum pulse
width requirements.

Vcc

Vref

Active Pull-up
Circuit

ESD
Protection
Circuit

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Vcc (min.)

Internal Register
Reset to Logic "0"

Device Pin
Reset to Logic "1"

Power-Up Reset

Input/Output Equivalent Schematics

Specifications

GAL20LV8

Normalized Tpd vs Vcc

Supply Voltage (V)

Normalized Tpd

0.8

0.9

1.1

1.2

3.00

3.15

3.30

3.45

3.60

PT H->L

PT L->H

Normalized Tco vs Vcc

Supply Voltage (V)

Normalized Tco

0.8

0.9

1.1

1.2

3.00

3.15

3.30

3.45

3.60

RISE

FALL

Normalized Tsu vs Vcc

Supply Voltage (V)

Normalized Ts

0.8

0.9

1.1

1.2

3.00

3.15

3.30

3.45

3.60

PT H->L

PT L->H

Normalized Tpd vs Temp

Temperature (deg. C)

Normalized Tpd

0.8

0.9

1.1

1.2

-55

-25

100

125

PT H->L

PT L->H

Normalized Tco vs Temp

Temperature (deg. C)

Normalized Tco

0.8

0.9

1.1

1.2

-55

-25

100

125

RISE

FALL

Normalized Tsu vs Temp

Temperature (deg. C)

Normalized Ts

0.8

0.9

1.1

1.2

-55

-25

100

125

PT H->L

PT L->H

Delta Tpd vs # of Outputs

Switching

Number of Outputs Switching

Delta Tpd

(ns)

-0.5

-0.4

-0.3

-0.2

-0.1

RISE

FALL

Delta Tco vs # of Outputs

Switching

Number of Outputs Switching

Delta Tco

(ns)

-0.5

-0.4

-0.3

-0.2

-0.1

RISE

FALL

Delta Tpd vs Output

Loading

Output Loading (pF)

Delta Tpd

(ns)

-6

-2

100

150

200

250

300

RISE

FALL

Delta Tco vs Output Loading

Output Loading (pF)

Delta Tco

(ns)

-4

100

150

200

250

300

RISE

FALL

Typical AC and DC Characteristic Diagrams

Specifications

GAL20LV8

Vol vs Iol

Iol (mA)

Vol (V)

0.25

0.5

0.75

0.00

5.00

10.00 15.00

20.00 25.00 30.00

Voh vs Ioh

Ioh(mA)

Voh (V)

0.5

1.5

2.5

0.00

5.00

10.00

15.00

20.00

25.00

30.00

Voh vs Ioh

Ioh(mA)

Voh (V)

2.8

2.85

2.9

2.95

0.00

1.00

2.00

3.00

4.00

Normalized Icc vs Vcc

Supply Voltage (V)

Normalized Icc

0.80

0.90

1.00

1.10

1.20

3.00

3.15

3.30

3.45

3.60

Normalized Icc vs Temp

Temperature (deg. C)

Normalized Icc

0.8

0.9

1.1

1.2

-55

-25

100

125

Normalized Icc vs Freq.

Frequency (MHz)

Normalized Icc

0.80

0.90

1.00

1.10

1.20

1.30

1.40

100

Delta Icc vs Vin (1 input)

Vin (V)

Delta Icc (mA)

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Input Clamp (Vik)

Vik (V)

Iik (mA)

-2.00

-1.50

-1.00

-0.50

0.00

Typical AC and DC Characteristic Diagrams

Document Outline

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Document Outline

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