GAL20LV8ZD

Low Voltage, Zero Power E

CMOS PLD

Generic Array LogicTM

Features

· 3.3V LOW VOLTAGE, ZERO POWER OPERATION

-- JEDEC Compatible 3.3V Interface Standard
-- Interfaces with Standard 5V TTL Devices
-- 50

A Typical Standby Current (100

A Max.)

-- 45mA Typical Active Current (55mA Max.)
-- Dedicated Power-down Pin

· HIGH PERFORMANCE E

CMOS TECHNOLOGY

-- TTL Compatible Balanced 8 mA Output Drive
-- 15 ns Maximum Propagation Delay
-- Fmax = 62.5 MHz
-- 10 ns Maximum from Clock Input to Data Output
-- UltraMOS

Advanced CMOS Technology

· E

CELL TECHNOLOGY

-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention

· EIGHT OUTPUT LOGIC MACROCELLS

-- Maximum Flexibility for Complex Logic Designs
-- Programmable Output Polarity

· PRELOAD AND POWER-ON RESET OF ALL REGISTERS

-- 100% Functional Testability

· APPLICATIONS INCLUDE:

-- Glue Logic for 3.3V Systems
-- Ideal for Mixed 3.3V and 5V Systems

· ELECTRONIC SIGNATURE FOR IDENTIFICATION

CLK

I/O/Q

DPP

I/OE

I/CLK

OLMC

IMUX

PROGRAMMABLE

AND-ARRAY

(64 X 40)

OLMC

I/CLK

DPP

GND

I/OE

I/O/Q

Vcc

I/O/Q

PLCC

GAL20LV8ZD

Top View

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

December 1997

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

20lv8zd_03

Description

The GAL20LV8ZD, at 100

A standby current and 15ns propagation

delay provides the highest speed low-voltage PLD available in the
market. The GAL20LV8ZD is manufactured using Lattice
Semiconductor's advanced 3.3V E

CMOS process, which com-

bines CMOS with Electrically Erasable (E

) floating gate technology.

The GAL20LV8ZD utilizes a dedicated power-down pin (DPP) to
put the device into standby mode. It has 19 inputs available to the
AND array and is capable of interfacing with both 3.3V and stan-
dard 5V devices.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.

Functional Block Diagram

Pin Configuration

Specifications

GAL20LV8ZD

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of

each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in-
put/output configuration. These two global and 16 individual archi-
tecture bits define all possible configurations in a GAL20LV8ZD.
The information given on these architecture bits is only to give a
better understanding of the device. Compiler software will trans-
parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.

Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft-
ware manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.

In registered mode pin 2 and pin 16 are permanently configured
as clock and output enable, respectively. These pins cannot be con-
figured as dedicated inputs in the registered mode.

In complex mode pin 2 and pin 16 become dedicated inputs and
use the feedback paths of pin 26 and pin 18 respectively. Because
of this feedback path usage, pin 26 and pin 18 do not have the
feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
21 and 23) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

When using the standard GAL20V8 JEDEC fuse pattern generated
by the logic compilers for the GAL20LV8ZD, special attention must
be given to pin 5 (DPP) to make sure that it is not used as one of
the functional inputs.

Output Logic Macrocell (OLMC)

Compiler Support for OLMC

Specifications

GAL20LV8ZD

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity, I/O and register placement.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub-
sets of the I/O function.

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

Pin 5 is used as dedicated power-down pin on GAL20LV8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Combinatorial Configuration for Registered Mode

- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 2 & Pin 16 are permanently configured as
CLK & OE for registered output configuration.

Registered Configuration for Registered Mode

- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 2 controls common CLK for the registered

outputs.

- Pin 16 controls common OE for the registered

outputs.

- Pin 2 & Pin 16 are permanently configured as

CLK & OE for registered output configuration.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

CLK

XOR

Registered Mode

Specifications

GAL20LV8ZD

PLCC Package Pinout

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631
Byte7 Byte6 .... .... Byte1 Byte0

MSB LSB

SYN-2704

AC0-2705

0000

PTD

2640

0280

0320

0600

0640

0920

0960

1240

1280

1560

1600

1880

1920

2200

2240

2520

OLMC

XOR-2567
AC1-2639

OLMC

XOR-2566
AC1-2638

OLMC

XOR-2565
AC1-2637

OLMC

XOR-2564
AC1-2636

XOR-2563
AC1-2635

OLMC

XOR-2562
AC1-2634

OLMC

XOR-2561
AC1-2633

XOR-2560
AC1-2632

Power

Management

Control

2703

Registered Mode Logic Diagram

Specifications

GAL20LV8ZD

In the Complex mode, macrocells are configured as output only or
I/O functions.

Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 18 & 26) do not have input capability. De-
signs requiring eight I/Os can be implemented in the Registered
mode.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 2 and
16 are always available as data inputs into the AND array.

Pin 5 is used as dedicated power-down pin on GAL20LV8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 19 through Pin 25 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 18 and Pin 26 are configured to this function.

XOR

Complex Mode

Specifications

GAL20LV8ZD

PLCC Package Pinout

MSB LSB

SYN-2704

AC0-2705

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631
Byte7 Byte6 .... .... Byte1 Byte0

0000

PTD

2640

0280

0320

0600

0640

0920

0960

1240

1280

1560

1600

1880

1920

2200

2240

2520

OLMC

2703

XOR-2567
AC1-2639

XOR-2566
AC1-2638

XOR-2565
AC1-2637

XOR-2564
AC1-2636

XOR-2563
AC1-2635

XOR-2562
AC1-2634

XOR-2561
AC1-2633

XOR-2560
AC1-2632

Power

Management

Control

Complex Mode Logic Diagram

Specifications

GAL20LV8ZD

In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

Architecture configurations available in this mode are similar to the
common 14L8 and 16P6 devices with many permutations of ge-
neric output polarity or input choices.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro-
grammable polarity.

Pins 2 and 16 are always available as data inputs into the AND
array. The center two macrocells (pins 21 & 23) cannot be used
in the input configuration.

Pin 5 is used as dedicated power-down pin on GAL20LV8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- All OLMC except pins 21 & 23 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- Pins 21 & 23 are permanently configured to
this function.

Dedicated Input Configuration for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 21 & 23 can be configured to
this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

Vcc

XOR

Vcc

XOR

Simple Mode

Specifications

GAL20LV8ZD

MSB LSB

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631
Byte7 Byte6 .... .... Byte1 Byte0

SYN-2704

AC0-2705

PLCC Package Pinouts

0000

PTD

2640

0280

0320

0600

0640

0920

0960

1240

1280

1560

1600

1880

1920

2200

2240

2520

OLMC

XOR-2560
AC1-2632

OLMC

XOR-2561
AC1-2633

XOR-2562
AC1-2634

XOR-2563
AC1-2635

XOR-2564
AC1-2636

XOR-2565
AC1-2637

XOR-2566
AC1-2638

XOR-2567
AC1-2639

2703

Power

Management

Control

Simple Mode Logic Diagram

Specifications

GAL20LV8ZD

Recommended Operating Conditions

Commercial Devices:
Ambient Temperature (T

) ............................. 0 to +75

Supply voltage (V

)

with Respect to Ground ......................... +3.0 to +3.6V

Input Low Voltage

Vss 0.5

0.8

Input High Voltage

2.0

5.25

Input or I/O Low Leakage Current

(MAX.)

Input or I/O High Leakage Current

-0.2)V

5.25V

Output Low Voltage

= MAX. Vin = V

or V

0.5

= 0.5 mA Vin = V

or V

0.2

Output High Voltage

= MAX. Vin = V

or V

2.4

= -0.5 mA Vin = V

or V

Vcc-0.45

= -100

A Vin = V

or V

Vcc-0.2

Low Level Output Current

High Level Output Current

-8

Output Short Circuit Current

= 3.3V V

OUT

= GND T

= 25

-30

-130

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.

MAX.

UNITS

COMMERCIAL

Stand-by Power

= GND V

= Vcc Outputs Open

ZD -15/-25

100

Supply Current

Operating Power

= 0.5V V

= 3.0V

ZD -15/-25

Supply Current

toggle

= 15 MHz Outputs Open

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2) Typical values are at Vcc = 3.3V and T

= 25

Absolute Maximum Ratings

(1)

Supply voltage V

....................................

0.5 to +5.6V

Input voltage applied ................................. -0.5 to +5.6V
Off-state output voltage applied ................ -0.5 to +5.6V
Storage Temperature ................................. -65 to 150

Ambient Temperature with

Power Applied ......................................... -55 to 125

1. Stresses above those listed under the "Absolute Maximum

Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

Specifications

GAL20LV8ZD

Input or I/O to Combinatorial Output

Clock to Output Delay

Clock to Feedback Delay

Setup Time, Input or Fdbk before Clk

Hold Time, Input or Fdbk after Clk

Maximum Clock Frequency with

45.5

33.3

MHz

External Feedback, 1/(tsu + tco)

max

Maximum Clock Frequency with

MHz

Internal Feedback, 1/(tsu + tcf)

Maximum Clock Frequency with

62.5

41.6

MHz

No Feedback

Clock Pulse Duration, High

Clock Pulse Duration, Low

Input or I/O to Output Enabled

to Output Enabled

dis

Input or I/O to Output Disabled

to Output Disabled

-25

MIN. MAX.

-15

MIN. MAX.

UNITS

PARAM

TEST

COND.

DESCRIPTION

COM

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.

SYMBOL

PARAMETER

TYPICAL

UNITS

TEST CONDITIONS

Input Capacitance

= 3.3V, V

= 0V

I/O

I/O Capacitance

= 3.3V, V

I/O

= 0V

AC Switching Characteristics

Over Recommended Operating Conditions

Capacitance (T

= 25

C, f = 1.0 MHz)

Specifications

GAL20LV8ZD

whd

DPP Pulse Duration High

wld

DPP Pulse Duration Low

ivdh

Valid Input before DPP High

gvdh

Valid OE before DPP High

cvdh

Valid Clock before DPP High

dhix

Input Don't Care after DPP High

dhgx

OE Don't Care after DPP High

dhcx

Clock Don't Care after DPP High

ixdl

Input Don't Care before DPP Low

gxdl

OE Don't Care before DPP Low

cxdl

Clock Don't Care before DPP Low

dliv

DPP Low to Valid Input

dlgv

DPP Low to Valid OE

dlcv

DPP Low to Valid Clock

dlov

DPP Low to Valid Output

PARAMETER

UNITS

-25

MIN. MAX.

TEST

COND

DESCRIPTION

-15

MIN. MAX.

ACTIVE TO STANDBY

STANDBY TO ACTIVE

COM

dhcx

DPP

INPUT or
I/O FEEDBACK

CLK

OUTPUT

cvdh

gvdh

ivdh

dhgx

dhix

p d ,

e n ,

d i s

c o

dliv

dlgv

d lcv

dlov

cxdl

gxdl

ixdl

1) Refer to Switching Test Conditions section.

Dedicated Power-Down Pin Specications

Over Recommended Operating Conditions

Dedicated Power-Down Pin Timing Waveforms

Specifications

GAL20LV8ZD

max with Internal Feedback 1/(

su+

cf)

max with External Feedback 1/(

su+

co)

CLK

LOGIC
ARRAY

R E G I S T E R

L O G I C
A R R A Y

c o

s u

C L K

LOGIC
ARRAY

CLK

su +

max with No Feedback

Note: fmax with no feedback may be less than 1/(twh
+ twl). This is to allow for a clock duty cycle of other
than 50%.

Note: fmax with external feedback is calculated from
measured tsu and tco.

Note: tcf is a calculated value, derived by subtracting
tsu from the period of fmax w/internal feedback (tcf
= 1/fmax - tsu). The value of tcf is used primarily
when calculating the delay from clocking a register
to a combinatorial output (through registered feed-
back), as shown above. For example, the timing
from clock to a combinatorial output is equal to tcf
+ tpd.

TEST POINT

C *

FROM OUTPUT (O/Q)
UNDER TEST

+3.3V

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

2ns 10% 90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

See Figure

3-state levels are measured 0.5V from steady-state active
level. 3-state to active transitions are measured at (Voh - 0.5)
V and (Vol + 0.5) V.

Output Load Conditions (see figure)

Test Condition

270

220

35pF

Active High

270

220

35pF

Active Low

270

220

35pF

Active High

270

220

5pF

Active Low

270

220

5pF

max Descriptions

Switching Test Conditions

Specifications

GAL20LV8ZD

Electronic Signature

An electronic signature word is provided in every GAL20LV8ZD
device. It contains 64 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is al-
ways available to the user independent of the state of the security
cell.

NOTE: The electronic signature is included in checksum calcula-
tions. Changing the electronic signature will alter checksum.

Security Cell

A security cell is provided in the GAL20LV8ZD devices to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The electronic signature data is always avail-
able to the user, regardless of the state of this security cell.

Device Programming

GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.

The GAL20LV8ZD devices includes circuitry that allows each reg-
istered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If nec-
essary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.

Input Buffers

GAL20LV8ZD devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.

Dedicated Power-Down Pin

The GAL20LV8ZD uses pin 5 as the dedicated power-down sig-
nal to put the device in to the power-down state. DPP is an active
high signal where a logic high driven on this signal puts the device
into power-down state. Input pin 5 cannot be used as a logic func-
tion input on this device.

Specifications

GAL20LV8ZD

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Vcc (min.)

Internal Register
Reset to Logic "0"

Device Pin
Reset to Logic "1"

Circuitry within the GAL20LV8ZD provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (

pr, 10

s MAX). As a result,

the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the

asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the GAL20LV8ZD.
First, the V

rise must be monotonic. Second, the clock input

must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of

pr time. As in

normal system operation, avoid clocking the device until all input
and feedback path setup times have been met. The clock must
also meet the minimum pulse width requirements.

Typical Output

Typical Input

Vcc

Tri-State
Control

Feedback
(To Input Buffer)

Feedback

Data
Output

Vcc

ESD
Protection
Circuit

Vcc

Power-Up Reset

Input/Output Equivalent Schematic

Specifications

GAL20LV8ZD

Normalized Tpd vs Vcc

Supply Voltage (V)

Normalized Tpd

0.8

0.9

1.1

1.2

3.00

3.15

3.30

3.45

3.60

PT H->L

PT L->H

Normalized Tco vs Vcc

Supply Voltage (V)

Normalized Tco

0.8

0.9

1.1

1.2

3.00

3.15

3.30

3.45

3.60

RISE

FALL

Normalized Tsu vs Vcc

Supply Voltage (V)

Normalized Tsu

0.8

0.9

1.1

1.2

3.00

3.15

3.30

3.45

3.60

PT H->L

PT L->H

Normalized Tpd vs Temp

Temperature (deg. C)

Normalized Tpd

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

PT H->L

PT L->H

Normalized Tco vs Temp

Temperature (deg. C)

Normalized Tco

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

RISE

FALL

Normalized Tsu vs Temp

Temperature (deg. C)

Normalized Tsu

0.7

0.8

0.9

1.1

1.2

1.3

1.4

-55

-25

100

125

PT H->L

PT L->H

Delta Tpd vs # of Outputs

Switching

Number of Outputs Switching

Delta Tpd (ns)

-1

-0.75

-0.5

-0.25

RISE

FALL

Delta Tco vs # of Outputs

Switching

Number of Outputs Switching

Delta Tco (ns)

-0.5

-0.4

-0.3

-0.2

-0.1

RISE

FALL

Delta Tpd vs Output Loading

Output Loading (pF)

Delta Tpd (ns)

-2

100

150

200

250

300

RISE

FALL

Delta Tco vs Output Loading

Output Loading (pF)

Delta Tco (ns)

-4

-2

100

150

200

250

300

RISE

FALL

Typical AC and DC Characteristics

Specifications

GAL20LV8ZD

Input Clamp (Vik)

Vik (V)

Iik (mA)

100

-1.50

-1.20

-0.90

-0.60

-0.30

0.00

Vol vs Iol

Iol (mA)

Vol (V)

0.25

0.5

0.75

1.25

1.5

0.00

20.00

40.00

60.00

80.00

Voh vs Ioh

Ioh(mA)

Voh (V)

0.5

1.5

2.5

0.00

10.00

20.00

30.00

40.00

50.00

Voh vs Ioh

Ioh(mA)

Voh (V)

2.85

2.875

2.9

2.925

2.95

2.975

0.00

1.00

2.00

3.00

4.00

Normalized Icc vs Vcc

Supply Voltage (V)

Normalized Icc

0.70

0.80

0.90

1.00

1.10

1.20

1.30

3.00

3.15

3.30

3.45

3.60

Normalized Icc vs Temp

Temperature (deg. C)

Normalized Icc

0.9

0.95

1.05

1.1

1.15

1.2

-55

-25

100

125

Normalized Icc vs Freq.

Frequency (MHz)

Normalized Icc

0.75

1.00

1.25

1.50

1.75

2.00

100

Delta Icc vs Vin (1 input)

Vin (V)

Delta Icc (mA)

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

Typical AC and DC Characteristics

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GAL20LV8ZD

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GAL20LV8ZD