GAL20RA10

High-Speed Asynchronous E

CMOS PLD

Generic Array LogicTM

GND

Vcc

I/O/Q

DIP

PLCC

GND

I/O/Q

Vcc

I/O/Q

GAL

20RA10

Features

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

-- 7.5 ns Maximum Propagation Delay
-- Fmax = 83.3 MHz
-- 9 ns Maximum from Clock Input to Data Output
-- TTL Compatible 8 mA Outputs
-- UltraMOS

Advanced CMOS Technology

· 50% to 75% REDUCTION IN POWER FROM BIPOLAR

-- 75mA Typical Icc

· ACTIVE PULL-UPS ON ALL PINS

· E

CELL TECHNOLOGY

-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100 ms)
-- 20 Year Data Retention

· TEN OUTPUT LOGIC MACROCELLS

-- Independent Programmable Clocks

-- Independent Asynchronous Reset and Preset

-- Registered or Combinatorial with Polarity
-- Full Function and Parametric Compatibility with

PAL20RA10

· PRELOAD AND POWER-ON RESET OF ALL REGISTERS

-- 100% Functional Testability

· APPLICATIONS INCLUDE:

-- State Machine Control
-- Standard Logic Consolidation
-- Multiple Clock Logic Designs

· ELECTRONIC SIGNATURE FOR IDENTIFICATION

GAL20RA10

Top View

PROGRAMMABLE

AND-ARRAY

(80X40)

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

July 1997

Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

20ra10_02

Description

The GAL20RA10 combines a high performance CMOS process
with electrically erasable (E

) floating gate technology to provide

the highest speed performance available in the PLD market. Lattice
Semiconductor's E

CMOS circuitry achieves power levels as low

as 75mA typical I

which represents a substantial savings in power

when compared to bipolar counterparts. E

technology offers high

speed (<100ms) erase times providing the ability to reprogram,
reconfigure or test the devices quickly and efficiently.

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL20RA10 is a direct parametric compatible CMOS
replacement for the PAL20RA10 device.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. Therefore, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Functional Block Diagram

Pin Configuration

Specifications

GAL20RA10

)

(

)

(

)

(

)

(

Industrial Grade Specifications

)

(

)

(

)

(

)

(

Blank = Commercial
I = Industrial

Grade

Package

Power

L = Low Power

Speed (ns)

XXXXXXXX

X X

Device Name

P = Plastic DIP
J = PLCC

GAL20RA10B

GAL20RA10 Ordering Information

Commercial Grade Specifications

Part Number Description

Specifications

GAL20RA10

Output Logic Macrocell (OLMC)

The GAL20RA10 OLMC consists of 10 D flip-flops with indi-
vidual asynchronous programmable reset, preset and clock product
terms. The sum of four product terms and an Exclusive-OR pro-
vide a programmable polarity D-input to each flip-flop. An output
enable term combined with the dedicated output enable pin pro-
vides tri-state control of each output. Each OLMC has a flip-flop
bypass, allowing any combination of registered or combinatorial
outputs.

The GAL20RA10 has 10 dedicated input pins and 10 program-
mable I/O pins, which can be either inputs, outputs, or dynamic I/
O. Each pin has a unique path to the logic array. All macrocells
have the same type and number of data and control product terms,
allowing the user to exchange I/O pin assignments without restric-
tion.

Independent Programmable Clocks

An independent clock control product term is provided for each
GAL20RA10 macrocell. Data is clocked into the flip-flop on the
active edge of the clock product term. The use of individual clock
control product terms allow up to ten separate clocks. These clocks
can be derived from any pin or combination of pins and/or feedback
from other flip-flops. Multiple clock sources allow a number of
asynchronous register functions to be combined into a single
GAL20RA10. This allows the designer to combine discrete logic
functions into a single device.

Programmable Polarity

The polarity of the D-input to each macrocell flip-flop is individually
programmable to be active high or low. This is accomplished with
a programmable Exclusive-OR gate on the D-input of each flip-
flop. The polarity of the pin is active low when XOR bit is pro-
grammed (or zero) and is active high when XOR bit is erased (or
one). Because of the inverted output buffer, the XOR gate output
node is opposite polarity from the pin. It should be noted that the
programmable polarity only affects the data latched into the flip-flop
on the active edge of the clock product term. The reset, preset and
preload will alter the state of the flip-flop independent of the state
of programmable polarity bit. The ability to program the active po-
larity of the D-inputs can be used to reduce the total number of
product terms used, by allowing the DeMorganization of the logic
functions. This logic reduction is accomplished by the logic com-
piler, and does not require the designer to define the polarity.

Output Enable

The output of each GAL20RA10 macrocell is controlled by the
"AND'ing" of an independent output enable product term and a
common active low output enable pin (pin 13 on DIP package / pin
16 on PLCC package). The output is enabled while the output en-
able product term is active and the output enable pin is low. This
output control structure allows several output enable alternatives.

Combinatorial Control

The register in each GAL20RA10 macrocell may be bypassed by
asserting both the reset and preset product terms. While both
product terms are active the flip-flop is bypassed and the D- input
is presented directly to the inverting output buffer. This provides
the designer the ability to dynamically configure any macrocell as
a combinatorial output, or to fix the macrocell as combinatorial only
by forcing both reset and preset product terms active. Some logic
compilers will configure macrocells as registered or combinatorial
based on the logic equations, others require the designer to force
the reset and preset product terms active for combinatorial
macrocells.

Parallel Flip-Flop Preload

The flip-flops of a GAL20RA10 can be reset or preset from the
I/O pins by applying a logic low to the preload pin (pin 1 on DIP
package / pin 2 on PLCC package) and applying the desired logic
level to each I/O pin. The I/O pins must remain valid for the preload
setup and hold time. All 10 flip-flops are reset or preset during
preload, independent of all other OLMC inputs.

A logic low on an I/O pin during preload will preset the flip-flop, a
logic high will reset the flip-flop. The output of any flip-flop to be
preloaded must be disabled. Enabling the output during preload
will maintain the current logic state. It should be noted that the
preload alters the state of the flip-flop whose output is inverted by
the output buffer. A reset of the flip-flop will result in the output pin
becoming a logic high and a preset will result in a logic low. Note
that the common output enable pin will disable all 10 outputs of the
GAL20RA10 when held high.

RESET PRESET FUNCTION

Registered function of data product term

Reset register to "0" (device pin = "1")

Preset register to "1" (device pin = "0")

Asynchronous Reset and Preset

Each GAL20RA10 macrocell has an independent asynchronous
reset and preset control product term. The reset and preset product
terms are level sensitive, and will hold the flip-flop in the reset or
preset state while the product term is active independent of the clock
or D-inputs. It should be noted that the reset and preset term al-
ter the state of the flip-flop whose output is inverted by the output
buffer. A reset of the flip-flop will result in the output pin becoming
a logic high and a preset will result in a logic low.

Specifications

GAL20RA10B

Recommended Operating Conditions

Commercial Devices:
Ambient Temperature (T

) ............................. 0 to +75

Supply voltage (V

)

with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:
Ambient Temperature (T

) ..........................-40 to +85

Supply voltage (V

)

with Respect to Ground ..................... +4.50 to +5.50V

Absolute Maximum Ratings

(1)

Supply voltage V

....................................... -0.5 to +7V

Input voltage applied ........................... -2.5 to V

+1.0V

Off-state output voltage applied .......... -2.5 to V

+1.0V

Storage Temperature ................................. -65 to 150

Ambient Temperature with

Power Applied ......................................... -55 to 125

1.Stresses above those listed under the "Absolute Maximum

Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

Input Low Voltage

Vss 0.5

0.8

Input High Voltage

2.0

Vcc+1

Input or I/O Low Leakage Current

(MAX.)

-100

Input or I/O High Leakage Current

3.5V

Output Low Voltage

= MAX. Vin = V

or V

0.5

Output High Voltage

= MAX. Vin = V

or V

2.4

Low Level Output Current

High Level Output Current

-3.2

Output Short Circuit Current

= 5V

OUT

= 0.5V T

= 25

-50

-135

COMMERCIAL

Operating Power

= 0.5V V

= 3.0V

L -7/-10/-15/-20/-30

100

Supply Current

toggle

= 15MHz Outputs Open

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.

MAX.

UNITS

INDUSTRIAL

Operating Power

= 0.5V V

= 3.0V

L -20

120

Supply Current

toggle

= 15MHz Outputs Open

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and T

= 25

Specifications

GAL20RA10B

SYMBOL

PARAMETER

MAXIMUM*

UNITS

TEST CONDITIONS

Input Capacitance

= 5.0V, V

= 2.0V

I/O

I/O Capacitance

= 5.0V, V

I/O

= 2.0V

*Characterized but not 100% tested.

Input or I/O to Combinatorial Output

7.5

Clock to Output Delay

Setup Time, Input or Fdbk before Clk

Hold Time, Input or Fdbk after Clk

max

Maximum Clock Frequency with

83.3

66.7

45.0

33.3

20.0

MHz

External Feedback, 1/(tsu + tco)

Maximum Clock Frequency with

83.3

71.4

50.0

41.7

25.0

MHz

No Feedback

Clock Pulse Duration, High

Clock Pulse Duration, Low

en/

dis

B,C

I or I/O to Output Enabled / Disabled

7.5

en/

dis

B,C

to Output Enabled / Disabled

ar/

Input or I/O to Async. Reset / Preset

arw/

apw

Async. Reset / Preset Pulse Duration

arr/

apr

Async. Reset / Preset Recovery Time

Preload Pulse Duration

Preload Setup Time

Preload Hold Time

UNITS

-30

MIN.

MAX.

-20

MIN.

MAX.

-15

MIN.

MAX.

-10

MIN.

MAX.

PARAM.

DESCRIPTION

TEST

COND

-7

MIN.

MAX.

COM

COM / IND

COM

1) Refer to Switching Test Conditions section.
2) Refer to fmax Descriptions section.

AC Switching Characteristics

Over Recommended Operating Conditions

Capacitance (T

= 25

C, f = 1.0 MHz)

Specifications

GAL20RA10

Typical Input Pull-up Characteristic

Electronic Signature

An electronic signature word is provided in every GAL20RA10
device. It contains 64 bits of reprogrammable memory that con-
tains user defined data. Some uses include user ID codes, revi-
sion numbers, pattern identification or inventory control codes. The
signature data is always available to the user independent of the
state of the security cell.

NOTE: The electronic signature bits if programmed to any value
other then zero(0) will alter the checksum of the device.

Security Cell

A security cell is provided in every GAL20RA10 device as a deter-
rent to unauthorized copying of the device pattern. Once pro-
grammed, this cell prevents further read access of the device
pattern information. This cell can be only be reset by reprogram-
ming the device. The original pattern can never be examined once
this cell is programmed. The Electronic Signature is always avail-
able regardless of the security cell state.

Latch-Up Protection

GAL20RA10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.

1 . 0

2 . 0

3 . 0

4 . 0

5 . 0

- 6 0

- 2 0

- 4 0

In p u t V o lt ag e ( V o lt s)

I
nput

r
r
e

(

)

Device Programming

GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
part of the programming cycle.

Input Buffers

GAL20RA10 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high impedance
and present a much lighter load to the driving logic than traditional
bipolar devices.

GAL20RA10 input buffers have active pull-ups within their input
structure. As a result, unused inputs and I/Os will float to a TTL
"high" (logical "1"). Lattice Semiconductor recommends that all un-
used inputs and tri-stated I/O pins be connected to another active
input, Vcc, or GND. Doing this will tend to improve noise immu-
nity and reduce Icc for the device.

Specifications

GAL20RA10

Vcc

Vref

Active Pull-up
Circuit

ESD
Protection
Circuit

Vcc

Typical Input

Circuitry within the GAL20RA10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1

s MAX). As a result,

the state on the registered output pins (if they are enabled) will
be high on power-up, because of the inverting buffer on the output
pins. This feature can greatly simplify state machine design by
providing a known state on power-up. The timing diagram for
power-up is shown to the right. Because of the asynchronous

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Vcc (min.)

Internal Register
Reset to Logic "0"

Device Pin
Reset to Logic "1"

nature of system power-up, some conditions must be met to
provide a valid power-up reset of the GAL20RA10. First, the Vcc
rise must be monotonic. Second, the clock input must be at a static
TTL level as shown in the diagram during power up. The regis-
ters will reset within a maximum of 1

s. As in normal system op-

eration, avoid clocking the device until all input and feedback path
setup times have been met. The clock must also meet the mini-
mum pulse width requirements.

(Vref Typical = 3.2V)

Vcc

Vref

Tri-State
Control

Active Pull-up
Circuit

Feedback
(To Input Buffer)

Feedback

Data
Output

Typical Output

Power-Up Reset

Input/Output Equivalent Schematics

Specifications

GAL20RA10

Normalized Tpd vs Vcc

Supply Voltage (V)

Normalized Tpd

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

Normalized Tco vs Vcc

Supply Voltage (V)

Normalized Tco

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

Normalized Tsu vs Vcc

Supply Voltage (V)

Normalized Tsu

0.6

0.8

1.2

1.4

4.50

4.75

5.00

5.25

5.50

Normalized Tpd vs Temp

Temperature (deg. C)

Normalized Tpd

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

Normalized Tco vs Temp

Temperature (deg. C)

Normalized Tco

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

Normalized Tsu vs Temp

Temperature (deg. C)

Normalized Tsu

0.6

0.8

1.2

1.4

1.6

-55

-25

100

125

Delta Tpd vs # of Outputs

Switching

Number of Outputs Switching

Delta Tpd (ns)

-1.5

-1

-0.5

Delta Tco vs # of Outputs

Switching

Number of Outputs Switching

Delta Tco (ns)

-2

-1.5

-1

-0.5

Delta Tpd vs Output

Loading

Output Loading (pF)

Delta Tpd (ns)

-4

-2

100

150

RISE

FALL

Delta Tco vs Output

Loading

Output Loading (pF)

Delta Tco (ns)

-4

-2

100

150

RISE

FALL

GAL10RA10B-7/-10: Typical AC and DC Characteristic Diagrams

Specifications

GAL20RA10

Normalized Tpd vs Vcc

Supply Voltage (V)

Normalized Tpd

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

PT H->L

PT L->H

Normalized Tco vs Vcc

Supply Voltage (V)

Normalized Tco

0.9

0.95

1.05

1.1

4.50

4.75

5.00

5.25

5.50

RISE

FALL

Normalized Tsu vs Vcc

Supply Voltage (V)

Normalized Tsu

0.4

0.6

0.8

1.2

1.4

1.6

4.50

4.75

5.00

5.25

5.50

Normalized Tpd vs Temp

Temperature (deg. C)

Normalized Tpd

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

125

PT H->L

PT L->H

Normalized Tco vs Temp

Temperature (deg. C)

Normalized Tco

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

125

RISE

FALL

Normalized Tsu vs Temp

Temperature (deg. C)

Normalized Tsu

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

-55

-25

125

Delta Tpd vs # of Outputs

Switching

Number of Outputs Switching

Delta Tpd (ns)

-1.2

-1

-0.8

-0.6

-0.4

-0.2

RISE

FALL

Delta Tco vs # of Outputs

Switching

Number of Outputs Switching

Delta Tco (ns)

-1.2

-1

-0.8

-0.6

-0.4

-0.2

RISE

FALL

Delta Tpd vs Output

Loading

Output Loading (pF)

Delta Tpd (ns)

-4

-2

100

150

200

250

300

RISE

FALL

Delta Tco vs Output

Loading

Output Loading (pF)

Delta Tco (ns)

-4

-2

100

150

200

250

300

RISE

FALL

GAL10RA10B-15/-20/-30: Typical AC and DC Characteristic Diagrams

Document Outline

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Document Outline

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