GAL20V8Z

GAL20V8ZD

Zero Power E

CMOS PLD

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

December 1997

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

I/O

N C

I/O/Q

2 8

I/DPP

N C

1 1

1 4

1 6

1 9

2 5

1 2

1 8

2 1

2 3

2 6

I/O/Q

I/C

/
Q

I/O

I/ O/ Q

I /O E

I/C L K

I/D P P

V c c

G N D

1 2

1 3

2 4

1 8

Features

· ZERO POWER E

CMOS TECHNOLOGY

-- 100

A Standby Current

-- Input Transition Detection on GAL20V8Z
-- Dedicated Power-down Pin on GAL20V8ZD
-- Input and Output Latching During Power Down

· HIGH PERFORMANCE E

CMOS TECHNOLOGY

-- 12 ns Maximum Propagation Delay
-- Fmax = 83.3 MHz
-- 8 ns Maximum from Clock Input to Data Output
-- TTL Compatible 16 mA Output Drive
-- UltraMOS

Advanced CMOS Technology

· E

CELL TECHNOLOGY

-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention

· EIGHT OUTPUT LOGIC MACROCELLS

-- Maximum Flexibility for Complex Logic Designs
-- Programmable Output Polarity
-- Architecturally Similar to Standard GAL20V8

· PRELOAD AND POWER-ON RESET OF ALL REGISTERS

-- 100% Functional Testability

· APPLICATIONS INCLUDE:

-- Battery Powered Systems
-- DMA Control
-- State Machine Control
-- High Speed Graphics Processing

· ELECTRONIC SIGNATURE FOR IDENTIFICATION

GAL20V8Z

GAL20V8ZD

Top View

DIP

GAL

20V8Z

20V8ZD

CLK

I/O/Q

I/DPP

I/OE

I/CLK

OLMC

IMUX

PROGRAMMABLE

AND-ARRAY

(64 X 40)

OLMC

PLCC

20v8zzd_03

Description

The GAL20V8Z and GAL20V8ZD, at 100

A standby current and

12ns propagation delay provides the highest speed and lowest
power combination PLD available in the market. The
GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad-
vanced zero power E

CMOS process, which combines CMOS with

Electrically Erasable (E

) floating gate technology.

The GAL20V8Z uses Input Transition Detection (ITD) to put the
device in standby mode and is capable of emulating the full func-
tionality of the standard GAL20V8. The GAL20V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 19 inputs available to the AND array.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Functional Block Diagram

Pin Configuration

Specifications

GAL20V8Z

GAL20V8ZD

Tpd (ns)

Tsu (ns)

Tco (ns)

Icc (mA)

(

Ordering #

Package

100

GAL20V8Z-12QP

24-Pin Plastic DIP

100

GAL20V8Z-12QJ

28-Lead PLCC

100

GAL20V8Z-15QP

24-Pin Plastic DIP

100

GAL20V8Z-15QJ

28-Lead PLCC

Tpd (ns)

Tsu (ns)

Tco (ns)

Icc (mA)

(

Ordering #

Package

100

GAL20V8ZD-12QP

24-Pin Plastic DIP

100

GAL20V8ZD-12QJ

28-Lead PLCC

100

GAL20V8ZD-15QP

24-Pin Plastic DIP

100

GAL20V8ZD-15QJ

28-Lead PLCC

GAL20V8ZD: Commercial Grade Specifications

Blank = Commercial

Grade

Package

Active Power

Q = Quarter Power

XXXXXXXX

X X

Device Name

P = Plastic DIP
J = PLCC

GAL20V8Z (Zero Power ITD)

GAL20V8ZD (Zero Power DPP)

Speed (ns)

GAL20V8Z/ZD Ordering Information

GAL20V8Z: Commercial Grade Specifications

Part Number Description

Specifications

GAL20V8Z

GAL20V8ZD

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,

control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in-
put/output configuration. These two global and 16 individual archi-
tecture bits define all possible configurations in a GAL20V8Z/ZD.
The information given on these architecture bits is only to give a
better understanding of the device. Compiler software will trans-
parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.

Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft-
ware manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.

In registered mode pin 1(2) and pin 13(16) are permanently con-
figured as clock and output enable, respectively. These pins cannot
be configured as dedicated inputs in the registered mode.

In complex mode pin 1(2) and pin 13(16) become dedicated in-
puts and use the feedback paths of pin 22(26) and pin 15(18) re-
spectively. Because of this feedback path usage, pin 22(26) and
pin 15(18) do not have the feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
18(21) and 19(23)) will not have the feedback option as these pins
are always configured as dedicated combinatorial output.

When using the standard GAL20V8 JEDEC fuse pattern generated
by the logic compilers for the GAL20V8ZD, special attention must
be given to pin 4(5) (DPP) to make sure that it is not used as one
of the functional inputs.

Output Logic Macrocell (OLMC)

Compiler Support for OLMC

Specifications

GAL20V8Z

GAL20V8ZD

Combinatorial Configuration for Registered Mode

- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1(2) & Pin 13(16) are permanently configured as
CLK &

for registered output configuration.

Registered Configuration for Registered Mode

- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1(2) controls common CLK for the registered

outputs.

- Pin 13(16) controls common

for the registered

outputs.

- Pin 1(2) & Pin 13(16) are permanently configured as

CLK &

for registered output configuration.

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity, I/O and register placement.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub-
sets of the I/O function.

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

CLK

XOR

Registered Mode

Specifications

GAL20V8Z

GAL20V8ZD

In the Complex mode, macrocells are configured as output only or
I/O functions.

Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 15(18) & 22(26)) do not have input capability.
Designs requiring eight I/Os can be implemented in the Registered
mode.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1(2) and
13(16) are always available as data inputs into the AND array.

Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 16(19) through Pin 21(25) are configured to this
function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 15(18) and Pin 22(26) are configured to this
function.

XOR

Complex Mode

Specifications

GAL20V8Z

GAL20V8ZD

In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

Architecture configurations available in this mode are similar to the
common 14L8 and 16P6 devices with many permutations of ge-
neric output polarity or input choices.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro-
grammable polarity.

Pins 1(2) and 13(16) are always available as data inputs into the
AND array. The center two macrocells (pins 18(21) & 19(23)) can-
not be used in the input configuration.

Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- All OLMC except pins 18(21) & 19(23) can be
configured to this function.

Combinatorial Output Configuration for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- Pins 18(21) & 19(23) are permanently configured to
this function.

Dedicated Input Configuration for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 18(21) & 19(23) can be
configured to this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

Vcc

XOR

Vcc

XOR

Simple Mode

Specifications

GAL20V8Z

GAL20V8ZD

SYMBOL

PARAMETER

MAXIMUM*

UNITS

TEST CONDITIONS

Input Capacitance

= 5.0V, V

= 2.0V

I/O

I/O Capacitance

= 5.0V, V

I/O

= 2.0V

*Characterized but not 100% tested

Recommended Operating Conditions

Commercial Devices:
Ambient Temperature (T

) ............................... 0 to 75

Supply voltage (V

)

with Respect to Ground ..................... +4.75 to +5.25V

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.

MAX.

UNITS

Input Low Voltage

Vss 0.5

0.8

Input High Voltage

2.0

Vcc+1

Input or I/O Low Leakage Current

(MAX.)

Input or I/O High Leakage Current

3.5V

Output Low Voltage

= MAX. Vin = V

or V

0.5

Output High Voltage

= MAX. Vin = V

or V

2.4

= -100

A Vin = V

or V

Vcc-1

Low Level Output Current

High Level Output Current

3.2

Output Short Circuit Current

= 5V

OUT

= 0.5V

= 25

150

COMMERCIAL

Stand-by Power

= GND V

= Vcc Outputs Open

Z-12/-15

100

Supply Current

ZD-12/-15

Operating Power

= 0.5V V

= 3.0V

Z-12/-15

Supply Current

toggle

= 15 MHz Outputs Open

ZD-12/-15

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2) Typical values are at Vcc = 5V and T

= 25

Absolute Maximum Ratings

(1)

Supply voltage V

........................................ .5 to +7V

Input voltage applied .......................... 2.5 to V

+1.0V

Off-state output voltage applied ......... 2.5 to V

+1.0V

Storage Temperature ................................ 65 to 150

Ambient Temperature with
Power Applied ........................................... 55 to 125

1. Stresses above those listed under the "Absolute Maximum

Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

Capacitance (TA = 25

C, f = 1.0 MHz)

Specifications

GAL20V8Z

GAL20V8ZD

Specifications

GAL20V8Z

AC Switching Characteristics

Over Recommended Operating Conditions

Input or I/O to Combinational Output

Clock to Output Delay

Clock to Feedback Delay

Setup Time, Input or Feedback before Clock

Hold Time, Input or Feedback after Clock

Maximum Clock Frequency with

MHz

External Feedback, 1/(tsu + tco)

max

Maximum Clock Frequency with

62.5

45.5

MHz

Internal Feedback, 1/(tsu + tcf)

Maximum Clock Frequency with

83.3

62.5

MHz

No Feedback

Clock Pulse Duration, High

Clock Pulse Duration, Low

Input or I/O to Output Enabled

OE to Output Enabled

dis

Input or I/O to Output Disabled

OE to Output Disabled

Last Active Input to Standby

140

150

Standby to Active Output

PARAMETER

UNITS

-15

MIN.

MAX.

TEST

COND

DESCRIPTION

-12

MIN.

MAX.

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
4) Add

sa to

pd,

su,

en and

dis when the device is coming out of standby state.

COM

POWER

INPUT or
I/O FEEDBACK

CLK

OUTPUT

en,

dis

Icc

Isb

* Note: Rising clock edges
are allowed during

sa but

outputs are not guaranteed.

Standby Power Timing Waveforms

Specifications

GAL20V8Z

GAL20V8ZD

Specifications

GAL20V8ZD

AC Switching Characteristics

Over Recommended Operating Conditions

Input or I/O to Combinational Output

Clock to Output Delay

Clock to Feedback Delay

Setup Time, Input or Feedback before Clock

Hold Time, Input or Feedback after Clock

Maximum Clock Frequency with

MHz

External Feedback, 1/(tsu + tco)

max

Maximum Clock Frequency with

62.5

45.5

MHz

Internal Feedback, 1/(tsu + tcf)

Maximum Clock Frequency with

83.3

62.5

MHz

No Feedback

Clock Pulse Duration, High

Clock Pulse Duration, Low

Input or I/O to Output Enabled

OE to Output Enabled

dis

Input or I/O to Output Disabled

OE to Output Disabled

PARAMETER

UNITS

-15

MIN. MAX.

TEST

COND

DESCRIPTION

-12

MIN. MAX.

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.

COM

Specifications

GAL20V8Z

GAL20V8ZD

Specifications

GAL20V8ZD

whd

DPP Pulse Duration High

wld

DPP Pulse Duration Low

ivdh

Valid Input before DPP High

gvdh

Valid OE before DPP High

cvdh

Valid Clock Before DPP High

dhix

Input Don't Care after DPP High

dhgx

OE Don't Care after DPP High

dhcx

Clock Don't Care after DPP High

dliv

DPP Low to Valid Input

dlgv

DPP Low to Valid OE

dlcv

DPP Low to Valid Clock

dlov

DPP Low to Valid Output

PARAMETER

UNITS

-15

MIN. MAX.

TEST

COND

DESCRIPTION

-12

MIN. MAX.

1) Refer to Switching Test Conditions section.

ACTIVE TO STANDBY

STANDBY TO ACTIVE

dhcx

DPP

INPUT or
I/O FEEDBACK

CLK

OUTPUT

cvdh

gvdh

ivdh

dhgx

dhix

p d ,

e n ,

d i s

c o

dliv

dlgv

d lcv

dlov

Dedicated Power-Down Pin Specifications

Over Recommended Operating Conditions

COM

Dedicated Power-Down Pin Timing Waveforms

Specifications

GAL20V8Z

GAL20V8ZD

Output Load Conditions (see figure)

Test Condition

300

390

50pF

Active High

390

50pF

Active Low

300

390

50pF

Active High

390

5pF

Active Low

300

390

5pF

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns 10% 90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

See Figure

3-state levels are measured 0.5V from steady-state active
level.

Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.

max with Internal Feedback 1/(

su+

cf)

max with External Feedback 1/(

su+

co)

Note: fmax with external feedback is calculated from
measured tsu and tco.

TEST POINT

C *

FROM OUTPUT (O/Q)
UNDER TEST

+5V

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

R E G I S T E R

L O G I C
A R R A Y

c o

s u

C L K

max with No Feedback

Note: fmax with no feedback may be less than 1/(twh
+ twl). This is to allow for a clock duty cycle of other
than 50%.

LOGIC
ARRAY

CLK

su +

CLK

LOGIC
ARRAY

max Specifications

Switching Test Conditions

Specifications

GAL20V8Z

GAL20V8ZD

Electronic Signature

An electronic signature word is provided in every GAL20V8Z/ZD
device. It contains 64 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is al-
ways available to the user independent of the state of the security
cell.

NOTE: The electronic signature is included in checksum calcula-
tions. Changing the electronic signature will alter checksum.

Security Cell

A security cell is provided in the GAL20V8Z/ZD devices to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The electronic signature data is always avail-
able to the user, regardless of the state of this security cell.

Device Programming

GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the GAL Development Tools Section of the Data
Book). Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.

Input Transition Detection (ITD)

The GAL20V8Z relies on its internal input detection circuitry to put
the device in power down mode. If there is no input transition for
the specified period of time, the device will go into the power down
state. Any valid input transition will put the device back into active
state. The first rising clock transition from power-down state only
acts as a wake up signal into the device and will not clock the data
input through to the output (refer to standby power timing waveform
for more detail). Any input pulse widths greater than 5ns at input
voltage level of 1.5V will be detected as input transition. The device
will not detect any input pulse widths less than 1ns measured at
input voltage level of 1.5V as input transition.

Dedicated Power-Down Pin

The GAL20V8ZD uses pin 4 (pin 5 on PLCC) as the dedicated
power-down signal to put the device in power-down state. DPP is
an active high signal where logic high driven on this signal puts the
device into power-down state. Input pin 4 (5) cannot be used as
a functional input on this device.

Input Current (uA)

Input Voltage (Volts)

Typical Input Characteristic

- 4 0

- 3 0

- 2 0

- 1 0

1 0

2 0

3 0

4 0

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.

The GAL20V8Z/ZD devices includes circuitry that allows each reg-
istered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If nec-
essary, approved GAL programmers capable of executing text
vectors perform output register preload automatically.

Input Buffers

GAL20V8Z/ZD devices are designed with TTL level compatible in-
put buffers. These buffers, with their characteristically high imped-
ance, load driving logic much less than traditional bipolar devices.
This allows for a greater fan out from the driving logic.

GAL20V8Z/ZD input buffers have latches within the buffers. As a
result, when the device goes into standby mode the inputs will be
latched to its values prior to standby. In order to overcome the input
latches, they will have to be driven by an external source. Lattice
Semiconductor recommends that all unused inputs and tri-stated
I/O pins for both devices be connected to another active input, V

or GND. Doing this will tend to improve noise immunity and reduce
I

for the device.

Specifications

GAL20V8Z

GAL20V8ZD

Typical Output

Typical Input

Circuitry within the GAL20V8Z/ZD provides a reset signal to all
registers during power-up. All internal registers will have their Q
outputs set low after a specified time (

pr, 1

s MAX). As a result,

the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the

asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the GAL20V8Z/ZD.
First, the V

rise must be monotonic. Second, the clock input

must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of

pr time. As in

normal system operation, avoid clocking the device until all input
and feedback path setup times have been met. The clock must
also meet the minimum pulse width requirements.

Vcc

ESD
Protection
Circuit

Vcc

Tri-State
Control

Feedback
(To Input Buffer)

Feedback

Data
Output

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Vcc (min.)

Internal Register
Reset to Logic "0"

Device Pin
Reset to Logic "1"

Power-Up Reset

Input/Output Equivalent Schematics

Specifications

GAL20V8Z

GAL20V8ZD

Normalized Tpd vs Vcc

Supply Voltage (V)

Normalized Tpd

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

PT H->L

PT L->H

Normalized Tco vs Vcc

Supply Voltage (V)

Normalized Tco

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

RISE

FALL

Normalized Tsu vs Vcc

Supply Voltage (V)

Normalized Tsu

0.8

0.9

1.1

1.2

1.3

1.4

4.50

4.75

5.00

5.25

5.50

PT H->L

PT L->H

Normalized Tpd vs Temp

Temperature (deg. C)

Normalized Tpd

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

PT H->L

PT L->H

Normalized Tco vs Temp

Temperature (deg. C)

Normalized Tco

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

RISE

FALL

Normalized Tsu vs Temp

Temperature (deg. C)

Normalized Tsu

0.7

0.8

0.9

1.1

1.2

1.3

1.4

-55

-25

100

125

PT H->L

PT L->H

Delta Tpd vs # of Outputs

Switching

Number of Outputs Switching

Delta Tpd (ns)

-2

-1.5

-1

-0.5

RISE

FALL

Delta Tco vs # of Outputs

Switching

Number of Outputs Switching

Delta Tco (ns)

-2

-1.5

-1

-0.5

RISE

FALL

Delta Tpd vs Output Loading

Output Loading (pF)

Delta Tpd (ns)

-2

100

150

200

250

300

RISE

FALL

Delta Tco vs Output Loading

Output Loading (pF)

Delta Tco (ns)

-2

100

150

200

250

300

RISE

FALL

Typical AC and DC Characteristics

Specifications

GAL20V8Z

GAL20V8ZD

Vol vs Iol

Iol (mA)

Vol (V)

0.25

0.5

0.75

1.25

1.5

0.00

20.00

40.00

60.00

Voh vs Ioh

Ioh(mA)

Voh (V)

0.00

10.00

20.00

30.00

40.00

50.00

60.00

Voh vs Ioh

Ioh(mA)

Voh (V)

2.5

3.5

4.5

0.00

1.00

2.00

3.00

4.00

Normalized Icc vs Vcc

Supply Voltage (V)

Normalized Icc

0.70

0.80

0.90

1.00

1.10

1.20

1.30

4.50

4.75

5.00

5.25

5.50

Normalized Icc vs Temp

Temperature (deg. C)

Normalized Icc

0.8

0.9

1.1

1.2

-55

-25

100

125

Normalized Icc vs Freq. (DPP

& ITD > 10MHz)

Frequency (MHz)

Normalized Icc

0.80

0.90

1.00

1.10

1.20

1.30

100

Delta Icc vs Vin (1 input)

Vin (V)

Delta Icc (mA)

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Input Clamp (Vik)

Vik (V)

Iik (mA)

-1.00

-0.80

-0.60

-0.40

-0.20

0.00

Normalized Icc vs Freq. (ITD)

Frequency (KHz)

Normalized Icc

0.2

0.4

0.6

0.8

100

1000

10000

Typical AC and DC Characteristics

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GAL20V8Z-12QJ

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GAL20V8Z-12QJ