GAL20VP8

High-Speed E

CMOS PLD

Generic Array LogicTM

Features

· HIGH DRIVE E

CMOS

GAL

DEVICE

-- TTL Compatible 64 mA Output Drive
-- 15 ns Maximum Propagation Delay
-- Fmax = 80 MHz
-- 10 ns Maximum from Clock Input to Data Output
-- UltraMOS

Advanced CMOS Technology

· ENHANCED INPUT AND OUTPUT FEATURES

-- Schmitt Trigger Inputs
-- Programmable Open-Drain or Totem-Pole Outputs
-- Active Pull-Ups on All Inputs and I/O pins

· E

CELL TECHNOLOGY

-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention

· EIGHT OUTPUT LOGIC MACROCELLS

-- Maximum Flexibility for Complex Logic Designs
-- Programmable Output Polarity
-- Architecturally Compatible with Standard GAL20V8

· PRELOAD AND POWER-ON RESET OF ALL REGISTERS

-- 100% Functional Testability

· APPLICATIONS INCLUDE:

-- Ideal for Bus Control & Bus Arbitration Logic
-- Bus Address Decode Logic
-- Memory Address, Data and Control Circuits
-- DMA Control

· ELECTRONIC SIGNATURE FOR IDENTIFICATION

I/CLK

GND

Vcc

I/O/Q

I/OE

I/CLK

I/OE

I/O/Q

GND

I/O/Q

Vcc

I/O/Q

GAL20VP8

Top View

DIP

PLCC

GAL

20VP8

CLK

I/O/Q

I/OE

I/CLK

OLMC

IMUX

PROGRAMMABLE

AND-ARRAY

(64 X 40)

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

December 1997

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

20vp8_03

Description

The GAL20VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli-
cations. The GAL20VP8 is manufactured using Lattice
Semiconductor's advanced E

CMOS process which combines

CMOS with Electrically Erasable (E

) floating gate technology. High

speed erase times (<100ms) allow the devices to be reprogrammed
quickly and efficiently.

System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL20VP8
combines the familiar GAL20V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design flex-
ibility by allowing the Output Logic Macrocell (OLMC) to be con-
figured by the user. The 64mA output drive eliminates the need for
additional devices to provide bus-driving capability.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.

Functional Block Diagram

Pin Configuration

Specifications

GAL20VP8

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of

each macrocell controls the polarity of the output in any of the three
modes, while the AC1 and AC2 bit of each of the macrocells controls
the input/output and totem-pole/open-drain configuration. These
two global and 24 individual architecture bits define all possible con-
figurations in a GAL20VP8. The information given on these archi-
tecture bits is only to give a better understanding of the device.
Compiler software will transparently set these architecture bits from
the pin definitions, so the user should not need to directly manipulate
these architecture bits.

Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft-
ware manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1(2) and pin 12(14) are permanently con-
figured as clock and output enable, respectively. These pins cannot
be configured as dedicated inputs in the registered mode.

In complex mode pin 1(2) and pin 12(14) become dedicated in-
puts and use the feedback paths of pin 22(26) and pin 14(17) re-
spectively. Because of this feedback path usage, pin 22(26) and
pin 14(17) do not have the feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins (pins
17(20) and 19(23)) will not have the feedback option as these pins
are always configured as dedicated combinatorial output.

In addition to the architecture configurations, the logic compiler
software also supports configuration of either totem-pole or open-
drain outputs. The actual architecture bit configuration, again, is
transparent to the user with the default configuration being the
standard totem-pole output.

Output Logic Macrocell (OLMC)

Compiler Support for OLMC

Specifications

GAL20VP8

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub-
sets of the I/O function.

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1(2) controls common CLK for the registered
outputs.
- Pin 12(14) controls common

for the registered

outputs.
- Pin 1(2) & Pin 12(14) are permanently configured as
CLK &

for registered output configuration.

Combinatorial Configuration for Registered Mode

- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1(2) & Pin 12(14) are permanently configured as
CLK &

. for registered output configuration.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

CLK

XOR

Registered Mode

Specifications

GAL20VP8

In the Complex mode, macrocells are configured as output only or
I/O functions.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 14(17) & 22(26)) do not have input capability.
Designs requiring eight I/Os can be implemented in the Registered
mode.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1(2) and
12(14) are always available as data inputs into the AND array.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 15(18) through Pin 21(25) are configured to this
function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 14(17) and Pin 22(26) are configured to this
function.

XOR

Complex Mode

Specifications

GAL20VP8

In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro-
grammable polarity.

Pins 1(2) and 12(14) are always available as data inputs into the
AND array. The center two macrocells (pins 17(20) & 19(23)) can-
not be used in the input configuration.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- All OLMC except pins 17(20) & 19(23) can be
configured to this function.

Combinatorial Output Configuration for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pins 17(20) & 19(23) are permanently configured to
this function.

Dedicated Input Configuration for Simple Mode

- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- All OLMC except pins 17(20) & 19(23) can be
configured to this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

Vcc

XOR

Vcc

XOR

Simple Mode

Specifications

GAL20VP8

Recommended Operating Conditions

Commercial Devices:
Ambient Temperature (T

) ............................... 0 to 75

Supply voltage (V

)

with Respect to Ground ..................... +4.75 to +5.25V

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.

MAX.

UNITS

Input Low Voltage

Vss 0.5

0.8

Input High Voltage

2.0

Vcc+1

Input Clamp Voltage

Vcc = Min. I

32mA

1.2

Input or I/O Low Leakage Current

(MAX.)

100

Input or I/O High Leakage Current

3.5V

Output Low Voltage

= MAX. Vin = V

or V

0.5

Output High Voltage

= MAX. Vin = V

or V

2.4

Low Level Output Current

High Level Output Current

Output Short Circuit Current

= 5V

OUT

= 0.5V

= 25

400

1) Characterized but not 100% tested.
2) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
3) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
4) Typical values are at Vcc = 5V and T

= 25

COMMERCIAL

Operating Power

= 0.5V V

= 3.0V

L -15/-25

115

Supply Current

toggle

= 15MHz Outputs Open

Absolute Maximum Ratings

(1)

Supply voltage V

........................................ .5 to +7V

Input voltage applied .......................... 2.5 to V

+1.0V

Off-state output voltage applied ......... 2.5 to V

+1.0V

Storage Temperature ................................ 65 to 150

Ambient Temperature with
Power Applied ........................................... 55 to 125

1. Stresses above those listed under the "Absolute Maximum

Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

Specifications

GAL20VP8

Input or I/O to Combinational Output

Clock to Output Delay

Clock to Feedback Delay

4.5

Setup Time, Input or Feedback before Clock

Hold Time, Input or Feedback after Clock

Maximum Clock Frequency with

55.5

MHz

External Feedback, 1/(tsu + tco)

max

Maximum Clock Frequency with

MHz

Internal Feedback, 1/(tsu + tcf)

Maximum Clock Frequency with

MHz

No Feedback

Clock Pulse Duration, High

Clock Pulse Duration, Low

Input or I/O to Output Enabled

OE to Output Enabled

dis

Input or I/O to Output Disabled

OE to Output Disabled

-15

MIN. MAX.

PARAMETER

UNITS

-25

MIN. MAX.

TEST

COND

DESCRIPTION

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.

SYMBOL

PARAMETER

MAXIMUM*

UNITS

TEST CONDITIONS

Input Capacitance

= 5.0V, V

= 2.0V

I/O

I/O Capacitance

= 5.0V, V

I/O

= 2.0V

*Characterized but not 100% tested.

COM

AC Switching Characteristics

Over Recommended Operating Conditions

Capacitance (T

= 25

C, f = 1.0 MHz)

Specifications

GAL20VP8

max with Internal Feedback 1/(

su+

cf)

Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

max with External Feedback 1/(

su+

co)

Note: fmax with external feedback is calculated from measured
tsu and tco.

LOGIC
ARRAY

CLK

su +

max with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.

CLK

LOGIC
ARRAY

CLK

Output Load Conditions (see figure)

Test Condition

500

50pF

Active High

500

50pF

Active Low

500

50pF

Active High

500

5pF

Active Low

500

5pF

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns 10% 90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

See Figure

3-state levels are measured 0.5V from steady-state active
level.

TEST POINT

C *

FROM OUTPUT (O/Q)
UNDER TEST

+5V

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

max Descriptions

Switching Test Conditions

Specifications

GAL20VP8

Electronic Signature

An electronic signature word is provided in every GAL20VP8 de-
vice. It contains 64 bits of reprogrammable memory that can contain
user defined data. Some uses include user ID codes, revision num-
bers, or inventory control. The signature data is always available
to the user independent of the state of the security cell.

NOTE: The electronic signature is included in checksum calcula-
tions. Changing the electronic signature will alter the checksum.

Signature Cell

The security cell is provided on all GAL20VP8 devices to prevent
unauthorized copying of the array patterns. Once programmed,
the circuitry enabling array is disabled, preventing further program-
ming or verification of the array. The cell can only be erased by re-
programming the device, so the original configuration can never
be examined once this cell is programmed. Signature data is al-
ways available to the user.

Latch-Up Protection

GAL20VP8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any pos-
sibility of SCR induced latching.

Bulk Erase Mode

During a programming cycle, a clear function performs a bulk erase
of the array and the architecture word. In addition, the electronic
signature word and the security cell are erased. This mode resets
a previously configured device back to its original state, which is
all JEDEC ones.

Schmitt Trigger Inputs

One of the enhancements of the GAL20VP8 for bus interface logic
implementation is input gysteresis. The threshold of the positive
going edge is 1.5V, while the threshold of the negative going edge
is 1.3V. This provides a typical hysteresis of 200mV between
positive and negative transitions of the inputs.

Bulk Erase Mode

All eight outputs of the GAL20VP8 are capable of driving 64 mA
loads when driving low and 32 mA loads when driving high. Near
symmetrical high and low output drive capability provides small

skews between high-to-low and low-to-high output transitions.

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system

Typical Input Pull-up Characteristic

1.0

2.0

3.0

4.0 5.0

-60

-20

-40

Input Voltage (Volts)

Input Current (

operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.

The GAL20VP8 device includes circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing test vectors can
perform output register preload automatically.

Input Buffers

The GAL20VP8 devices are designed with TTL level compatible
input buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than
bipolar TTL devices.

GAL20VP8 input buffers have active pull-ups within their input
structure. As a result, unused inputs and I/O's will float to a TTL
"high" (logical "1"). Lattice Semiconductor recommends that all un-
used inputs and tri-stated I/O pins for both devices be connected
to another active input, V

, or GND. Doing this will tend to improve

noise immunity and reduce I

for the device.

Programmable Open-Drain Outputs

In addition to the standard GAL20V8 type configuration, the out-
puts of the GAL20VP8 are individually programmable either as a
standard totempole output or an open-drain output. The totempole
output drives the specified V

and V

levels whereas the open-

drain output drives only the specified V

. The V

level on the

open-drain output depends on the external loading and pull-up. This
output configuration is controlled by the AC2 fuse. When AC2 cell
is erased (JEDEC "1") the output is configured as a totempole out-
put and when AC2 cell is programmed (JEDEC "0") the output is
configured as an open-drain. The default configuration when the
device is in bulk erased state is totempole configuration. The AC2
fuses associated with each of the outputs is included in all of the
logic diagrams.

Specifications

GAL20VP8

Typical Output

Typical Input

Vref = 3.1V

Circuitry within the GAL20VP8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (

pr, 1

s MAX). As a result, the

state on the registered output pins (if they are enabled) will always
be high on power-up, regardless of the programmed polarity of
the output pins. This feature can greatly simplify state machine
design by providing a known state on power-up. The timing dia-
gram for power-up is shown above. Because of the asynchro-

nous nature of system power-up, some conditions must be met
to provide a valid power-up reset of the GAL20VP8. First, the V

rise must be monotonic. Second, the clock input must be at static
TTL level as shown in the diagram during power up. The registers
will reset within a maximum of

pr time. As in normal system op-

eration, avoid clocking the device until all input and feedback path
setup times have been met. The clock must also meet the mini-
mum pulse width requirements.

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Vcc (min.)

Internal Register
Reset to Logic "0"

Device Pin
Reset to Logic "1"

Vcc

Vref

Active Pull-up

Circuit

ESD
Protection
Circuit

Vcc

Vref

Tri-State
Control

Active Pull-up
Circuit

Feedback
(To Input Buffer)

Feedback

Data
Output

Power-Up Reset

Input/Output Equivalent Schematics

Specifications

GAL20VP8

Normalized Tpd vs Vcc

Supply Voltage (V)

Normalized Tpd

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

PT H->L

PT L->H

Normalized Tco vs Vcc

Supply Voltage (V)

Normalized Tco

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

RISE

FALL

Normalized Tsu vs Vcc

Supply Voltage (V)

Normalized Tsu

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

PT H->L

PT L->H

Normalized Tpd vs Temp

Temperature (deg. C)

Normalized Tpd

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

PT H->L

PT L->H

Normalized Tco vs Temp

Temperature (deg. C)

Normalized Tco

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

RISE

FALL

Normalized Tsu vs Temp

Temperature (deg. C)

Normalized Tsu

0.7

0.8

0.9

1.1

1.2

1.3

1.4

-55

-25

100

125

PT H->L

PT L->H

Delta Tpd vs # of Outputs

Switching

Number of Outputs Switching

Delta Tpd (ns)

-0.5

-0.4

-0.3

-0.2

-0.1

RISE

FALL

Delta Tco vs # of Outputs

Switching

Number of Outputs Switching

Delta Tco (ns)

-1.25

-1

-0.75

-0.5

-0.25

RISE

FALL

Delta Tpd vs Output Loading

Output Loading (pF)

Delta Tpd (ns)

-2

100

150

200

250

300

RISE

FALL

Delta Tco vs Output Loading

Output Loading (pF)

Delta Tco (ns)

-2

100

150

200

250

300

RISE

FALL

Typical AC and DC Characteristic Diagrams

Specifications

GAL20VP8

Vol vs Iol

Iol (mA)

Vol (V)

0.1

0.2

0.3

0.4

0.5

0.00

20.00

40.00

60.00

80.00

Voh vs Ioh

Ioh(mA)

Voh (V)

0.00

10.00

20.00

30.00

40.00

50.00

60.00

Voh vs Ioh

Ioh(mA)

Voh (V)

3.5

3.75

4.25

4.5

0.00

1.00

2.00

3.00

4.00

Normalized Icc vs Vcc

Supply Voltage (V)

Normalized Icc

0.80

0.90

1.00

1.10

1.20

4.50

4.75

5.00

5.25

5.50

Normalized Icc vs Temp

Temperature (deg. C)

Normalized Icc

0.7

0.8

0.9

1.1

1.2

-55

-25

100

125

Normalized Icc vs Freq.

Frequency (MHz)

Normalized Icc

0.90

1.00

1.10

1.20

1.30

1.40

100

Delta Icc vs Vin (1 input)

Vin (V)

Delta Icc (mA)

0.5

1.5

2.5

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Input Clamp (Vik)

Vik (V)

Iik (mA)

-2.00

-1.50

-1.00

-0.50

0.00

Typical AC and DC Characteristic Diagrams

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GAL20VP8

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GAL20VP8