GAL26CLV12

Low Voltage E

CMOS PLD

Generic Array LogicTM

VCC

I/O/Q

I/CLK

I/O/Q

GND

I/O/Q

FEATURES

Features

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

-- 5 ns Maximum Propagation Delay
-- Fmax = 200 MHz
-- 3.5 ns Maximum from Clock Input to Data Output
-- UltraMOS

Advanced CMOS Technology

· 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE

-- JEDEC-Compatible 3.3V Interface Standard
-- Inputs and I/O Interface with Standard 5V TTL Devices

· ACTIVE PULL-UPS ON ALL PINS

· E

CELL TECHNOLOGY

-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention

· TWELVE OUTPUT LOGIC MACROCELLS

-- Maximum Flexibility for Complex Logic Designs
-- Programmable Output Polarity

· PRELOAD AND POWER-ON RESET OF ALL REGISTERS

-- 100% Functional Testability

· APPLICATIONS INCLUDE:

-- Glue Logic for 3.3V Systems
-- DMA Control
-- State Machine Control
-- High Speed Graphics Processing
-- Standard Logic Speed Upgrade

· ELECTRONIC SIGNATURE FOR IDENTIFICATION

PROGRAMMABLE

AND-ARRAY

(122X52)

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

I/CLK

INPUT

RESET

PRESET

GAL26CLV12D

Top View

PLCC

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

July 1997

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Description

The GAL26CLV12D, at 5 ns maximum propagation delay time,
provides higher performance than its 5V counterpart. The
GAL26CLV12D can interface with both 3.3V and 5V signal levels.
The GAL26CLV12D is manufactured using Lattice Semiconductor's
advanced 3.3V E

CMOS process, which combines CMOS with

Electrically Erasable (E

) floating gate technology. High speed erase

times (<100ms) allow the devices to be reprogrammed quickly and
efficiently.

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

26clv12_02

Functional Block Diagram

Pin Configuration

Specifications

GAL26CLV12

GAL26CLV12D OUTPUT LOGIC MACROCELL (OLMC)

Each of the Macrocells of the GAL26CLV12D has two primary func-
tional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (S0 and S1), which are nor-
mally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.

REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC's D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop's /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.

NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.

COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
"on" (dedicated output), "off" (dedicated input), or "product-term
driven" (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.

The GAL26CLV12D has a variable number of product terms per
OLMC. Of the twelve available OLMCs, two OLMCs have access
to twelve product terms (pins 20 and 22), two have access to ten
product terms (pins 19 and 23), and the other eight OLMCs have
eight product terms each. In addition to the product terms available
for logic, each OLMC has an additional product term dedicated to
output enable control.

The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.

The GAL26CLV12D has a product term for Asynchronous Reset
(AR) and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchro-
nous Reset sets all registered outputs to zero any time this dedi-
cated product term is asserted. The Synchronous Preset sets all
registers to a logic one on the rising edge of the next clock pulse
after this product term is asserted.

NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.

A R

S P

C L K

4 T O 1

M U X

2 T O 1

M U X

Output Logic Macrocell (OLMC)

Output Logic Macrocell Configurations

Specifications

GAL26CLV12

PLCC Package Pinout

ASYNCHRONOUS RESET
(TO ALL REGISTERS)

0052

.
.
.

0468

OLMC

6344

6345

SYNCHRONOUS PRESET
(TO ALL REGISTERS)

OLMC

6346

6347

OLMC

6348

6349

OLMC

6350

6351

OLMC

6352

6353

OLMC

6354

6355

OLMC

6356

6357

OLMC

6358

6359

OLMC

6360

6361

OLMC

6362

6363

OLMC

6364

6365

OLMC

6366

6367

0000

0520

.
.
.

0936

0988

.
.
.

1404

1456

.
.
.

1872

1924

.
.
.
.

2444

3848

.
.
.
.

4368

2496

.
.
.
.
.

3120

3172

.
.
.
.
.

3796

4420

.
.
.

4836

4888

.
.
.

5304

5356

.
.
.

5772

5824

.
.
.

6240

6292

Electronic Signature

6368, 6369 ...

... 6430, 6431

Byte 7 Byte 6 Byte 5 Byte 4

Byte 2 Byte 1 Byte 0

Byte 3

GAL26CLV12D Logic Diagram/JEDEC Fuse Map

Specifications

GAL26CLV12

Input Low Voltage

Vss - 0.3

0.8

Input High Voltage

2.0

5.25

I/O High Voltage

2.0

Vcc+0.5

Input or I/O Low Leakage Current

(MAX.)

-100

Input or I/O High Leakage Current

(Vcc-0.2)V

Input Leakage Current

Vcc

5.25V

I/O Leakage Current

Vcc

5.25V

Output Low Voltage

= MAX. Vin = V

or V

0.4

= 500

A Vin = V

or V

0.2

Output High Voltage

= MAX. Vin = V

or V

2.4

= -100

A Vin = V

or V

Vcc-0.2V

Low Level Output Current

High Level Output Current

-8

Output Short Circuit Current

= 3.3V

OUT

= 0.5V T

= 25

-15

-80

Absolute Maximum Ratings

(1)

Supply voltage V

.................................... -0.5 to +4.6V

Input or I/O voltage applied ....................... -0.5 to +5.6V
Off-state output voltage applied ................ -0.5 to +4.6V
Storage Temperature ................................. -65 to 150

Ambient Temperature with

Power Applied ......................................... -55 to 125

1.Stresses above those listed under the "Absolute Maximum

Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

Recommended Operating Conditions

Commercial Devices:
Ambient Temperature (T

) ............................. 0 to +75

Supply voltage (V

)

with Respect to Ground ......................... +3.0 to +3.6V

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 3.3V and T

= 25

COMMERCIAL

Operating Power

= 0V V

= 3.0V Unused Inputs at GND

130

Supply Current

toggle

= 15MHz Outputs Open

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.

MAX.

UNITS

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

Specifications

GAL26CLV12

-7

MIN. MAX.

Input or I/O to Combinational Output

7.5

Clock to Output Delay

3.5

4.5

Clock to Feedback Delay

Setup Time, Input or Feedback before Clock

3.5

5.5

Hold Time, Input or Feedback after Clock

Maximum Clock Frequency with

143

100

MHz

External Feedback, 1/(tsu + tco)

max

Maximum Clock Frequency with

154

117

MHz

Internal Feedback, 1/(tsu + tcf)

Maximum Clock Frequency with

200

142

MHz

No Feedback

Clock Pulse Duration, High

2.5

3.5

Clock Pulse Duration, Low

2.5

3.5

Input or I/O to Output Enabled

7.5

dis

Input or I/O to Output Disabled

7.5

Input or I/O to Asynchronous Reset of Register

arw

Asynchronous Reset Pulse Duration

5.5

arr

Asynchronous Reset to Clock

Recovery Time

spr

Synchronous Preset to Clock

Recovery Time

-5

MIN. MAX.

UNITS

PARAMETER

TEST

COND

DESCRIPTION

SYMBOL

PARAMETER

TYPICAL

UNITS

TEST CONDITIONS

Input Capacitance

= 3.3V, V

= 0V

I/O

I/O Capacitance

= 3.3V, V

I/O

= 0V

1) Refer to Switching Test Conditions section.
2) Minimum values for

pd and

co are not 100% tested but established by characterization.

3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
4) Refer to fmax Descriptions section. Characterized but not 100% tested.

COM

AC Switching Characteristics

Over Recommended Operating Conditions

Capacitance (T

= 25

C, f = 1.0 MHz)

Specifications

GAL26CLV12

Input or I/O to Output Enable/Disable

Registered Output

Combinatorial Output

INPUT or
I/O FEEDBACK

REGISTERED
OUTPUT

CLK

VALID INPUT

s u

c o

(external fdbk)

1 /

m a x

CLK

(w/o fdbk)

w h

w l

1 /

m a x

Clock Width

R E G I S T ER E D
O U T P U T

CLK

arw

arr

INPU T or
I/O F EED B ACK
DRIVI NG AR

max with Feedback

CLK

REGISTERED
FEEDBACK

c f

1 /

m a x ( i n t e r n a l f d b k )

Asynchronous Reset

Synchronous Preset

dis

INPUT or
I/O FEEDBACK

OUTPUT

VALID INPUT

INPUT or
I/O FEEDBACK

COMBINATORIAL
OUTPUT

REGISTERED
OUTPUT

CLK

INPUT or
I/O FEEDBACK
DRIVING SP

spr

Switching Waveforms

Specifications

GAL26CLV12

max with Internal Feedback 1/(

su+

cf)

Note: tcf is a calculated value, derived by subtracting tsu from

the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

max with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

LOGIC
ARRAY

CLK

max with External Feedback 1/(

su+

co)

Note: fmax with external feedback is calculated from measured

tsu and tco.

LOGIC
ARRAY

CLK

su +

CLK

LOGIC
ARRAY

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

1.5ns 10% 90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

See Figure

includes test fixture and probe capacitance.

TEST POINT

= 50

, C

= 35pF*

FROM OUTPUT (O/Q)
UNDER TEST

+1.45V

Output Load Conditions (see figure)

Test Condition

35pF

High Z to Active High at 1.9V

35pF

High Z to Active Low at 1.0V

35pF

Active High to High Z at 1.9V

35pF

Active Low to High Z at 1.0V

35pF

max Descriptions

Switching Test Conditions

Specifications

GAL26CLV12

Electronic Signature

An electronic signature (ES) is provided in every GAL26CLV12D
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is al-
ways available to the user independent of the state of the security
cell.

Security Cell

A security cell is provided in every GAL26CLV12D device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.

Latch-Up Protection

GAL26CLV12D devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of suf-
ficient magnitude to prevent input undershoots from causing the
circuitry to latch.

Device Programming

GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as

part of the programming cycle.

Typical Input Pull-up Characteristic

Input Voltage (V)

t C

r
r
e

t
(

-80

-70

-60

-50

-40

-30

-20

-10

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an il-
legal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.

The GAL26CLV12D device includes circuitry that allows each reg-
istered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If nec-
essary, approved GAL programmers capable of executing test vec-

tors perform output register preload automatically.

Input Buffers

GAL26CLV12D devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.

The input and I/O pins on the GAL26CLV12D also have built-in ac-
tive pull-ups. As a result, floating inputs will float to a TTL high (logic
1). However, Lattice Semiconductor recommends that all unused
inputs and tri-stated I/O pins be connected to an adjacent active
input, Vcc, or ground. Doing so will tend to improve noise immu-
nity and reduce Icc for the device. (See equivalent input and I/O

schematics on the following page.)

Specifications

GAL26CLV12

Typ. Vref = Vcc

Typical Output

Typ. Vref = Vcc

Typical Input

Circuitry within the GAL26CLV12D provides a reset signal to all
registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1

s MAX). As a result,

the state on the registered output pins (if they are enabled) will
be either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-

chronous nature of system power-up, some conditions must be
met to provide a valid power-up reset of the GAL26CLV12D. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.

Vcc

Vref

Tri-State
Control

Active Pull-up Circuit

Feedback
(To Input Buffer)

Feedback

Data
Output

Vcc

Vref

Active Pull-up Circuit

ESD
Protection
Circuit

Vcc

Vcc (min.)

Internal Register
Reset to Logic "0"

Device Pin
Reset to Logic "1"

Device Pin
Reset to Logic "0"

V c c

C L K

INTERNAL REGISTER

Q - OUTPUT

ACTIVE LOW

OUTPUT REGISTER

ACTIVE HIGH

OUTPUT REGISTER

Power-Up Reset

Input/Output Equivalent Schematics

Specifications

GAL26CLV12

Delta Tpd vs # of Outputs

Switching

-0.4

-0.3

-0.2

-0.1

10 11 1 2

Number of Outputs Switching

Delta T

pd (

ns)

RISE
FALL

Delta Tco vs # of Outputs

Switching

-0.5

-0.4

-0.3

-0.2

-0.1

11 1 2

Number of Outputs Switching

Delta T

co (

ns)

RISE
FALL

Delta Tpd vs Output Loading

-8

-4

1 2

1 6

2 0

100

150

200

250

3 00

Output Loading (pF)

Delta T

pd (

ns)

RISE
FALL

Delta Tco vs Output Loading

-4

1 2

1 6

2 0

100

150

200

250

3 00

Output Loading (pF)

Delta T

co (

ns)

RISE
FALL

Normalized Tpd vs Vcc

0.9

0.95

1.05

1.1

3.15

3.3

3.45

3.6

Supply Voltage (V)

Normalized T

RISE
FALL

Normalized Tco vs Vcc

0.9

0.95

1.05

1.1

3.15

3.3

3.45

3.6

Supply Voltage (V)

Normalized T

RISE
FALL

Normalized Tsu vs Vcc

0.8

0.9

1.1

1.2

3.15

3.3

3.45

3.6

Supply Voltage (V)

Normalized Ts

RISE
FALL

Normalized Tpd vs Temp

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

Temperature (deg. C)

Normalized T

RISE
FALL

Normalized Tsu vs Temp

0.8

0.9

1.1

1.2

1.3

-55

-25

1 00

1 25

Temperature (deg. C)

Normalized Ts

RISE
FALL

Normalized Tco vs Temp

0.9

1.1

1.2

-55

-25

2 5

5 0

7 5

100

125

Temperature (deg. C)

Normalized T

RISE
FALL

GAL26CLV12D: Typical AC and DC Characteristic Diagrams

Specifications

GAL26CLV12

Vol vs Iol

0.2

0.4

0.6

0.8

Iol (mA)

Vol (V)

Voh vs Ioh

1.5

2.5

1 0

1 5

Ioh(mA)

Voh (V)

Voh vs Ioh

2.7

2.8

2.9

0.00

1.00

2.00

3.00

4.00

5.00

Ioh(mA)

Voh (V)

Normalized Icc vs Vcc

0.8

0.9

1.1

1.2

3.15

3.3

3.45

3.6

Supply Voltage (V)

Normalized Icc

Normalized Icc vs Temp

0.8

0.9

1.1

1.2

1.3

-55

-25

2 5

5 0

8 8

100

125

Temperature (deg. C)

Normalized Icc

Normalized Icc vs Freq

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1 00

Frequency (MHz)

Normalized Icc

Input Clamp (Vik)

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

Vik (V)

Iik (mA)

Delta Icc vs Vin (1 input)

0.5

1.5

2.5

3.5

4.5

Vin (V)

Delta Icc (mA)

GAL26CLV12D: Typical AC and DC Characteristic Diagrams

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