GAL26CV12
High Performance E
2
CMOS PLD
Generic Array LogicTM
1
Features
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
-- 7.5 ns Maximum Propagation Delay
-- Fmax = 142.8 MHz
-- 4.5ns Maximum from Clock Input to Data Output
-- TTL Compatible 16 mA Outputs
-- UltraMOS
Advanced CMOS Technology
ACTIVE PULL-UPS ON ALL PINS
LOW POWER CMOS
-- 90 mA Typical Icc
E
2
CELL TECHNOLOGY
-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention
TWELVE OUTPUT LOGIC MACROCELLS
-- Uses Standard 22V10 Macrocells
-- Maximum Flexibility for Complex Logic Designs
PRELOAD AND POWER-ON RESET OF REGISTERS
-- 100% Functional Testability
APPLICATIONS INCLUDE:
-- DMA Control
-- State Machine Control
-- High Speed Graphics Processing
-- Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
I
I
I
I
I
I
I
I
I
I
I
PROGRAMMABLE
AND-ARRAY
(122X52)
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
10
OLMC
I/O/Q
12
OLMC
I/O/Q
12
OLMC
I/O/Q
10
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
I/CLK
INPUT
RESET
PRESET
I/O/Q
1
28
14
15
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/O/Q
Vcc
I/CLK
I
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
I/O/Q
I
I
I
I
I
I
I
7
21
I
I
I
VCC
I
I
I
2
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
I/CLK
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
28
4
26
5
7
9
11
12
14
16
18
19
21
23
25
GAL26CV12
Top View
GAL
26CV12
PLCC
DIP
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
June 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
26cv12_03
Description
The GAL26CV12, at 7.5 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E
2
) floating gate technology to provide the highest
performance 28-pin PLD available on the market. E
2
technology
offers high speed (<100ms) erase times, providing the ability to
reprogram or reconfigure the device quickly and efficiently.
Expanding upon the industry standard 22V10 architecture, the
GAL26CV12 eliminates the learning curve typically associated with
using a new device architecture. The generic architecture provides
maximum design flexibility by allowing the Output Logic Macrocell
(OLMC) to be configured by the user. The GAL26CV12 OLMC is
fully compatible with the OLMC in standard bipolar and CMOS
22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and data
retention in excess of 20 years are specified.
Functional Block Diagram
Pin Configuration
Specifications
GAL26CV12
2
)
s
n
(
d
p
T
)
s
n
(
u
s
T
)
s
n
(
o
c
T
)
A
m
(
c
c
I
#
g
n
i
r
e
d
r
O
e
g
a
k
c
a
P
5
.
7
6
5
.
4
0
3
1
P
L
7
-
C
2
1
V
C
6
2
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
8
2
0
3
1
J
L
7
-
C
2
1
V
C
6
2
L
A
G
C
C
L
P
d
a
e
L
-
8
2
0
1
7
7
0
3
1
P
L
0
1
-
B
2
1
V
C
6
2
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
8
2
0
3
1
J
L
0
1
-
B
2
1
V
C
6
2
L
A
G
C
C
L
P
d
a
e
L
-
8
2
5
1
0
1
8
0
3
1
P
L
5
1
-
B
2
1
V
C
6
2
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
8
2
0
3
1
J
L
5
1
-
B
2
1
V
C
6
2
L
A
G
C
C
L
P
d
a
e
L
-
8
2
0
2
2
1
2
1
0
3
1
P
L
0
2
-
B
2
1
V
C
6
2
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
8
2
0
3
1
J
L
0
2
-
B
2
1
V
C
6
2
L
A
G
C
C
L
P
d
a
e
L
-
8
2
)
s
n
(
d
p
T
)
s
n
(
u
s
T
)
s
n
(
o
c
T
)
A
m
(
c
c
I
#
g
n
i
r
e
d
r
O
e
g
a
k
c
a
P
0
1
7
7
0
5
1
I
P
L
0
1
-
C
2
1
V
C
6
2
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
8
2
0
5
1
I
J
L
0
1
-
C
2
1
V
C
6
2
L
A
G
C
C
L
P
d
a
e
L
-
8
2
5
1
0
1
8
0
5
1
I
P
L
5
1
-
B
2
1
V
C
6
2
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
8
2
0
5
1
I
J
L
5
1
-
B
2
1
V
C
6
2
L
A
G
C
C
L
P
d
a
e
L
-
8
2
0
2
2
1
2
1
0
5
1
I
P
L
0
2
-
B
2
1
V
C
6
2
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
8
2
0
5
1
I
J
L
0
2
-
B
2
1
V
C
6
2
L
A
G
C
C
L
P
d
a
e
L
-
8
2
Industrial Grade Specifications
Blank = Commercial
I = Industrial
Grade
Package
Power
L = Low Power
Speed (ns)
XXXXXXXX
XX
X
X X
Device Name
_
P = Plastic DIP
J = PLCC
GAL26CV12C
GAL26CV12B
GAL26CV12 Ordering Information
Commercial Grade Specifications
Part Number Description
Specifications
GAL26CV12
3
GAL26CV12 OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the GAL26CV12 has two primary
functional modes: registered, and combinatorial I/O. The modes
and the output polarity are set by two bits (SO and S1), which are
normally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC's D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an
individual product term for each OLMC, and can therefore be
defined by a logic equation. The D flip-flop's /Q output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.
The GAL26CV12 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registered outputs to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers
to a logic one on the rising edge of the next clock pulse after this
product term is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
The GAL26CV12 has a variable number of product terms per
OLMC. Of the twelve available OLMCs, two OLMCs have access
to twelve product terms (pins 20 and 22), two have access to ten
product terms (pins 19 and 23), and the other eight OLMCs have
eight product terms each. In addition to the product terms available
for logic, each OLMC has an additional product term dedicated to
output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
A R
S P
D
Q
Q
C L K
4 T O 1
M U X
2 T O 1
M U X
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Output
tri-state control is available as an individual product term for each
output, and may be individually set by the compiler as either "on"
(dedicated output), "off" (dedicated input), or "product term driven"
(dynamic I/O). Feedback into the AND array is from the pin side of
the output enable buffer. Both polarities (true and inverted) of the
pin are fed back into the AND array.
Output Logic Macrocell (OLMC)
Output Logic Macrocell Configurations
Specifications
GAL26CV12
4
ACTIVE HIGH
ACTIVE LOW
ACTIVE HIGH
ACTIVE LOW
S
0
= 1
S
1
= 1
S
0
= 0
S
1
= 1
S
0
= 0
S
1
= 0
S
0
= 1
S
1
= 0
A R
S P
D
Q
Q
C L K
A R
S P
D
Q
Q
C L K
Registered Mode
Combinatorial Mode
Specifications
GAL26CV12
5
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0
4
8
12
16
20
24
28
32
36
40
44
48
1
0052
.
.
.
0468
2
27
28
OLMC
S0
6344
S1
6345
26
25
24
23
22
20
19
18
17
16
15
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
14
13
12
11
10
OLMC
S0
6346
S1
6347
OLMC
S0
6348
S1
6349
OLMC
S0
6350
S1
6351
OLMC
S0
6352
S1
6353
OLMC
S0
6354
S1
6355
OLMC
S0
6356
S1
6357
OLMC
S0
6358
S1
6359
OLMC
S0
6360
S1
6361
OLMC
S0
6362
S1
6363
OLMC
S0
6364
S1
6365
OLMC
S0
6366
S1
6367
0000
0520
.
.
.
0936
0988
.
.
.
1404
1456
.
.
.
1872
1924
.
.
.
.
2444
3848
.
.
.
.
4368
2496
.
.
.
.
.
3120
3172
.
.
.
.
.
3796
4420
.
.
.
4836
4888
.
.
.
5304
5356
.
.
.
5772
5824
.
.
.
6240
6292
3
4
5
6
8
9
Electronic Signature
6368, 6369 ...
... 6430, 6431
L
S
B
M
S
B
Byte 7 Byte 6 Byte 5 Byte 4
Byte 2 Byte 1 Byte 0
Byte 3
8
8
8
8
10
12
12
10
8
8
8
8
GAL26CV12 Logic Diagram/JEDEC Fuse Map
DIP & PLCC Package Pinouts
Specifications
GAL26CV12
6
Specifications
GAL26CV12C
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (T
A
) ............................. 0 to +75
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient Temperature (T
A
) ........................... 40 to 85
C
Supply voltage (V
CC
)
with Respect to Ground ......................... +4.5 to +5.5V
Absolute Maximum Ratings
(1)
Supply voltage V
CC
...................................... 0.5 to +7V
Input voltage applied .......................... 2.5 to V
CC
+1.0V
Off-state output voltage applied ......... 2.5 to V
CC
+1.0V
Storage Temperature ................................ 65 to 150
C
Ambient Temperature with
Power Applied ........................................... 55 to 125
C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the op-
erational sections of this specification is not implied (while pro-
gramming, follow the programming specifications).
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
3
MAX.
UNITS
V
IL
Input Low Voltage
Vss 0.5
--
0.8
V
V
IH
Input High Voltage
2.0
--
Vcc+1
V
I
IL
1
Input or I/O Low Leakage Current
0V
V
IN
V
IL
(MAX.)
--
--
100
A
I
IH
Input or I/O High Leakage Current
3.5V
V
IN
V
CC
--
--
10
A
V
OL
Output Low Voltage
I
OL
= MAX. Vin = V
IL
or V
IH
--
--
0.5
V
V
OH
Output High Voltage
I
OH
= MAX. Vin = V
IL
or V
IH
2.4
--
--
V
I
OL
Low Level Output Current
--
--
16
mA
I
OH
High Level Output Current
--
--
3.2
mA
I
OS
2
Output Short Circuit Current
V
CC
= 5V
V
OUT
= 0.5V T
A
= 25
C
30
--
130
mA
COMMERCIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V f
toggle
= 15MHz
L-7
--
90
130
mA
Supply Current
Outputs Open
INDUSTRIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V f
toggle
= 15MHz
L-10
--
90
150
mA
Supply Current
Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and T
A
= 25
C.
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
Specifications
GAL26CV12
7
Specifications
GAL26CV12C
t
pd
A
Input or I/O to Comb. Output
1
7.5
1
10
ns
t
co
A
Clock to Output Delay
1
4.5
1
7
ns
t
cf
2
--
Clock to Feedback Delay
--
2.5
--
2.5
ns
t
su
1
--
Setup Time, Input or Fdbk before Clk
6
--
7
--
ns
t
su
2
--
Setup Time, SP before Clock
6
--
7
--
ns
t
h
--
Hold Time, Input or Fdbk after Clk
0
--
0
--
ns
A
Maximum Clock Frequency with
95.2
--
71.4
--
MHz
External Feedback, 1/(tsu + tco)
f
max
3
A
Maximum Clock Frequency with
117.6
--
105
--
MHz
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
142.8
--
105
--
MHz
No Feedback
t
wh
--
Clock Pulse Duration, High
3.5
--
4
--
ns
t
wl
--
Clock Pulse Duration, Low
3.5
--
4
--
ns
t
en
B
Input or I/O to Output Enabled
1
7.5
1
10
ns
t
dis
C
Input or I/O to Output Disabled
1
7.5
1
9
ns
t
ar
A
Input or I/O to Asynch. Reset of Reg.
1
9
1
13
ns
t
arw
--
Asynchronous Reset Pulse Duration
7
--
8
--
ns
t
arr
--
Asynch. Reset to Clk
Recovery Time
5
--
8
--
ns
t
spr
--
Synch. Preset to Clk
Recovery Time
5
--
10
--
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
PARAM
UNITS
-10
MIN. MAX.
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 5.0V, V
I
= 2.0V
C
I/O
I/O Capacitance
8
pF
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested.
IND
COM
-7
MIN.
MAX.
TEST
COND.
1
DESCRIPTION
AC Switching Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
Capacitance (T
A
= 25
C, f = 1.0 MHz)
Specifications
GAL26CV12
8
Specifications
GAL26CV12B
COMMERCIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V f
toggle
= 15MHz
L-10/-15/-20
--
90
130
mA
Supply Current
Outputs Open
INDUSTRIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V f
toggle
= 15MHz
L-15/-20
--
90
150
mA
Supply Current
Outputs Open
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (T
A
) ............................. 0 to +75
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient Temperature (T
A
) ........................... 40 to 85
C
Supply voltage (V
CC
)
with Respect to Ground ......................... +4.5 to +5.5V
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
3
MAX.
UNITS
V
IL
Input Low Voltage
Vss 0.5
--
0.8
V
V
IH
Input High Voltage
2.0
--
Vcc+1
V
I
IL
1
Input or I/O Low Leakage Current
0V
V
IN
V
IL
(MAX.)
--
--
100
A
I
IH
Input or I/O High Leakage Current
3.5V
V
IN
V
CC
--
--
10
A
V
OL
Output Low Voltage
I
OL
= MAX. Vin = V
IL
or V
IH
--
--
0.5
V
V
OH
Output High Voltage
I
OH
= MAX. Vin = V
IL
or V
IH
2.4
--
--
V
I
OL
Low Level Output Current
--
--
16
mA
I
OH
High Level Output Current
--
--
3.2
mA
I
OS
2
Output Short Circuit Current
V
CC
= 5V
V
OUT
= 0.5V T
A
= 25
C
30
--
130
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and T
A
= 25
C.
Absolute Maximum Ratings
(1)
Supply voltage V
CC
...................................... 0.5 to +7V
Input voltage applied .......................... 2.5 to V
CC
+1.0V
Off-state output voltage applied ......... 2.5 to V
CC
+1.0V
Storage Temperature ................................ 65 to 150
C
Ambient Temperature with
Power Applied ........................................... 55 to 125
C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the op-
erational sections of this specification is not implied (while pro-
gramming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
Specifications
GAL26CV12
9
Specifications
GAL26CV12B
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
t
pd
A
Input or I/O to Combinatorial Output
3
10
3
15
3
20
ns
t
co
A
Clock to Output Delay
2
7
2
8
2
12
ns
t
cf
2
--
Clock to Feedback Delay
--
2.5
--
2.5
--
10
ns
t
su
1
--
Setup Time, Input or Feedback before Clock
7
--
10
--
12
--
ns
t
su
2
--
Setup Time, SP before Clock
10
--
10
--
12
--
ns
t
h
--
Hold Time, Input or Feedback after Clock
0
--
0
--
0
--
ns
A
Maximum Clock Frequency with
71.4
--
55.5
--
41.6
--
MHz
External Feedback, 1/(tsu + tco)
f
max
3
A
Maximum Clock Frequency with
105
--
80
--
45.4
--
MHz
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
105
--
83.3
--
62.5
--
MHz
No Feedback
t
wh
--
Clock Pulse Duration, High
4
--
6
--
8
--
ns
t
wl
--
Clock Pulse Duration, Low
4
--
6
--
8
--
ns
t
en
B
Input or I/O to Output Enabled
3
10
3
15
3
20
ns
t
dis
C
Input or I/O to Output Disabled
3
10
3
15
3
20
ns
t
ar
A
Input or I/O to Asynchronous Reset of Register
3
13
3
20
3
25
ns
t
arw
--
Asynchronous Reset Pulse Duration
8
--
10
--
15
--
ns
t
arr
--
Asynchronous Reset to Clock
Recovery Time
8
--
10
--
15
--
ns
t
spr
--
Synchronous Preset to Clock
Recovery Time
10
--
10
--
12
--
ns
PARAMETER
UNITS
TEST
COND.
1
DESCRIPTION
-20
MIN. MAX.
-15
MIN. MAX.
-10
MIN. MAX.
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 5.0V, V
I
= 2.0V
C
I/O
I/O Capacitance
8
pF
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested.
COM / IND
COM
COM / IND
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (T
A
= 25
C, f = 1.0 MHz)
Specifications
GAL26CV12
10
Input or I/O to Output Enable/Disable
Registered Output
Combinatorial Output
VALID INPUT
INPUT or
I/O FEEDBACK
t
pd
COMBINATORIAL
OUTPUT
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
t
s u
t
c o
t
h
(external fdbk)
1 /
f
m a x
t
en
t
dis
INPUT or
I/O FEEDBACK
OUTPUT
CLK
(w/o fdbk)
t
w h
t
w l
1 /
f
m a x
Clock Width
REGISTERED
OUTPUT
CLK
INPUT or
I/O FEEDBACK
DRIVING SP
t
su
t
h
t
co
t
spr
R E G I S T ER E D
O U T P U T
CLK
t
arw
t
ar
t
arr
INPU T or
I/O F EED B ACK
DRIVI NG AR
f
max with Feedback
CLK
REGISTERED
FEEDBACK
t
cf
t
su
1/
f
max (internal fdbk)
Synchronous Preset
Asynchronous Reset
Switching Waveforms
Specifications
GAL26CV12
11
f
max with Internal Feedback 1/(
t
su+
t
cf)
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
f
max with External Feedback 1/(
t
su+
t
co)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
f
max with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
GAL26CV12 Output Load Conditions (see figure)
Test Condition
R
1
R
2
C
L
A
300
390
50pF
B
Active High
390
50pF
Active Low
300
390
50pF
C
Active High
390
5pF
Active Low
300
390
5pF
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
R E G I S T E R
L O G I C
A R R A Y
t
c o
t
s u
C L K
Input Pulse Levels
GND to 3.0V
Input Rise and
C-7/-10/-15
1.5ns 10% 90%
Fall Times
B-10/-15/-20
3ns 10% 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
REGISTER
LOGIC
ARRAY
CLK
t
su +
t
h
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
f
max Definitions
Switching Test Conditions
Specifications
GAL26CV12
12
Electronic Signature
An electronic signature is provided in every GAL26CV12 device.
It contains 64 bits of reprogrammable memory that can contain
user-defined data. Some uses include user ID codes, revision
numbers, or inventory control. The signature data is always avail-
able to the user independent of the state of the security cell.
Security Cell
A security cell is provided in every GAL26CV12 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.
Latch-Up Protection
GAL26CV12 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential for latch-up caused by negative input undershoots. Ad-
ditionally, outputs are designed with n-channel pull-ups instead of
the traditional p-channel pull-ups in order to eliminate latch-up due
to output overshoots.
Device Programming
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
part of the programming cycle.
Typical Input Current
1 . 0
2 . 0
3 . 0
4 . 0
5 . 0
- 6 0
0
- 2 0
- 4 0
0
In p u t V o lt ag e ( V o lt s)
I
nput
C
u
r
r
e
nt
(
u
A
)
Output Register Preload
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in normal machine operation. This is because certain events may
occur during system operation that throw the logic into an illegal
state (power-up, line voltage glitches, brown-outs, etc.). To test a
design for proper treatment of these conditions, a way must be
provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
The GAL26CV12 device includes circuitry that allows each regis-
tered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If nec-
essary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
Input Buffers
GAL26CV12 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
logic.
The input and I/O pins also have built-in active pull-ups. As a result,
floating inputs will float to a TTL high (logic 1). However, Lattice
Semiconductor recommends that all unused inputs and tri-stated
I/O pins be connected to an adjacent active input, Vcc, or ground.
Doing so will tend to improve noise immunity and reduce Icc for the
device.
Specifications
GAL26CV12
13
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Typical Input
Typical Output
(Vref Typical = 3.2V)
(Vref Typical = 3.2V)
provide a valid power-up reset of the device. First, the V
CC
rise must
be monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
Circuitry within the GAL26CV12 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1
s MAX). As a result, the state
on the registered output pins (if they are enabled) will be either high
or low on power-up, depending on the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. Because of the asynchro-
nous nature of system power-up, some conditions must be met to
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Device Pin
Reset to Logic "0"
V c c
C L K
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Power-Up Reset
Input/Output Equivalent Schematics
Specifications
GAL26CV12
14
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-1
-0.75
-0.5
-0.25
0
1
2
3
4
5
6
7
8
9
10 11 12
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-1
-0.75
-0.5
-0.25
0
1
2
3
4
5
6
7
8
9
10 11 12
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
GAL26CV12C: Typical AC and DC Characteristic Diagrams
Specifications
GAL26CV12
15
Vol vs Iol
Iol (mA)
Vol (V)
0
0.5
1
1.5
2
2.5
3
0.00
20.00
40.00
60.00
80.00
100.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00
10.00
20.00
30.00
40.00
50.00
60.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3
3.25
3.5
3.75
4
0.00
1.00
2.00
3.00
4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.7
0.8
0.9
1
1.1
1.2
1.3
4.50
4.75
5.00
5.25
5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
0
25
50
75
100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
2
4
6
8
10
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
10
20
30
40
50
60
-2.00
-1.50
-1.00
-0.50
0.00
GAL26CV12C: Typical AC and DC Characteristic Diagrams
Specifications
GAL26CV12
16
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
9
10 11 12
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
9
10 11 12
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
GAL26CV12B: Typical AC and DC Characteristic Diagrams
Specifications
GAL26CV12
17
Vol vs Iol
Iol (mA)
Vol (V)
0
0.5
1
1.5
2
2.5
3
0.00
20.00
40.00
60.00
80.00
100.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00
10.00
20.00
30.00
40.00
50.00
60.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3.5
3.75
4
4.25
4.5
0.00
1.00
2.00
3.00
4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
0
25
50
75
100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
2
4
6
8
10
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
10
20
30
40
50
60
70
80
90
100
-2.00
-1.50
-1.00
-0.50
0.00
GAL26CV12B: Typical AC and DC Characteristic Diagrams
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