GAL6001
High Performance E
2
CMOS
FPLA
Generic Array LogicTM
1
Description
Using a high performance E
2
CMOS technology, Lattice
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers a high degree of functional integration and flexibility in a 24-
pin, 300-mil package.
The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Advanced features that simplify programming and reduce test time,
coupled with E
2
CMOS reprogrammable cells, enable 100% AC, DC,
programmability, and functionality testing of each GAL6001 during
manufacture. As a result, Lattice Semiconductor delivers 100% field
programmability and functionality of all GAL products. In addition,
100 erase/write cycles and data retention in excess of 20 years are
specified.
1
12
13
24
I/ICLK
I
I
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OCLK
I/O/Q
I/O/Q
6
18
2
28
NC
I/ICLK
I
I
I
I
I
I
I
NC
NC
NC
GND
I
I
OCLK
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I
I/O/Q
I/O/Q
4
5
7
9
11
12
14
16
18
19
21
23
25
26
Features
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
-- 30ns Maximum Propagation Delay
-- 27MHz Maximum Frequency
-- 12ns Maximum Clock to Output Delay
-- TTL Compatible 16mA Outputs
-- UltraMOS
Advanced CMOS Technology
LOW POWER CMOS
-- 90mA Typical Icc
E
2
CELL TECHNOLOGY
-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention
UNPRECEDENTED FUNCTIONAL DENSITY
-- 78 x 64 x 36 FPLA Architecture
-- 10 Output Logic Macrocells
-- 8 Buried Logic Macrocells
-- 20 Input and I/O Logic Macrocells
HIGH-LEVEL DESIGN FLEXIBILITY
-- Asynchronous or Synchronous Clocking
-- Separate State Register and Input Clock Pins
-- Functional Superset of Existing 24-pin PAL
and FPLA Devices
APPLICATIONS INCLUDE:
-- Sequencers
-- State Machine Control
-- Multiple PLD Device Integration
GAL6001
Top View
PLCC
DIP
GAL
6001
OUTPUT
ENABLE
AND
OR
D
11
2
INPUT
CLOCK
ICLK
14
23
IOLMC
ILMC
OLMC
E
RESET
OUTPUTS
14 - 23
14
23
0
7
BLMC
D
E
OUTPUT
CLOCK
OCLK
{
INPUTS
2-11
{
Copyright 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
July 1997
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
6001_02
Functional Block Diagram
Macrocell Names
ILMC
INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
BLMC
BURIED LOGIC MACROCELL
OLMC
OUTPUT LOGIC MACROCELL
I
0
- I
10
INPUT
I/O/Q
BIDIRECTIONAL
ICLK
INPUT CLOCK
V
CC
POWER (+5)
OCLK
OUTPUT CLOCK
GND
GROUND
Pin Names
Pin Configuration
Specifications
GAL6001
2
)
s
n
(
d
p
T
)
z
H
M
(
x
a
m
F
)
A
m
(
c
c
I
#
g
n
i
r
e
d
r
O
e
g
a
k
c
a
P
0
3
7
2
0
5
1
P
L
0
3
-
B
1
0
0
6
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
4
2
0
5
1
J
L
0
3
-
B
1
0
0
6
L
A
G
C
C
L
P
d
a
e
L
-
8
2
Blank = Commercial
Grade
Package
Power
L = Low Power
Speed (ns)
XXXXXXXX
XX
X
X X
Device Name
_
P = Plastic DIP
J = PLCC
GAL6001B
GAL6001 Ordering Information
Commercial Grade Specifications
Part Number Description
Specifications
GAL6001
3
The GAL6001 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
IOLMC to the I/O pins (14-23). Each input section is configurable
as a block for asynchronous, latched, or registered inputs. Pin 1
(ICLK) is used as an enable input for latched macrocells or as a
clock input for registered macrocells. Configurable input blocks
provide system designers with unparalleled design flexibility. With
the GAL6001, external registers and latches are not necessary.
Both the ILMC and the IOLMC are block configurable. However,
the ILMC can be configured independently of the IOLMC. The three
valid macrocell configurations are shown in the macrocell equivalent
diagrams on the following pages.
The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are called
the Buried Logic Macrocells (BLMC), and are useful for building
state machines. The second group of macrocells consists of 10
cells whose outputs, in addition to feeding back into the AND ar-
ray, are available at the device pins. Cells in this group are known
as Output Logic Macrocells (OLMC).
The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinatorial, D-type
register with sum term (asynchronous) clock, or D/E-type register.
Output macrocells always have I/O capability, with directional control
provided by the 10 output enable (OE) product terms. Additionally,
the polarity of each OLMC output is selected through the "D" XOR.
Polarity selection is available for BLMCs, since both the true and
complemented forms of their outputs are available in the AND array.
Polarity of all "E" sum terms is selected through the "E" XOR.
When the macrocell is configured as a D/E type register, it is clocked
from the common OCLK and the register clock enable input is con-
trolled by the associated "E" sum term. This configuration is useful
for building counters and state-machines with state hold functions.
When the macrocell is configured as a D-type register with a sum
term clock, the register is always enabled and its "E" sum term is
routed directly to the clock input. This permits asynchronous pro-
grammable clocking, selected on a register-by-register basis.
Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. Registers are reset
to a logic zero. If connected to an output pin, a logic one will oc-
cur because of the inverting output buffer.
There are two possible feedback paths from each OLMC. The first
path is directly from the OLMC (this feedback is before the output
buffer and always present). When the OLMC is used as an out-
put, the second feedback path is through the IOLMC. With this dual
feedback arrangement, the OLMC can be permanently buried (the
associated OLMC pin is an input), or dynamically buried with the
use of the output enable product term.
The D/E registers used in this device offer the designer the ultimate
in flexibility and utility. The D/E register architecture can emulate
RS-, JK-, and T-type registers with the same efficiency as a dedi-
cated RS-, JK-, or T-register.
The three macrocell configurations are shown in the macrocell
equivalent diagrams on the following pages.
Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)
Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)
Specifications
GAL6001
4
ILMC/IOLMC
Generic Logic Block Diagram
IOLMC (I/O Logic Macrocell)
JEDEC Fuse Numbers
ISYN
LATCH
8220
8221
ILMC (Input Logic Macrocell)
JEDEC Fuse Numbers
ISYN
LATCH
8218
8219
MUX
INVALID
LATCH
REG.
D
Q
E
D
Q
ICLK
0 0
0 1
1 0
1 1
AND
ARRAY
INPUT
or I/O
10
10
LATCH
ISYN
ILMC and IOLMC Configurations
Specifications
GAL6001
5
OLMC/BLMC
Generic Logic Block Diagram
BLMC (Buried Logic Macrocell)
JEDEC Fuse Numbers
BLMC
OCLK
OSYN
XORE
7
8175
8176
8177
6
8172
8173
8174
5
8169
8170
8171
4
8166
8167
8168
3
8163
8164
8165
2
8160
8161
8162
1
8157
8158
8159
0
8154
8155
8156
OLMC (Output Logic Macrocell)
JEDEC Fuse Numbers
OLMC
OCLK
OSYN
XORE
XORD
0
8178
8179
8180
8181
1
8182
8183
8184
8185
2
8186
8187
8188
8189
3
8190
8191
8192
8193
4
8194
8195
8196
8197
5
8198
8199
8200
8201
6
8202
8203
8204
8205
7
8206
8207
8208
8209
8
8210
8211
8212
8213
9
8214
8215
8216
8217
D
Q
E
OSYN(i)
MUX
0
1
R
MUX
0
1
CKS(i)
Vcc
MUX
0
1
RESET
IOLMC
I/O
AND
ARRAY
OE
PRODUCT
TERM
OCLK
D
E
OLMC ONLY
OLMC ONLY
XORD(i)
XORE(i)
OLMC and BLMC Configurations
Specifications
GAL6001
6
OL
M
C
0
OL
M
C
1
OL
M
C
2
OL
M
C
3
OL
M
C
4
OL
M
C
5
OL
M
C
6
OL
M
C
7
OL
M
C
8
OL
M
C
9
ICL
K
BL
M
C
0
BL
M
C
7
BL
M
C
6
BL
M
C
5
BL
M
C
4
BL
M
C
1
BL
M
C
2
BL
M
C
3
1(2)
2(
3)
3(4)
4(5)
5(
6)
6(7)
7(
9
)
8(1
0
)
9(1
1
)
10(
12)
11(13)
MU X
LTC H.
R EG.
MUX
LTCH.
REG.
IO
L
M
C
9
IOL
M
C
8
IOL
M
C
7
IO
L
M
C
6
IOL
M
C
5
IOL
M
C
4
IO
L
M
C
3
IO
L
M
C
2
IO
L
M
C
1
IO
L
M
C
0
GAL6001 Logic Diagram
Specifications
GAL6001
7
XO
RD
XO
RE
0
1
D
E
R
Q
01
1
0
XO
RD
XO
RE
0
1
D
E
R
Q
01
1
0
XO
RD
XO
RE
0
1
D
E
R
Q
01
1
0
XO
RD
XO
RE
0
1
D
E
R
Q
01
1
0
XO
RD
XO
RE
0
1
D
E
R
Q
01
1
0
XO
RD
XO
RE
0
1
D
E
R
Q
01
1
0
XO
R
D
XO
R
E
0
1
D
E
R
Q
01
1
0
XO
R
D
XO
R
E
0
1
D
E
R
Q
01
1
0
XO
R
D
XO
R
E
0
1
D
E
R
Q
01
1
0
XO
RD
XO
RE
0
1
D
E
R
Q
01
1
0
XO
R
E
0
1
D
E
R
Q
0
1
1
0
XO
R
E
0
1
D
E
R
Q
0
1
1
0
XO
RE
0
1
D
E
R
Q
0
1
1
0
XO
RE
0
1
D
E
R
Q
0
1
1
0
XO
RE
0
1
D
E
R
Q
0
1
1
0
XO
RE
0
1
D
E
R
Q
0
1
1
0
XO
RE
0
1
D
E
R
Q
0
1
1
0
XO
RE
0
1
D
E
R
Q
0
1
1
0
23
(
2
7
)
13(
1
6)
14
(
1
7)
15
(
1
8)
16(
1
9)
17(
2
0)
18(
2
1)
19(
2
3)
20(
2
4)
21(
2
5)
22
(
2
6)
BL
M
C
0
BL
M
C
1
BL
M
C
2
BL
M
C
3
BL
M
C
4
BL
M
C
5
BL
M
C
6
BL
M
C
7
OL
M
C
9
OL
M
C
8
OL
M
C
7
OL
M
C
6
OL
M
C
5
OL
M
C
4
OL
M
C
3
OL
M
C
2
OL
M
C
1
OL
M
C
0
R
ESET
OC
L
K
The number of Differential Product Terms that may
switch is limited to a maximum of 15. Refer to the
Differential Product Term Switching Applications sec-
tion of this data sheet for a full explanation.
GAL6001 Logic Diagram (Continued)
Specifications
GAL6001
8
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
2
MAX.
UNITS
V
IL
Input Low Voltage
Vss 0.5
--
0.8
V
V
IH
Input High Voltage
2.0
--
Vcc+1
V
I
IL
Input or I/O Low Leakage Current
0V
V
IN
V
IL
(MAX.)
--
--
-10
A
I
IH
Input or I/O High Leakage Current
3.5V
IH
V
IN
V
CC
--
--
10
A
V
OL
Output Low Voltage
I
OL
= MAX. Vin = V
IL
or V
IH
--
--
0.5
V
V
OH
Output High Voltage
I
OH
= MAX. Vin = V
IL
or V
IH
2.4
--
--
V
I
OL
Low Level Output Current
--
--
16
mA
I
OH
High Level Output Current
--
--
3.2
mA
I
OS
1
Output Short Circuit Current
V
CC
= 5V
V
OUT
= 0.5V
30
--
130
mA
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (T
A
) ............................... 0 to 75
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.75 to +5.25V
Absolute Maximum Ratings
(1)
Supply voltage V
CC
...................................... 0.5 to +7V
Input voltage applied .......................... 2.5 to V
CC
+1.0V
Off-state output voltage applied ......... 2.5 to V
CC
+1.0V
Storage Temperature ................................ 65 to 150
C
Ambient Temperature with
Power Applied ........................................ 55 to 125
C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
COMMERCIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V
L -30
--
90
150
mA
Supply Current
f
toggle
= 15MHz Outputs Open
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
2) Typical values are at Vcc = 5V and T
A
= 25
C
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 5.0V, V
I
= 2.0V
C
I/O
I/O Capacitance
10
pF
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested.
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
Capacitance (T
A
= 25
C, f = 1.0 MHz)
Specifications
GAL6001
9
t
pd1
A
Combinatorial Input to Combinatorial Output
--
30
ns
t
pd2
A
Feedback or I/O to Combinatorial Output
--
30
ns
t
pd3
A
Transparent Latch Input to Combinatorial Output
--
35
ns
t
co1
A
Input Latch ICLK to Combinatorial Output Delay
--
35
ns
t
co2
A
Input Reg. ICLK to Combinatorial Output Delay
--
35
ns
t
co3
A
Output D/E Reg. OCLK to Output Delay
--
12
ns
t
co4
A
Output D Reg. Sum Term CLK to Output Delay
--
35
ns
t
su1
--
Setup Time, Input before Input Latch ICLK
2.5
--
ns
t
su2
--
Setup Time, Input before Input Reg. ICLK
2.5
--
ns
t
su3
--
Setup Time, Input or Feedback before D/E Reg. OCLK
25
--
ns
t
su4
--
Setup Time, Input or Feedback before D Reg. Sum Term CLK
7.5
--
ns
t
su5
--
Setup Time, Input Reg. ICLK before D/E Reg. OCLK
30
--
ns
t
su6
--
Setup Time, Input Reg. ICLK before D Reg. Sum Term CLK
15
--
ns
t
h1
--
Hold Time, Input after Input Latch ICLK
5
--
ns
t
h2
--
Hold Time, Input after Input Reg. ICLK
5
--
ns
t
h3
--
Hold Time, Input or Feedback after D/E Reg. OCLK
0
--
ns
t
h4
--
Hold Time, Input or Feedback after D Reg. Sum Term CLK
10
--
ns
f
max
--
Maximum Clock Frequency, OCLK
27
--
MHz
t
wh1
--
ICLK or OCLK Pulse Duration, High
10
--
ns
t
wh2
--
Sum Term CLK Pulse Duration, High
15
--
ns
t
wl1
--
ICLK or OCLK Pulse Duration, Low
10
--
ns
t
wl2
--
Sum Term CLK Pulse Duration, Low
15
--
ns
t
arw
--
Reset Pulse Duration
15
--
ns
t
en
B
Input or I/O to Output Enabled
--
25
ns
t
dis
C
Input or I/O to Output Disabled
--
25
ns
t
ar
A
Input or I/O to Asynchronous Reg. Reset
--
35
ns
t
arr1
--
Asynchronous Reset to OCLK Recovery Time
20
--
ns
t
arr2
--
Asynchronous Reset to Sum Term CLK Recovery Time
10
--
ns
UNITS
PARAMETER
TEST
COND
1
.
DESCRIPTION
1) Refer to Switching Test Conditions section.
-30
MIN. MAX.
COM
AC Switching Characteristics
Over Recommended Operating Conditions
Specifications
GAL6001
10
Registered Output (OCLK)
Clock Width
Asynchronous Reset
Input or I/O to Output Enable/Disable
Registered Output (Sum Term CLK)
Combinatorial Output
Latched Input
INPUT or
I/O FEEDBACK
VALID INPUT
COMBINATORIAL
OUTPUT
ICLK (LATCH)
t
su1
t
h1
t
co1
t
pd3
INPUT or
I/O FEEDBACK
VALID INPUT
REGISTERED
OUTPUT
Sum Term CLK
t
su4
t
h4
t
co4
ICLK or
OCLK
Sum Term CLK
t
wh1
t
wl1
t
wl2
t
wh2
t
en
t
dis
INPUT or
I/O FEEDBACK
OUTPUT
REGISTERED
OUTPUT
t
arw
t
ar
INPUT or
I/O FEEDBACK
DRIVING AR
OCLK
Sum Term CLK
t
arr2
t
arr1
INPUT or
I/O FEEDBACK
VALID INPUT
REGISTERED
OUTPUT
OCLK
1/
f
max
t
su3
t
h3
t
co3
INPUT or
I/O FEEDBACK
VALID INPUT
COMBINATORIAL
OUTPUT
ICLK (REGISTER)
OCLK
Sum Term CLK
t
su2
t
h2
t
co2
t
su5
t
su6
Registered Input
VALID INPUT
COMBINATORIAL
OUTPUT
t
pd1,2
INPUT or
I/O FEEDBACK
Switching Waveforms
Specifications
GAL6001
11
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns 10% 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition
R
1
R
2
C
L
A
300
390
50pF
B
Active High
390
50pF
Active Low
300
390
50pF
C
Active High
390
5pF
Active Low
300
390
5pF
f
max with External Feedback 1/(
t
su+
t
co)
Note: fmax with external feedback is calculated from measured
tsu and tco.
f
max with Internal Feedback 1/(
t
su+
t
cf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
f
max with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
REGISTER
LOGIC
ARRAY
CLK
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
fmax Descriptions
Switching Test Conditions
Specifications
GAL6001
12
Array Description
The GAL6001 contains two E
2
reprogrammable arrays. The first
is an AND array and the second is an OR array. These arrays are
described in detail below.
AND ARRAY
The AND array is organized as 78 inputs by 75 product term out-
puts. The 10 ILMCs, 10 IOLMCs, 8 BLMC feedbacks, 10 OLMC
feedbacks, and ICLK comprise the 39 inputs to this array (each
available in true and complement forms). 64 product terms serve
as inputs to the OR array. The RESET product term generates the
RESET signal described in the Output and Buried Logic Macrocells
section. There are 10 output enable product terms which allow
device pins 14-23 to be bi-directional or tri-state.
OR ARRAY
The OR array is organized as 64 inputs by 36 sum term outputs.
64 product terms from the AND array serve as the inputs to the OR
array. Of the 36 sum term outputs, 18 are data ("D") terms and 18
are enable/clock ("E") terms. These terms feed into the 10 OLMCs
and 8 BLMCs, one "D" term and one "E" term to each.
The programmable OR array offers unparalleled versatility in prod-
uct term usage. This programmability allows from 1 to 64 product
terms to be connected to a single sum term. A programmable OR
array is more flexible than a fixed, shared, or variable product term
architecture.
Electronic Signature
An electronic signature (ES) is provided in every GAL6001 device.
It contains 72 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
NOTE: The ES is included in checksum calculations. Changing the
ES will alter the checksum.
Security Cell
A security cell is provided in every GAL6001 device as a deterrent
to unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the AND and OR arrays.
This cell can be erased only during a bulk erase cycle, so the origi-
nal configuration can never be examined once this cell is pro-
grammed. The Electronic Signature is always available to the user,
regardless of the state of this control cell.
Bulk Erase
Before writing a new pattern into a previously programmed part,
the old pattern must first be erased. This erasure is done automati-
cally by the programming hardware as part of the programming
cycle and takes only 50 milliseconds.
Register Preload
When testing state machine designs, all possible states and state
transitions must be verified, not just those required during normal
operations. This is because in system operation, certain events
may occur that cause the logic to assume an illegal state: power-
up, brown out, line voltage glitches, etc. To test a design for proper
treatment of these conditions, a method must be provided to break
the feedback paths and force any desired state (i.e., illegal) into the
registers. Then the machine can be sequenced and the outputs
tested for correct next state generation.
All of the registers in the GAL6001 can be preloaded, including the
ILMC, IOLMC, OLMC, and BLMC registers. In addition, the con-
tents of the state and output registers can be examined in a special
diagnostics mode. Programming hardware takes care of all preload
timing and voltage requirements.
Latch-Up Protection
GAL6001 devices are designed with an on-board charge pump to
negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any pos-
sibility of SCR induced latching.
Input Buffers
GAL devices are designed with TTL level compatible input buffers.
These buffers, with their characteristically high impedance, load
driving logic much less than traditional bipolar devices. This al-
lows for a greater fan out from the driving logic.
GAL6001 devices do not possess active pull-ups within their input
structures. As a result, Lattice Semiconductor recommends that
all unused inputs and tri-stated I/O pins be connected to another
active input, Vcc, or GND. Doing this will tend to improve noise
immunity and reduce Icc for the device.
Specifications
GAL6001
13
Circuitry within the GAL6001 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1
s MAX). As a result, the state
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature
of system power-up, some conditions must be met to provide a
valid power-up reset of the GAL6001. First, the VCC rise must
be monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse
width requirements.
The number of Differential Product Term Switching (DPTS ) for
a given design is calculated by subtracting the total number of
product terms that are switching from a Logical HI to a Logical LO
from those switching from a Logical LO to a Logical HI within a
5ns period. After subtracting take the absolute value.
DPTS =
(P-Terms)
LH
- (P-Terms)
HL
DPTS restricts the number of product terms that can be switched
simultaneously - there is no limit on the number of product terms
that can be used.
A software utility is available from Lattice Semiconductor
Applications Engineering that will perform this calculation on any
GAL6001 JEDEC file. This program, DPTS, and additional
information may be obtained from your local Lattice
Semiconductor representative or by contacting Lattice
Semiconductor's Applications Engineering Dept. (Tel: 503-681-
0118 or 1-888-ISP-PLDS; FAX: 681-3037).
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Power-Up Reset
Differential Product Term Switching (DPTS) Applications
Specifications
GAL6001
14
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
9
10
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
9
10
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
Typical AC and DC Characteristic Diagrams
Specifications
GAL6001
15
Vol vs Iol
Iol (mA)
Vol (V)
0
0.5
1
1.5
2
2.5
0.00
20.00
40.00
60.00
80.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00
10.00
20.00
30.00
40.00
50.00
60.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3.5
3.75
4
4.25
4.5
0.00
1.00
2.00
3.00
4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
4.50
4.75
5.00
5.25
5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.7
0.8
0.9
1
1.1
1.2
-55
-25
0
25
75
100
125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
0
25
50
75
100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
0.5
1
1.5
2
2.5
3
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
10
20
30
40
50
60
70
80
90
100
-2.00
-1.50
-1.00
-0.50
0.00
Typical AC and DC Characteristic Diagrams
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