GAL6002

High Performance E

CMOS FPLA

Generic Array LogicTM

ILMC

INPUT LOGIC MACROCELL

IOLMC I/O LOGIC MACROCELL

BLMC

BURIED LOGIC MACROCELL

OLMC

OUTPUT LOGIC MACROCELL

I/ICLK

GND

Vcc

I/O/Q

OCLK

I/O/Q

I/ICLK

GND

OCLK

I/O/Q

Vcc

I/O/Q

GAL6002

Top View

PLCC

DIP

GAL

6002

OUTPUT
ENABLE

AND

INPUT

CLOCK

ICLK

IOLMC

ILMC

OLMC

RESET

OUTPUTS

14 - 23

BLMC

OUTPUT

CLOCK

OCLK

{

INPUTS

2-11

{

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

July 1997

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

6002_02

Features

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

-- 15ns Maximum Propagation Delay
-- 75MHz Maximum Frequency
-- 6.5ns Maximum Clock to Output Delay
-- TTL Compatible 16mA Outputs
-- UltraMOS

Advanced CMOS Technology

· ACTIVE PULL-UPS ON ALL PINS

· LOW POWER CMOS

-- 90mA Typical Icc

· E

CELL TECHNOLOGY

-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention

· UNPRECEDENTED FUNCTIONAL DENSITY

-- 78 x 64 x 36 FPLA Architecture
-- 10 Output Logic Macrocells
-- 8 Buried Logic Macrocells
-- 20 Input and I/O Logic Macrocells

· HIGH-LEVEL DESIGN FLEXIBILITY

-- Asynchronous or Synchronous Clocking
-- Separate State Register and Input Clock Pins
-- Functional Superset of Existing 24-pin PAL

and FPLA Devices

· APPLICATIONS INCLUDE:

-- Sequencers
-- State Machine Control
-- Multiple PLD Device Integration

Description

Having an FPLA architecture, the GAL6002 provides superior
flexibility in state-machine design. The GAL6002 offers the highest
degree of functional integration, flexibility, and speed currently
available in a 24-pin, 300-mil package. E

CMOS technology offers

high speed (<100ms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.

The GAL6002 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.

Pin Configuration

Macrocell Names

PinNames

- I

INPUT

I/O/Q

BIDIRECTIONAL

ICLK

INPUT CLOCK

POWER (+5V)

OCLK

OUTPUT CLOCK

GND

GROUND

Functional Block Diagram

Specifications

GAL6002

The GAL6002 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
IOLMC to the I/O pins (14-23). Each input section is individually
configurable as asynchronous, latched, or registered inputs. Pin
1 (ICLK) is used as an enable input for latched macrocells or as a
clock input for registered macrocells. Individually configurable
inputs provide system designers with unparalleled design flexibility.
With the GAL6002, external input registers and latches are not
necessary.

Both the ILMC and the IOLMC are individually configurable and the
ILMC can be configured independently of the IOLMC. The three
valid macrocell configurations and its associated fuse numbers are
shown in the diagrams on the following pages. Note that these
programmable cells are configured by the logic compiler software.
The user does not need to manually manipulate these architecture
bits.

The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are called
the Buried Logic Macrocells (BLMC), and are useful for building
state machines. The second group of macrocells consists of 10
cells whose outputs, in addition to feeding back into the AND array,
are available at the device pins. Cells in this group are known as
Output Logic Macrocells (OLMC).

The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinational, D-type
register with sum term (asynchronous) clock, or D/E-type register.
Output macrocells always have I/O capability, with directional control
provided by the 10 output enable (OE) product terms. Additionally,
the polarity of each OLMC output is selected through the
programmable polarity control cell called XORD. Polarity selection
for BLMCs is selected through the true and complement forms of
their feedbacks to the AND array. Polarity of all E (Enable) sum
terms is selected through the XORE programmable cells.

When the output or buried logic macrocell is configured as a
D/E type register, the register is clocked from the common OCLK
and the register clock enable input is controlled by the associated
"E" sum term. This configuration is useful for building counters and
state-machines with count hold and state hold functions.

When the macrocell is configured as a D type register with a sum
term clock, the register is always enabled and the associated "E"

sum term is routed directly to the clock input. This permits
asynchronous programmable clocking, selected on a register-by-
register basis.

Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. All registers reset
to logic zero. With the inverting output buffers, the output pins will
reset to logic one.

There are two possible feedback paths from each OLMC. The first
path is directly from the OLMC (this feedback is before the output
buffer). When the OLMC is used as an output, the second feedback
path is through the IOLMC. With this dual feedback arrangement,
the OLMC can be permanently buried without losing the use of the
associated OLMC pin as an input, or dynamically buried with the
use of the output enable product term.

The D/E registers used in this device offer the designer the ultimate
in flexibility and utility. The D/E register architecture can emulate
RS, JK, and T registers with the same efficiency as a dedicated RS,
JK, or T registers.

The three macrocell configurations are shown in the diagrams on
the following pages. These programmable cells are also configured
by the logic compiler software. The user does not need to manually
manipulate these architecture bits.

Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)

Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)

Specifications

GAL6002

(
2

)

13(

(
1

16(

19)

17(

20)

18(

21)

19(

23)

20(

21(

(
2

ESET

Logic Diagram (Continued)

Specifications

GAL6002

Recommended Operating Conditions

Commercial Devices:
Ambient Temperature (T

) ............................... 0 to 75

Supply voltage (V

)

with Respect to Ground ..................... +4.75 to +5.25V

Absolute Maximum Ratings

(1)

Supply voltage V

...................................... 0.5 to +7V

Input voltage applied .......................... 2.5 to V

+1.0V

Off-state output voltage applied ......... 2.5 to V

+1.0V

Storage Temperature ................................ 65 to 150

Ambient Temperature with

Power Applied ........................................ 55 to 125

1.Stresses above those listed under the "Absolute Maximum

Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

COMMERCIAL

Operating Power

= 0.5V V

= 3.0V

L -15/-20

135

Supply Current

toggle

= 15MHz Outputs Open

Input Low Voltage

Vss 0.5

0.8

Input High Voltage

2.0

Vcc+1

Input or I/O Low Leakage Current

(MAX.)

-100

Input or I/O High Leakage Current

3.5V

Output Low Voltage

= MAX. Vin = V

or V

0.5

Output High Voltage

= MAX. Vin = V

or V

2.4

Low Level Output Current

High Level Output Current

3.2

Output Short Circuit Current

= 5V

OUT

= 0.5V T

= 25

130

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.

MAX.

UNITS

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and T

= 25

SYMBOL

PARAMETER

MAXIMUM*

UNITS

TEST CONDITIONS

Input Capacitance

= 5.0V, V

= 2.0V

I/O

I/O Capacitance

= 5.0V, V

I/O

= 2.0V

*Characterized but not 100% tested.

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

Capacitance (TA = 25

C, f = 1.0 MHz)

Specifications

GAL6002

AC Switching Characteristics

Over Recommended Operating Conditions

pd1

Combinatorial Input to Combinatorial Output

pd2

Feedback or I/O to Combinational Output

pd3

Transparent Latch Input to Combinatorial Output

co1

Input Latch ICLK to Combinatorial Output Delay

co2

Input Reg. ICLK to Combinatorial Output Delay

co3

Output D/E Reg. OCLK to Output Delay

6.5

co4

Output D Reg. Sum Term CLK to Output Delay

cf1

Output D/E Reg. OCLK to Buried Feedback Delay

3.6

cf2

Output D Reg. STCLK to Buried Feedback Delay

10.1

su1

Setup Time, Input before Input Latch ICLK

1.5

su2

Setup Time, Input before Input Reg. ICLK

1.5

su3

Setup Time, Input or Fdbk before D/E Reg. OCLK

11.5

su4

Setup Time, Input or Fdbk before D Reg. Sum Term CLK

su5

Setup Time, Input Reg. ICLK before D/E Reg. OCLK

su6

Setup Time, Input Reg. ICLK before D Reg. Sum Term CLK

Hold Time, Input after Input Latch ICLK

Hold Time, Input after Input Reg. ICLK

Hold Time, Input or Feedback after D/E Reg. OCLK

Hold Time, Input or Feedback after D Reg. Sum Term CLK

max1

Max. Clock Frequency w/External Feedback, 1/(

su3+

co3)

55.5 --

47.6 --

MHz

max2

Max. Clock Frequency w/External Feedback, 1/(

su4+

co4)

43.4 --

MHz

max3

Max. Clock Frequency w/Internal Feedback, 1/(

su3+

cf1)

MHz

max4

Max. Clock Frequency w/Internal Feedback, 1/(

su4+

cf2)

MHz

max5

Max. Clock Frequency w/No Feedback, OCLK

MHz

max6

Max. Clock Frequency w/No Feedback, STCLK

MHz

wh1

ICLK Pulse Duration, High

wh2

OCLK Pulse Duration, High

wh3

STCLK Pulse Duration, High

UNITS

1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.

PARAM.

TEST

COND

DESCRIPTION

-20

MIN. MAX.

-15

MIN. MAX.

COM

Specifications

GAL6002

Asynchronous Reset

REGISTERED
OUTPUT

arw

INPUT or
I/O FEEDBACK
DRIVING AR

OCLK

Sum Term CLK

arr2

arr1

VALID INPUT

COMBINATORIAL
OUTPUT

pd1,2

INPUT or
I/O FEEDBACK

Combinatorial Output

Latched Input

INPUT or
I/O FEEDBACK

VALID INPUT

COMBINATORIAL
OUTPUT

ICLK (LATCH)

su1

co1

pd3

INPUT or
I/O FEEDBACK

VALID INPUT

REGISTERED
OUTPUT

Sum Term CLK

su4

co4

max2

Input or I/O to Output Enable/Disable

Clock Width

ICLK or
OCLK

Sum Term CLK

wh1,2

wl1,2

wl3

wh3

Registered Output (Sum Term CLK)

Registered Output (OCLK)

INPUT or
I/O FEEDBACK

VALID INPUT

REGISTERED
OUTPUT

OCLK

max1

su3

co3

Registered Input

INPUT or
I/O FEEDBACK

VALID INPUT

COMBINATORIAL
OUTPUT

ICLK (REGISTER)

OCLK

Sum Term CLK

su2

co2

su5

su6

dis

INPUT or
I/O FEEDBACK

OUTPUT

Switching Waveforms

Specifications

GAL6002

max with External Feedback 1/(

su+

co)

Note: fmax with external feedback is calculated from measured
tsu and tco.

max with Internal Feedback 1/(

su+

cf)

Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

max with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns 10% 90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

See Figure

3-state levels are measured 0.5V from steady-state active
level.

Test Condition

300

390

50pF

Active High

390

50pF

Active Low

300

390

50pF

Active High

390

5pF

Active Low

300

390

5pF

TEST POINT

C *

FROM OUTPUT (O/Q)
UNDER TEST

+5V

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

LOGIC
ARRAY

CLK

LOGIC
ARRAY

CLK

LOGIC
ARRAY

fmax Descriptions

Switching Test Conditions

Output Load Conditions (see figure)

Specifications

GAL6002

Array Description

The GAL6002 contains two E

reprogrammable arrays. The first is

an AND array and the second is an OR array. These arrays are de-
scribed in detail below.

AND ARRAY
The AND array is organized as 78 inputs by 75 product term outputs.
The 10 ILMCs, 10 IOLMCs, 8 BLMC feedbacks, 10 OLMC feed-
backs, and ICLK comprise the 39 inputs to this array (each available
in true and complement forms). 64 product terms serve as inputs
to the OR array. The RESET product term generates the RESET
signal described in the Output and Buried Logic Macrocells sec-
tion. There are 10 output enable product terms which allow device
I/O pins to be bi-directional or tri-state.

OR ARRAY
The OR array is organized as 64 inputs by 36 sum term outputs.
64 product terms from the AND array serve as the inputs to the OR
array. Of the 36 sum term outputs, 18 are data ("D") terms and 18
are enable/clock ("E") terms. These terms feed into the 10 OLMCs
and 8 BLMCs, one "D" term and one "E" term to each.

The programmable OR array offers unparalleled versatility in prod-
uct term usage. This programmability allows from 1 to 64 product
terms to be connected to a single sum term. A programmable OR
array is more flexible than a fixed, shared, or variable product term
architecture.

Electronic Signature

An electronic signature is provided with every GAL6002 device. It
contains 72 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.

NOTE: The electronic signature is included in checksum calcula-
tions. Changing the electronic signature will alter the checksum.

Security Cell

A security cell is provided with every GAL6002 device as a deterrent
to unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the AND array. This cell
can be erased only during a bulk erase cycle, so the original con-
figuration can never be examined once this cell is programmed.
The Electronic Signature is always available to the user, regard-
less of the state of this control cell.

Device Programming

GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manufac-
turers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.

Typical Input Pull-up Characteristic

1 . 0

2 . 0

3 . 0

4 . 0

5 . 0

- 6 0

- 2 0

- 4 0

In p u t V o lt ag e ( V o lt s)

I
nput

r
r
e

(

)

Register Preload

When testing state machine designs, all possible states and state
transitions must be verified, not just those required during normal
operations. This is because certain events may occur during sys-
tem operation that cause the logic to be in an illegal state (power-
up, line voltage glitches, brown-out, etc.). To test a design for proper
treatment of these conditions, a method must be provided to break
the feedback paths and force any desired state (i.e., illegal) into the
registers. Then the machine can be sequenced and the outputs
tested for correct next state generation.

All of the registers in the GAL6002 can be preloaded, including the
ILMC, IOLMC, OLMC, and BLMC registers. In addition, the con-
tents of the state and output registers can be examined in a special
diagnostics mode. Programming hardware takes care of all preload
timing and voltage requirements.

Latch-Up Protection

GAL6002 devices are designed with an on-board charge pump to
negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any pos-
sibility of SCR induced latching.

Input Buffers

GAL6002 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.

GAL6002 input buffers have active pull-ups within their input struc-
ture. This pull-up will cause any un-terminated input or I/O to float
to a TTL high (logical 1). Lattice Semiconductor recommends that
all unused inputs and tri-stated I/O pins be connected to another
active input, Vcc, or GND. Doing this will tend to improve noise

immunity and reduce Icc for the device.

Specifications

GAL6002

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Vcc (min.)

Internal Register
Reset to Logic "0"

Device Pin
Reset to Logic "1"

Circuitry within the GAL6002 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1

s MAX). As a result, the state

on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature

of system power-up, some conditions must be met to provide a
valid power-up reset of the GAL6002. First, the V

rise must be

monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation,
avoid clocking the device until all input and feedback path setup
times have been met. The clock must also meet the minimum
pulse width requirements.

The number of Differential Product Term Switching (DPTS ) for
a given design is calculated by subtracting the total number of
product terms that are switching from a Logical HI to a Logical LO
from those switching from a Logical LO to a Logical HI within a
5ns period. After subtracting take the absolute value.

DPTS =

(P-Terms)

- (P-Terms)

DPTS restricts the number of product terms that can be switched
simultaneously - there is no limit on the number of product terms
that can be used.

The majority of designs fall below 15 DPTS, with the upper limit
being approximately 25 DPTS. Lattice Semiconductor guarantees
and tests the commercial grade GAL6002 for functionality at
DPTS

30.

A software utility is available from Lattice Semiconductor
Applications Engineering that will perform this calculation on any
GAL6002 JEDEC file. This program, DPTS, and additional
information may be obtained from your local Lattice
Semiconductor representative or by contacting Lattice
Semiconductor Applications Engineering Dept. (Tel: 503-681-0118
or 1-888-ISP-PLDS; FAX: 681-3037).

Power-Up Reset

Differential Product Term Switching (DPTS) Applications

Specifications

GAL6002

Normalized Tpd vs Vcc

Supply Voltage (V)

Normalized Tpd

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

PT H->L

PT L->H

Normalized Tco vs Vcc

Supply Voltage (V)

Normalized Tco

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

RISE

FALL

Normalized Tsu vs Vcc

Supply Voltage (V)

Normalized Tsu

0.8

0.9

1.1

1.2

4.50

4.75

5.00

5.25

5.50

PT H->L

PT L->H

Normalized Tpd vs Temp

Temperature (deg. C)

Normalized Tpd

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

PT H->L

PT L->H

Normalized Tco vs Temp

Temperature (deg. C)

Normalized Tco

0.7

0.8

0.9

1.1

1.2

1.3

-55

-25

100

125

RISE

FALL

Normalized Tsu vs Temp

Temperature (deg. C)

Normalized Tsu

0.7

0.8

0.9

1.1

1.2

1.3

1.4

-55

-25

100

125

PT H->L

PT L->H

Delta Tpd vs # of Outputs

Switching

Number of Outputs Switching

Delta Tpd (ns)

-2

-1.5

-1

-0.5

RISE

FALL

Delta Tco vs # of Outputs

Switching

Number of Outputs Switching

Delta Tco (ns)

-2

-1.5

-1

-0.5

RISE

FALL

Delta Tpd vs Output Loading

Output Loading (pF)

Delta Tpd (ns)

-2

100

150

200

250

300

RISE

FALL

Delta Tco vs Output Loading

Output Loading (pF)

Delta Tco (ns)

-2

100

150

200

250

300

RISE

FALL

Typical AC and DC Characteristic Diagrams

Specifications

GAL6002

Vol vs Iol

Iol (mA)

Vol (V)

0.5

1.5

2.5

0.00

20.00

40.00

60.00

80.00

Voh vs Ioh

Ioh(mA)

Voh (V)

0.00

10.00

20.00

30.00

40.00

50.00

60.00

Voh vs Ioh

Ioh(mA)

Voh (V)

3.5

3.75

4.25

4.5

0.00

1.00

2.00

3.00

4.00

Normalized Icc vs Vcc

Supply Voltage (V)

Normalized Icc

0.80

0.90

1.00

1.10

1.20

4.50

4.75

5.00

5.25

5.50

Normalized Icc vs Temp

Temperature (deg. C)

Normalized Icc

0.7

0.8

0.9

1.1

1.2

-55

-25

100

125

Normalized Icc vs Freq.

Frequency (MHz)

Normalized Icc

0.80

0.90

1.00

1.10

1.20

100

Delta Icc vs Vin (1 input)

Vin (V)

Delta Icc (mA)

0.5

1.5

2.5

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Input Clamp (Vik)

Vik (V)

Iik (mA)

100

-2.00

-1.50

-1.00

-0.50

0.00

Typical AC and DC Characteristic Diagrams

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