Document Outline
- ispGAL22LV10 Datasheet
- Pin Configuration
- Ordering Information
- ispGAL22LV10: DC Electrical Characteristics
- ispGAL22LV10: AC Characteristics
ispGAL
22LV10
In-System Programmable Low Voltage
E
2
CMOS
PLD Generic Array LogicTM
1
Features
IN-SYSTEM PROGRAMMABLE
-- IEEE 1149.1 Standard TAP Controller Port
Programming
-- 4-Wire Serial Programming Interface
-- Minimum 10,000 Program/Erase Cycles
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
-- 4 ns Maximum Propagation Delay
-- Fmax = 250 MHz
-- 3 ns Maximum from Clock Input to Data Output
-- UltraMOS
Advanced CMOS Technology
3.3V LOW VOLTAGE 22V10 ARCHITECTURE
-- JEDEC-Compatible 3.3V Interface Standard
-- 5V Tolerant Inputs and I/O
-- I/O Interfaces with Standard 5V TTL Devices
ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
COMPATIBLE WITH STANDARD 22LV10/22V10 DEVICES
-- Function/Fuse-Map Compatible with 22LV10/22V10
Devices
-- Parametric Compatible with 22LV10
E
2
CELL TECHNOLOGY
-- In-System Programmable Logic
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention
APPLICATIONS INCLUDE:
-- DMA Control
-- State Machine Control
-- High Speed Graphics Processing
-- Software-Driven Hardware Configuration
ELECTRONIC SIGNATURE FOR IDENTIFICATION
PROGRAMMABLE
AND-ARRAY
(132X44)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
TDO
TDI
TMS
TCK
I/CLK
I
I
I
I
I
I
I
I
I
I
RESET
PRESET
8
10
12
14
16
16
14
12
10
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
PROGRAMMING
LOGIC
I
Copyright 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
December 1999
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
PLCC
2
28
TCK
I/CLK
I
I
I
I
I
I
I
I
TMS
TDO
TDI
GND
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q
I/O/Q
4
26
25
19
18
21
23
16
14
12
11
9
7
5
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
TDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
TDI
TCK
I/CLK
I
I
I
I
I
TMS
I
I
I
I
I
GND
1
7
14
28
22
15
ispGAL
22LV10
Top View
SSOP
ispGAL22LV10
Top View
isp22lv_06
Description
The ispGAL22LV10 is manufactured using Lattice Semiconductor's
advanced 3.3V E
2
CMOS process, which combines CMOS with
Electrically Erasable (E
2
) floating gate technology. The
ispGAL22LV10 can interface with both 3.3V and 5V signal levels.
The ispGAL22LV10 is fully function/fuse map compatible with the
GAL
22LV10 and GAL22V10. Further, the ispGAL22LV10 is para-
metric compatible with the GAL22LV10. The ispGAL22LV10 also
shares the same 28-pin PLCC package pin-out as the GAL22LV10.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 10,000 erase/write cycles
and data retention in excess of 20 years are specified.
Functional Block Diagram
Pin Configuration
New
4ns
Speed
Grade
Specifications
ispGAL22LV10
2
Commercial Grade Specifications
)
s
n
(
d
p
T
)
s
n
(
u
s
T
)
s
n
(
o
c
T
)
A
m
(
c
c
I
#
g
n
i
r
e
d
r
O
e
g
a
k
c
a
P
4
3
3
0
3
1
J
L
4
-
0
1
V
L
2
2
L
A
G
p
s
i
C
C
L
P
d
a
e
L
-
8
2
L
4
-
0
1
V
L
2
2
L
A
G
p
s
i
K
d
a
e
L
-
8
2
P
O
S
S
5
5
.
3
5
.
3
0
3
1
J
L
5
-
0
1
V
L
2
2
L
A
G
p
s
i
C
C
L
P
d
a
e
L
-
8
2
L
5
-
0
1
V
L
2
2
L
A
G
p
s
i
K
d
a
e
L
-
8
2
P
O
S
S
5
.
7
5
5
0
3
1
J
L
7
-
0
1
V
L
2
2
L
A
G
p
s
i
C
C
L
P
d
a
e
L
-
8
2
L
7
-
0
1
V
L
2
2
L
A
G
p
s
i
K
d
a
e
L
-
8
2
P
O
S
S
0
1
7
5
.
6
0
3
1
J
L
0
1
-
0
1
V
L
2
2
L
A
G
p
s
i
C
C
L
P
d
a
e
L
-
8
2
-
0
1
V
L
2
2
L
A
G
p
s
i
0
1 LK
d
a
e
L
-
8
2
P
O
S
S
5
1
0
1
8
0
3
1
J
L
5
1
-
0
1
V
L
2
2
L
A
G
p
s
i
C
C
L
P
d
a
e
L
-
8
2
-
0
1
V
L
2
2
L
A
G
p
s
i
5
1 LK
d
a
e
L
-
8
2
P
O
S
S
Blank = Commercial
I = Industrial
Grade
Package
Power
L = Low Power
Speed (ns)
XXXXXXXX
XX
X
X X
Device Name
_
J = PLCC
K = SSOP
ispGAL22LV10
Ordering Information
Part Number Description
Industrial Grade Specifications
)
s
n
(
d
p
T
)
s
n
(
u
s
T
)
s
n
(
o
c
T
)
A
m
(
c
c
I
#
g
n
i
r
e
d
r
O
e
g
a
k
c
a
P
5
.
7
5
5
0
6
1
I
J
L
7
-
0
1
V
L
2
2
L
A
G
p
s
i
C
C
L
P
d
a
e
L
-
8
2
L
7
-
0
1
V
L
2
2
L
A
G
p
s
i
I
K
d
a
e
L
-
8
2
P
O
S
S
0
1
7
5
.
6
0
6
1
I
J
L
0
1
-
0
1
V
L
2
2
L
A
G
p
s
i
C
C
L
P
d
a
e
L
-
8
2
-
0
1
V
L
2
2
L
A
G
p
s
i
0
1 L I
K
d
a
e
L
-
8
2
P
O
S
S
5
1
0
1
8
0
6
1
I
J
L
5
1
-
0
1
V
L
2
2
L
A
G
p
s
i
C
C
L
P
d
a
e
L
-
8
2
-
0
1
V
L
2
2
L
A
G
p
s
i
5
1 L I
K
d
a
e
L
-
8
2
P
O
S
S
Specifications
ispGAL22LV10
3
ispGAL22LV10 OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the ispGAL22LV10 has two primary func-
tional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (S0 and S1), which are nor-
mally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC's D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop's /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
"on" (dedicated output), "off" (dedicated input), or "product-term
driven" (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
The ispGAL22LV10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 17 and 27), two have ten product terms
(pins 18 and 26), two have twelve product terms (pins 19 and 25),
two have fourteen product terms (pins 20 and 24), and two OLMCs
have sixteen product terms (pins 21 and 23). In addition to the
product terms available for logic, each OLMC has an additional
product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
The ispGAL22LV10 has a product term for Asynchronous Reset
(AR) and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchro-
nous Reset sets all registers to zero any time this dedicated product
term is asserted. The Synchronous Preset sets all registers to a
logic one on the rising edge of the next clock pulse after this product
term is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
AR
SP
D
Q
Q
CLK
4 TO 1
MUX
2 TO 1
MUX
Output Logic Macrocell (OLMC)
Output Logic Macrocell Configurations
Specifications
ispGAL22LV10
4
ACTIVE HIGH
ACTIVE LOW
ACTIVE HIGH
ACTIVE LOW
S
0
= 1
S
1
= 1
S
0
= 0
S
1
= 1
S
0
= 0
S
1
= 0
S
0
= 1
S
1
= 0
A R
S P
D
Q
Q
C L K
A R
S P
D
Q
Q
C L K
Registered Mode
Combinatorial Mode
Specifications
ispGAL22LV10
5
PLCC & SSOP Package Pinout
2
26
OLMC
S0
5810
S1
5811
0440
.
.
.
.
0880
3
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0
4
8
12
16
20
24
28
32
36
40
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
12
0000
5764
0044
.
.
.
0396
27
S0
5808
S1
5809
25
OLMC
S0
5812
S1
5813
0924
.
.
.
.
.
1452
4
5
6
24
OLMC
S0
5814
S1
5815
1496
.
.
.
.
.
.
2112
23
OLMC
S0
5816
S1
5817
2156
.
.
.
.
.
.
.
2860
21
OLMC
S0
5818
S1
5819
2904
.
.
.
.
.
.
.
3608
20
OLMC
S0
5820
S1
5821
3652
.
.
.
.
.
.
4268
OLMC
S0
5822
S1
5823
4312
.
.
.
.
.
4840
10
19
18
OLMC
S0
5824
S1
5825
4884
.
.
.
.
5324
11
5368
.
.
.
5720
17
OLMC
S0
5826
S1
5827
9
7
13
16
8
10
14
16
12
12
16
14
10
8
OLMC
Electronic Signature
5828, 5829 ...
... 5890, 5891
L
S
B
M
S
B
Byte 7 Byte 6 Byte 5 Byte 4
Byte 2 Byte 1 Byte 0
Byte 3
ispGAL22LV10 Logic Diagram/JEDEC Fuse Map
Specifications
ispGAL22LV10
6
Specifications
ispGAL22LV10
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground
degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 3.3V and TA = 25
C
COMMERCIAL
I
CC
Operating Power
V
IL
= 0V V
IH
= 3.0V Unused Inputs at V
IL
--
90
130
mA
Supply Current
f
toggle
= 1MHz Outputs Open
V
IL
Input Low Voltage
Vss - 0.3
--
0.8
V
V
IH
Input or I/O High Voltage
2.0
--
5.25
V
I
IL
1
Input or I/O Low Leakage Current
0V
V
IN
V
IL
(MAX.)
--
--
-150
A
I
IH
Input or I/O High Leakage Current
(Vcc-0.2)V
V
IN
V
CC
--
--
10
A
Input or I/O High Leakage Current
Vcc
V
IN
5.25V
--
--
2
mA
V
OL
Output Low Voltage
I
OL
= MAX. Vin = V
IL
or V
IH
--
--
0.4
V
I
OL
= 500
A Vin = V
IL
or V
IH
--
--
0.2
V
V
OH
Output High Voltage
I
OH
= MAX. Vin = V
IL
or V
IH
2.4
--
--
V
I
OH
= -100
A Vin = V
IL
or V
IH
Vcc-0.2V
--
--
V
I
OL
Low Level Output Current
--
--
8
mA
I
OL-ISP
Low Level Output Current TDO
--
--
4
mA
I
OH
High Level Output Current
--
--
8
mA
I
OH-ISP
High Level Output Current TDO
--
--
2
mA
I
OS
2
Output Short Circuit Current
V
CC
= 3.3V
V
OUT
= 0.5V T
A
= 25
C
-30
--
-80
mA
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (T
A
) ............................... 0 to 75
C
Supply voltage (V
CC
)
with Respect to Ground ......................... +3.0 to +3.6V
Industrial Devices:
Ambient Temperature (T
A
) ............................ -40 to 85
C
Supply voltage (V
CC
)
with Respect to Ground ......................... +3.0 to +3.6V
Absolute Maximum Ratings
(1)
Supply voltage V
CC
.................................... -0.5 to +4.6V
Input and I/O voltage applied ..................... -0.5 to +5.6V
Off-state output voltage applied ................ -0.5 to +4.6V
Storage Temperature ................................. -65 to 150
C
Ambient Temperature with
Power Applied ......................................... -55 to 125
C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
3
MAX.
UNITS
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
INDUSTRIAL
I
CC
Operating Power
V
IL
= 0V V
IH
= 3.0V Unused Inputs at V
IL
--
90
160
mA
Supply Current
f
toggle
= 1MHz Outputs Open
Specifications
ispGAL22LV10
7
-5
MIN. MAX.
Specifications
ispGAL22LV10
-10
MIN. MAX.
t
pd
2
A
Input or I/O to Comb. Output
1
4
1
5
1
7.5
1
10
1
15
ns
t
co
2
A
Clock to Output Delay
1
3
1
3.5
1
5
1
6.5
--
8
ns
t
cf
3
--
Clock to Feedback Delay
--
2.5
--
2.5
--
2.5
--
2.5
--
2.5
ns
t
su
--
Setup Time, Input or Fdbk before Clk
3
--
3.5
--
5
--
7
--
10
--
ns
t
h
--
Hold Time, Input or Fdbk after Clk
0
--
0
--
0
--
0
--
0
--
ns
A
Maximum Clock Frequency with
167
--
143
--
100
--
74
--
55.5
--
MHz
External Feedback, 1/(tsu + tco)
f
max
4
A
Maximum Clock Frequency with
182
--
166
--
133
--
105
--
80
--
MHz
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
250
--
200
--
166
--
111
--
83.3
--
MHz
No Feedback
t
wh
4
--
Clock Pulse Duration, High
2
--
2.5
--
3
--
4
--
6
--
ns
t
wl
4
--
Clock Pulse Duration, Low
2
--
2.5
--
3
--
4
--
6
--
ns
t
en
B
Input or I/O to Output Enabled
1
5
1
6
1
7.5
1
10
--
15
ns
t
dis
C
Input or I/O to Output Disabled
1
5
1
6
1
7.5
1
10
--
15
ns
t
ar
A
Input or I/O to Asynch. Reset of Reg.
1
4.5
1
5.5
1
9
1
13
--
20
ns
t
arw
--
Asynchronous Reset Pulse Duration
4.5
--
5.5
--
7
--
8
--
15
--
ns
t
arr
--
Asynch. Reset to Clk
Recovery Time
3.5
--
4
--
5
--
8
--
10
--
ns
t
spr
--
Synch. Preset to Clk
Recovery Time
3.5
--
4
--
5
--
10
--
10
--
ns
-7
MIN. MAX.
UNITS
PARAM.
TEST
COND
1
.
DESCRIPTION
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
C
I
Input Capacitance
4
pF
V
CC
= 3.3V, V
I
= 0V
C
I/O
I/O Capacitance
5
pF
V
CC
= 3.3V, V
I/O
= 0V
1) Refer to Switching Test Conditions section.
2) Minimum values for
t
pd and
t
co are not 100% tested but established by characterization.
3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
4) Refer to fmax Descriptions section. Characterized but not 100% tested.
Note: Maximum clock input rise and fall time between 10% to 90% of Vout = 2ns.
COM/IND
COM/IND
COM
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (TA = 25
C, f = 1.0 MHz)
-15
MIN. MAX.
COM/IND
-4
MIN. MAX.
COM
Specifications
ispGAL22LV10
8
Input or I/O to Output Enable/Disable
Registered Output
Combinatorial Output
f
max with Feedback
Clock Width
t
en
t
dis
INPUT or
I/O FEEDBACK
OUTPUT
CLK
(w/o fdbk)
t
w h
t
w l
1 /
f
m a x
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
t
s u
t
c o
t
h
(external fdbk)
1 /
f
m a x
CLK
REGISTERED
FEEDBACK
t
c f
t
su
1 /
f
m a x ( i n t e r n a l f d b k )
REGISTERED
OUTPUT
C L K
t
arw
t
arr
INPUT or
I/O FEEDBACK
DRIVING AR
t
ar
Asynchronous Reset
REGISTERED
OUTPUT
CLK
INPUT or
I/O FEEDBACK
DRIVING SP
t
su
t
h
t
co
t
spr
Synchronous Preset
VALID INPUT
INPUT or
I/O FEEDBACK
t
pd
COMBINATORIAL
OUTPUT
Switching Waveforms
Specifications
ispGAL22LV10
9
f
max with Internal Feedback 1/(
t
su+
t
cf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
f
max with No Feedback
Note: fmax with no feedback may be less
than 1/twh + twl. This is to allow for a clock
duty cycle of other than 50%.
R E G I S T E R
L O G I C
A R R A Y
t
c o
t
s u
C L K
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
f
max with External Feedback 1/(
t
su+
t
co)
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
REGISTER
LOGIC
ARRAY
CLK
t
su +
t
h
f
max Descriptions
Switching Test Conditions
*C
L
includes test fixture and probe capacitance.
TEST POINT
Z
0
= 50
, C
L
= 35pF*
FROM OUTPUT (O/Q)
UNDER TEST
+1.45V
R
1
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
1.5ns 10% 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See Figure
Output Load Conditions (see figure)
Test Condition
R
1
C
L
A
50
35pF
B
High Z to Active High at 1.9V
50
35pF
High Z to Active Low at 1.0V
50
35pF
C
Active High to High Z at 1.9V
50
35pF
Active Low to High Z at 1.0V
50
35pF
Specifications
ispGAL22LV10
10
Electronic Signature
An electronic signature (ES) is provided in every ispGAL22LV10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the
security cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when com-
piling a set of logic equations. In addition, many device
programmers have two separate selections for the device,
typically an ispGAL22LV10 and a ispGAL22LV10-UES (UES =
User Electronic Signature) or ispGAL22LV10-ES. This allows
users to maintain compatibility with existing 22V10 designs,
while still having the option to use the GAL device's extra feature.
The JEDEC map for the ispGAL22LV10 contains the 64 extra
fuses for the electronic signature, for a total of 5892 fuses.
However, the ispGAL22LV10 device can still be programmed
with a standard 22V10 JEDEC map (5828 fuses) with any
qualified device programmer.
Security Cell
A security cell is provided in every ispGAL22LV10 device to
prevent unauthorized copying of the array patterns. Once
programmed, this cell prevents further read access to the func-
tional bits in the device. This cell can only be erased by
re-programming the device, so the original configuration can
never be examined once this cell is programmed. The Electronic
Signature is always available to the user, regardless of the state
of this control cell.
Latch-Up Protection
ispGAL22LV10 devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch.
Device Programming
The ispGAL22LV10 device uses a standard 22V10 JEDEC
fusemap file to describe the device programming information.
Any third party logic compiler can produce the JEDEC file for this
device.
In-System Programmability
The ispGAL22LV10 device features In-System Programmable
technology. By integrating all the high voltage programming
circuitry on-chip, programming can be accomplished by simply
shifting data into the device. Once the function is programmed,
the non-volatile E
2
CMOS cells will not lose the pattern even
when the power is turned off.
All necessary programming is done via four TTL level logic
interface signals. These four signals are fed into the on-chip
programming circuitry where a state machine controls the pro-
gramming. The interface signals are Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS)
control. For details on the operation of the internal state machine
and programming of ispGAL22LV10 devices please refer to the
ISP Architecture and Programming section in this Data Book.
Output Register Preload
When testing state machine designs, all possible states and
state transitions must be verified in the design, not just those
required in the normal machine operations. This is because
certain events may occur during system operation that throw the
logic into an illegal state (power-up, line voltage glitches, brown-
outs, etc.). To test a design for proper treatment of these
conditions, a way must be provided to break the feedback paths,
and force any desired (i.e., illegal) state into the registers. Then
the machine can be sequenced and the outputs tested for correct
next state conditions.
The ispGAL22LV10 device includes circuitry that allows each
registered output to be synchronously set either high or low.
Thus, any present state condition can be forced for test sequenc-
ing. If necessary, approved GAL programmers capable of
executing test vectors perform output register preload automati-
cally.
Input Buffers
ispGAL22LV10 devices are designed with TTL level compatible
input buffers. These buffers have a characteristically high
impedance, and present a much lighter load to the driving logic
than bipolar TTL devices.
All input and I/O pins also have built-in active pull-ups. As a
result, floating inputs will float to a TTL high (logic 1). However,
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins be connected to an adjacent active input, Vcc,
or ground. Doing so will tend to improve noise immunity and
reduce Icc for the device. (See equivalent input and I/O schemat-
ics on the following page.)
Typical Input Current
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
0.00
1.00
2.00
3.00
4.00
Input Voltage (Volts)
Input Current (
A)
Specifications
ispGAL22LV10
11
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Device Pin
Reset to Logic "0"
V c c
C L K
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
up, some conditions must be met to provide a valid power-up
reset of the ispGAL22LV10. First, the Vcc rise must be
monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will
reset within a maximum of tpr time. As in normal system
operation, avoid clocking the device until all input and feedback
path setup times have been met. The clock must also meet the
minimum pulse width requirements.
Output
Input
(Vref = Vcc)
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
(Vref = Vcc)
Vcc
PIN
Vcc
Vref
Active Pull-up Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Circuitry within the ispGAL22LV10 provides a reset signal to all
registers during power-up. All internal registers will have their
Q outputs set low after a specified time (tpr, 1
s MAX). As a
result, the state on the registered output pins (if they are
enabled) will be either high or low on power-up, depending on
the programmed polarity of the output pins. This feature can
greatly simplify state machine design by providing a known
state on power-up. The timing diagram for power-up is shown
above. Because of the asynchronous nature of system power-
Power-Up Reset
Input/Output Equivalent Schematics
Specifications
ispGAL22LV10
12
ispGAL22LV10: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
3
3.15
3.3
3.45
3.6
Supply Voltage (V)
Normalized T
p
d
RISE
FALL
Normalized Tco vs Vcc
0.97
0.98
0.99
1
1.01
1.02
1.03
3
3.15
3.3
3.45
3.6
Supply Voltage (V)
Normalized T
c
o
RISE
FALL
Normalized Tsu vs Vcc
0.8
0.9
1
1.1
1.2
3
3.15
3.3
3.45
3.6
Supply Voltage (V)
Normalized Tsu
RISE
FALL
Normalized Tpd vs Temp
0.9
1
1.1
1.2
-55
-25
0
25
50
75
100
125
Temperature (deg. C)
Normalized T
p
d
RISE
FALL
Normalized Tsu vs Temp
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
-55
-25
0
25
50
75
1 00
1 25
Temperature (deg. C)
Normalized Tsu
RISE
FALL
Normalized Tco vs Temp
0.9
0.95
1
1.05
1.1
1.15
-55
-25
0
2 5
5 0
7 5
100
125
Temperature (deg. C)
Normalized T
c
o
RISE
FALL
Delta Tpd vs # of Outputs
Switching
-0.4
-0.3
-0.2
-0.1
0
1
2
3
4
5
6
7
8
9
1 0
Number of Outputs Switching
Delta T
pd (
ns)
RISE
FALL
Delta Tco vs # of Outputs
Switching
-0.4
-0.3
-0.2
-0.1
0
1
2
3
4
5
6
7
8
9
1 0
Number of Outputs Switching
Delta T
c
o (
ns)
RISE
FALL
Delta Tpd vs Output Loading
-4
0
4
8
1 2
1 6
0
50
100
150
200
250
3 00
Output Loading (pF)
Delta T
pd (
ns)
RISE
FALL
Delta Tco vs Output Loading
-4
0
4
8
1 2
1 6
0
50
100
150
200
250
3 00
Output Loading (pF)
Delta T
c
o (
ns)
RISE
FALL
Specifications
ispGAL22LV10
13
ispGAL22LV10: Typical AC and DC Characteristic Diagrams
Vol vs Iol
0
0.2
0.4
0.6
0.8
1
0
5
10
15
20
25
30
35
Iol (mA)
Vol (
V
)
Voh vs Ioh
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
0
5
1 0
1 5
20
Ioh (mA)
Voh (
V
)
Voh vs Ioh
2.8
2.85
2.9
2.95
3
3.05
0.00
1.00
2.00
3.00
4.00
5.00
Ioh (mA)
Voh (
V
)
Normalized Icc vs Vcc
0.9
0.95
1
1.05
1.1
1.15
3
3.15
3.3
3.45
3.6
Supply Voltage (V)
Normalized I
c
c
Normalized Icc vs Temp
0.8
0.9
1
1.1
1.2
-55
-25
0
2 5
5 0
8 8
100
125
Temperature (deg. C)
Normalized I
c
c
Normalized Icc vs Freq
1
1.05
1.1
1.15
1.2
1.25
1.3
1
15
25
50
7 5
1 00
Frequency (MHz)
Normalized I
c
c
Input Clamp (Vik vs Iik)
0
10
20
30
40
50
60
-2.9
-2.3
-1.7
-1.1
-0.5
0
Vik (V)
Iik (
m
A)
Delta Icc vs Vin (1 input)
0
1
2
3
4
5
6
7
8
9
1 0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vin (V)
Delta I
cc (
m
A)
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