Specifications
ispGAL22V10
1
IN-SYSTEM PROGRAMMABLETM (5-V ONLY)
-- 4-Wire Serial Programming Interface
-- Minimum 10,000 Program/Erase Cycles
-- Built-in Pull-Down on SDI Pin Eliminates Discrete
Resistor on Board (ispGAL22V10C Only)
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
-- 7.5 ns Maximum Propagation Delay
-- Fmax = 111 MHz
-- 5 ns Maximum from Clock Input to Data Output
-- UltraMOS
Advanced CMOS Technology
ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
COMPATIBLE WITH STANDARD 22V10 DEVICES
-- Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
E
2
CELL TECHNOLOGY
-- In-System Programmable Logic
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention
TEN OUTPUT LOGIC MACROCELLS
-- Maximum Flexibility for Complex Logic Designs
APPLICATIONS INCLUDE:
-- DMA Control
-- State Machine Control
-- High Speed Graphics Processing
-- Software-Driven Hardware Configuration
ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
The ispGAL22V10, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E
2
) floating gate technology to provide the industry's
first in-system programmable 22V10 device. E
2
technology of-
fers high speed (<100ms) erase times, providing the ability to re-
program or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The ispGAL22V10 is fully function/fuse map/parametric
compatible with standard bipolar and CMOS 22V10 devices. The
standard PLCC package provides the same functional pinout as
the standard 22V10 PLCC package with No-Connect pins being
used for the ISP interface signals.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 10,000 erase/write
cycles and data retention in excess of 20 years are specified.
FUNCTIONAL BLOCK DIAGRAM
FEATURES
PIN CONFIGURATION
PROGRAMMABLE
AND-ARRAY
(132X44)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
SDI
MODE
SCLK
I/CLK
I
I
I
I
I
I
I
I
I
I
RESET
PRESET
8
10
12
14
16
16
14
12
10
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
PROGRAMMING
LOGIC
I
ispGAL22V10
In-System Programmable E
2
CMOS PLD
Generic Array LogicTM
Copyright 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
July 1997
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
PLCC
SDO
I/O/Q
I/O/Q
I/O/Q
2
2 8
I
I
MODE
I
I
I
5
1 1
1 4
1 6
1 9
2 5
4
7
9
1 2
1 8
2 1
2 3
2 6
I
I/O/Q
I/O/Q
I/O/Q
I
I
I/
O
/
Q
I/C
L
K
I/
O
/
Q
Vc
c
SC
L
K
I/O
/Q
I/O
/Q
I
SD
I
GN
D
I
I
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
SDI
SCLK
I/CLK
I
I
I
I
I
MODE
I
I
I
I
I
GND
1
7
14
28
22
15
ispGAL
22V10
Top View
SSOP
ispGAL22V10
Top View
isp22v10_02
Specifications
ispGAL22V10
2
ORDERING INFORMATION
Commercial Grade Specifications
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2
Industrial Grade Specifications
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PART NUMBER DESCRIPTION
Blank = Commercial
I = Industrial
Grade
Package
Power
L = Low Power
Speed (ns)
XXXXXXXX
XX
X
X X
Device Name
_
J = PLCC
K = SSOP
ispGAL22V10C
ispGAL22V10B
Specifications
ispGAL22V10
3
OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
ispGAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the ispGAL22V10 has two primary func-
tional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (SO and S1), which are nor-
mally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC's D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be de-
fined by a logic equation. The D flip-flop's /Q output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either "on" (dedicated output), "off" (dedicated input), or "product-
term driven" (dynamic I/O). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.
The ispGAL22V10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 17 and 27), two have ten product terms
(pins 18 and 26), two have twelve product terms (pins 19 and 25),
two have fourteen product terms (pins 20 and 24), and two
OLMCs have sixteen product terms (pins 21 and 23). In addition
to the product terms available for logic, each OLMC has an ad-
ditional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.
The ispGAL22V10 has a product term for Asynchronous Reset
(AR) and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asyn-
chronous Reset sets all registers to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all reg-
isters to a logic one on the rising edge of the next clock pulse after
this product term is asserted.
NOTE: The AR and SP product terms will force the Q output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
A R
S P
D
Q
Q
C L K
4 T O 1
M U X
2 T O 1
M U X
Specifications
ispGAL22V10
4
REGISTERED MODE
ACTIVE HIGH
ACTIVE LOW
COMBINATORIAL MODE
ACTIVE HIGH
ACTIVE LOW
S
0
= 1
S
1
= 1
S
0
= 0
S
1
= 1
S
0
= 0
S
1
= 0
S
0
= 1
S
1
= 0
A R
S P
D
Q
Q
C L K
A R
S P
D
Q
Q
C L K
Specifications
ispGAL22V10
5
ispGAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP
PLCC & SSOP Package Pinout
2
26
OLMC
S0
5810
S1
5811
0440
.
.
.
.
0880
3
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0
4
8
12
16
20
24
28
32
36
40
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
12
0000
5764
0044
.
.
.
0396
27
S0
5808
S1
5809
25
OLMC
S0
5812
S1
5813
0924
.
.
.
.
.
1452
4
5
6
24
OLMC
S0
5814
S1
5815
1496
.
.
.
.
.
.
2112
23
OLMC
S0
5816
S1
5817
2156
.
.
.
.
.
.
.
2860
21
OLMC
S0
5818
S1
5819
2904
.
.
.
.
.
.
.
3608
20
OLMC
S0
5820
S1
5821
3652
.
.
.
.
.
.
4268
OLMC
S0
5822
S1
5823
4312
.
.
.
.
.
4840
10
19
18
OLMC
S0
5824
S1
5825
4884
.
.
.
.
5324
11
5368
.
.
.
5720
17
OLMC
S0
5826
S1
5827
9
7
13
16
8
10
14
16
12
12
16
14
10
8
OLMC
Electronic Signature
5828, 5829 ...
... 5890, 5891
L
S
B
M
S
B
Byte 7 Byte 6 Byte 5 Byte 4
Byte 2 Byte 1 Byte 0
Byte 3
Specifications
ispGAL22V10
6
V
IL
Input Low Voltage
Vss 0.5
--
0.8
V
V
IH
Input High Voltage
2.0
--
Vcc+1
V
I
IL
Input or I/O Low Leakage Current
1
0V
V
IN
V
IL
(MAX.)
--
--
100
A
SDI Low Leakage Current
2
0V
V
IN
V
IL
(MAX.)
--
--
250
A
I
IH
Input or I/O High Leakage Current
3.5V
V
IN
V
CC
--
--
10
A
SDI High Leakage Current
2
V
IN
=
V
OH
(MIN.)
--
--
1
mA
V
OL
Output Low Voltage
I
OL
= MAX. Vin = V
IL
or V
IH
--
--
0.5
V
V
OH
Output High Voltage
I
OH
= MAX. Vin = V
IL
or V
IH
2.4
--
--
V
I
OL
Low Level Output Current
--
--
16
mA
I
OH
High Level Output Current
--
--
3.2
mA
I
OS
3
Output Short Circuit Current
V
CC
= 5V
V
OUT
= 0.5V
T
A
= 25
C
30
--
130
mA
RECOMMENDED OPERATING COND.
Commercial Devices:
Ambient Temperature (T
A
) ............................. 0 to +75
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient Temperature (T
A
) ............................ -40 to 85
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.50 to +5.50V
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
4
MAX.
UNITS
COMMERCIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V
L -7/-10/-15
--
90
140
mA
Supply Current
f
toggle
= 15MHz Outputs Open
ABSOLUTE MAXIMUM RATINGS
(1)
Supply voltage V
CC
.......................................
-
0.5 to +7V
Input voltage applied ........................... -2.5 to V
CC
+1.0V
Off-state output voltage applied ........... -2.5 to V
CC
+1.0V
Storage Temperature .................................. -65 to 150
C
Ambient Temperature with
Power Applied ......................................... -55 to 125
C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
Specifications
ispGAL22V10C
ispGAL22V10B
1) The leakage current is due to the internal pull-up on all pins (except SDI on ispGAL22V10C). See Input Buffer section for
more information.
2) The leakage current is due to the internal pull-down on the SDI pin (ispGAL22V10C only). See Input Buffer section for more
information.
3) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
4) Typical values are at Vcc = 5V and T
A
= 25
C
INDUSTRIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V
L -15
--
90
165
mA
Supply Current
f
toggle
= 15MHz Outputs Open
Specifications
ispGAL22V10
7
-15
MIN. MAX.
-10
MIN. MAX.
-7
MIN. MAX.
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
t
pd
A
Input or I/O to Combinatorial Output
--
7.5
--
10
--
15
ns
t
co
A
Clock to Output Delay
--
5
--
7
--
8
ns
t
cf
2
--
Clock to Feedback Delay
--
2.5
--
2.5
--
2.5
ns
t
su
1
--
Setup Time, Input or Feedback before Clock
6.5
--
7
10
--
ns
t
su
2
--
Setup Time, SP before Clock
10
--
10
--
10
--
ns
t
h
--
Hold Time, Input or Feedback after Clock
0
--
0
--
0
--
ns
A
Maximum Clock Frequency with
87
--
71.4
--
55.5
--
MHz
External Feedback, 1/(tsu + tco)
f
max
3
A
Maximum Clock Frequency with
111
--
105
--
80
--
MHz
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
111
--
105
--
83.3
--
MHz
No Feedback
t
wh
--
Clock Pulse Duration, High
4
--
4
--
6
--
ns
t
wl
--
Clock Pulse Duration, Low
4
--
4
--
6
--
ns
t
en
B
Input or I/O to Output Enabled
--
8
--
10
--
15
ns
t
dis
C
Input or I/O to Output Disabled
--
8
--
10
--
15
ns
t
ar
A
Input or I/O to Asynchronous Reset of Register
--
13
--
13
--
20
ns
t
arw
--
Asynchronous Reset Pulse Duration
8
--
8
--
15
--
ns
t
arr
--
Asynchronous Reset to Clock Recovery Time
8
--
8
--
10
--
ns
t
spr
--
Synchronous Preset to Clock Recovery Time
10
--
10
--
10
--
ns
PARAMETER
UNITS
TEST
COND.
1
DESCRIPTION
COM
COM/IND
COM
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 5.0V, V
I
= 2.0V
C
I/O
I/O Capacitance
8
pF
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested.
CAPACITANCE (T
A
= 25
C, f = 1.0 MHz)
Specifications
ispGAL22V10C
ispGAL22V10B
Specifications
ispGAL22V10
8
Input or I/O to Output Enable/Disable
Registered Output
Combinatorial Output
f
max with Feedback
Clock Width
SWITCHING WAVEFORMS
t
en
t
dis
INPUT or
I/O FEEDBACK
OUTPUT
CLK
(w/o fdbk)
t
w h
t
w l
1 /
f
m a x
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
t
s u
t
c o
t
h
(external fdbk)
1 /
f
m a x
CLK
REGISTERED
FEEDBACK
t
c f
t
su
1 /
f
m a x ( i n t e r n a l f d b k )
REGISTERED
OUTPUT
C L K
t
arw
t
arr
INPUT or
I/O FEEDBACK
DRIVING AR
t
ar
Asynchronous Reset
REGISTERED
OUTPUT
CLK
INPUT or
I/O FEEDBACK
DRIVING SP
t
su
t
h
t
co
t
spr
Synchronous Preset
VALID INPUT
INPUT or
I/O FEEDBACK
t
pd
COMBINATORIAL
OUTPUT
Specifications
ispGAL22V10
9
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns 10% 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition
R
1
R
2
C
L
A
300
390
50pF
B
Active High
390
50pF
Active Low
300
390
50pF
C
Active High
390
5pF
Active Low
300
390
5pF
SWITCHING TEST CONDITIONS
f
max with Internal Feedback 1/(
t
su+
t
cf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
f
max with No Feedback
Note: fmax with no feedback may be less
than 1/twh + twl. This is to allow for a clock
duty cycle of other than 50%.
fmax DESCRIPTIONS
R E G I S T E R
L O G I C
A R R A Y
t
c o
t
s u
C L K
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
f
max with External Feedback 1/(
t
su+
t
co)
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
REGISTER
LOGIC
ARRAY
CLK
t
su +
t
h
Specifications
ispGAL22V10
10
ELECTRONIC SIGNATURE
An electronic signature (ES) is provided in every ispGAL22V10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the
security cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when
compiling a set of logic equations. In addition, many device
programmers have two separate selections for the device,
typically an ispGAL22V10 and a ispGAL22V10-UES (UES =
User Electronic Signature) or ispGAL22V10-ES. This allows
users to maintain compatibility with existing 22V10 designs,
while still having the option to use the GAL device's extra
feature.
The JEDEC map for the ispGAL22V10 contains the 64 extra
fuses for the electronic signature, for a total of 5892 fuses.
However, the ispGAL22V10 device can still be programmed
with a standard 22V10 JEDEC map (5828 fuses) with any
qualified device programmer.
SECURITY CELL
A security cell is provided in every ispGAL22V10 device to
prevent unauthorized copying of the array patterns. Once
programmed, this cell prevents further read access to the
functional bits in the device. This cell can only be erased by re-
programming the device, so the original configuration can never
be examined once this cell is programmed. The Electronic
Signature is always available to the user, regardless of the state
of this control cell.
LATCH-UP PROTECTION
ispGAL22V10 devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch. Additionally, outputs are designed with n-
channel pullups instead of the traditional p-channel pullups to
eliminate any possibility of SCR induced latching.
DEVICE PROGRAMMING
The ispGAL22V10 device uses a standard 22V10 JEDEC
fusemap file to describe the device programming information.
Any third party logic compiler can produce the JEDEC file for this
device.
IN-SYSTEM PROGRAMMABILITY
The ispGAL22V10 device features In-System Programmable
technology. By integrating all the high voltage programming
circuitry on-chip, programming can be accomplished by simply
shifting data into the device. Once the function is programmed,
the non-volatile E
2
CMOS cells will not lose the pattern even
when the power is turned off.
All necessary programming is done via four TTL level logic
interface signals. These four signals are fed into the on-chip
programming circuitry where a state machine controls the pro-
gramming. The interface signals are Serial Data In (SDI), Serial
Data Out (SDO), Serial Clock (SCLK) and Mode (MODE)
control. For details on the operation of the internal state machine
and programming of ispGAL22V10 devices please refer to the
ISP Architecture and Programming section in this Data Book.
OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and
state transitions must be verified in the design, not just those
required in the normal machine operations. This is because
certain events may occur during system operation that throw the
logic into an illegal state (power-up, line voltage glitches, brown-
outs, etc.). To test a design for proper treatment of these
conditions, a way must be provided to break the feedback paths,
and force any desired (i.e., illegal) state into the registers. Then
the machine can be sequenced and the outputs tested for
correct next state conditions.
The ispGAL22V10 device includes circuitry that allows each
registered output to be synchronously set either high or low.
Thus, any present state condition can be forced for test se-
quencing. If necessary, approved GAL programmers capable of
executing test vectors perform output register preload automati-
cally.
INPUT BUFFERS
ispGAL22V10 devices are designed with TTL level compatible
input buffers. These buffers have a characteristically high
impedance, and present a much lighter load to the driving logic
than bipolar TTL devices.
All input and I/O pins (except SDI on the ispGAL22V10C) also
have built-in active pull-ups. As a result, floating inputs will float
to a TTL high (logic 1). The SDI pin on the ispGAL22V10C has
a built-in pull-down to keep the device out of the programming
state if the pin is not actively driven. However, Lattice Semicon-
ductor recommends that all unused inputs and tri-stated I/O pins
be connected to an adjacent active input, Vcc, or ground. Doing
so will tend to improve noise immunity and reduce Icc for the
device. (See equivalent input and I/O schematics on the follow-
ing page.)
Typical Input Current
1.0
2.0
3.0
4.0 5.0
-60
0
-20
-40
0
Input Voltage (Volts)
Input Current (
A)
Specifications
ispGAL22V10
11
POWER-UP RESET
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Device Pin
Reset to Logic "0"
V c c
C L K
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the ispGAL22V10.
First, the Vcc rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
Output
Input
(Vref Typical = 3.2V)
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
(Vref Typical = 3.2V)
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit (Except SDI
on ispGAL22V10C)
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Pull-down Resistor
(SDI on ispGAL22V10C Only)
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Circuitry within the ispGAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1
s MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
Specifications
ispGAL22V10
12
ispGAL22V10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-1
-0.75
-0.5
-0.25
0
1
2
3
4
5
6
7
8
9
10
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-1
-0.75
-0.5
-0.25
0
1
2
3
4
5
6
7
8
9
10
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
Delta Tpd vs Output Loading
Ouput Loading (pF)
Delta Tpd(ns)
- 2
0
2
4
6
8
10
0
50
100
150
200
250
300
RISE
FALL
Specifications
ispGAL22V10
13
ispGAL22V10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Iol (mA)
Vol (V)
0
0.5
1
1.5
2
2.5
3
0.00
20.00
40.00
60.00
80.00
100.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00
10.00
20.00
30.00
40.00
50.00
60.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3.5
3.75
4
4.25
4.5
0.00
1.00
2.00
3.00
4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
0
25
50
75
100
Delta Icc vs Vcc
Vin (V)
Delta Icc (mA)
0
1
2
3
4
5
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
10
20
30
40
50
60
70
80
90
100
-2.00
-1.50
-1.00
-0.50
0.00
Specifications
ispGAL22V10
14
Notes
Copyright 1997 Lattice Semiconductor Corporation.
E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice
Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation.
Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispDS, ispDS+, ispGDS, ispGDX, ispHDL, ispJTAG, ispStarter,
ispSTREAM, ispTEST, ispTURBO, ispVECTOR, ispVerilog, ispVHDL, Latch-Lock, LHDL, pDS+, RFT, Total ISP and Twin
GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All
brand names or product names mentioned are trademarks or registered trademarks of their respective holders.
Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international
patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296
US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US,
5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US,
5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US,
0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not
represent that products described herein are free from patent infringement or from any third-party right.
The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC)
reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors
contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers
obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is
current.
LSC warrants performance of its products to current and applicable specifications in accordance with LSC's standard
warranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing of
all parameters of each product is not necessarily performed, unless mandated by government requirements.
LSC assumes no liability for applications assistance, customer's product design, software performance, or infringements of
patents or services arising from the use of the products and services described herein.
LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such
applications is prohibited.
LATTICE SEMICONDUCTOR CORPORATION
5555 Northeast Moore Court
Hillsboro, Oregon 97124 U.S.A.
Tel.: (503) 681-0118
FAX: (503) 681-3037
http://www.latticesemi.com
July 1997
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