Document Outline
- ispLSI 1016E Data Sheet
- DC Electrical Characteristics
- AC Characteristics
- Pin Configuration: 44 PLCC
- Pin Configuration: 44 TQFP
- Ordering Information
ispLSI
1016E
In-System Programmable High Density PLD
1016e_06
1
Features
HIGH-DENSITY PROGRAMMABLE LOGIC
-- 2000 PLD Gates
-- 32 I/O Pins, Four Dedicated Inputs
-- 96 Registers
-- High-Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
-- Small Logic Block Size for Random Logic
HIGH-PERFORMANCE E
2
CMOS
TECHNOLOGY
--
f
max = 125 MHz Maximum Operating Frequency
--
t
pd = 7.5 ns Propagation Delay
-- TTL Compatible Inputs and Outputs
-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- 100% Tested at Time of Manufacture
-- Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
-- In-System Programmable (ISPTM) 5V Only
-- Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
-- Reprogram Soldered Device for Faster Prototyping
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
-- Complete Programmable Device Can Combine Glue
Logic and Structured Designs
-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control to
Minimize Switching Noise
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERTTM LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZERTM
-- PC and UNIX Platforms
Functional Block Diagram
CLK
A0
A1
A2
A3
A4
A5
A6
A7
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
Output Routing Pool
Output Routing Pool
Global Routing Pool (GRP)
Logic
Array
D Q
D Q
D Q
D Q
GLB
0139C1-isp
Description
The ispLSI 1016E is a High Density Programmable Logic
Device containing 96 Registers, 32 Universal I/O pins,
four Dedicated Input pins, three Dedicated Clock Input
pins, one Global OE input pin and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1016E features
5V in-system programming and in-system diagnostic
capabilities. The ispLSI 1016E offers non-volatile
reprogrammability of the logic, as well as the interconnect
to provide truly reconfigurable systems. A functional
superset of the ispLSI 1016 architecture, the ispLSI
1016E device adds a new global output enable pin.
The basic unit of logic on the ispLSI 1016E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1...B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 1016E device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinatorial
or registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
October 1998
2
Specifications
ispLSI 1016E
Functional Block Diagram
Figure 1. ispLSI 1016E Functional Block Diagram
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source
4 mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. Each ispLSI
1016E device contains two Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1016E device are selected using the
Clock Distribution Network. Three dedicated clock pins
(Y0, Y1 and Y2) are brought into the distribution network,
and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0
and IOCLK 1) are provided to route clocks to the GLBs
and I/O cells. The Clock Distribution Network can also be
driven from a special clock GLB (B0 on the ispLSI 1016E
device). The logic of this GLB allows the user to create an
internal clock from a combination of internal signals
within the device.
I/O 0
I/O 1
I/O 2
I/O 3
GOE 0/IN 3
MODE/IN 2
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
SDI/IN 0
SDO/IN 1
I/O 4
I/O 5
ispEN
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
A0
A1
A2
A3
A4
A5
A6
A7
B7
B6
B5
B4
B3
B2
B1
B0
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
Megablock
Output Routing Pool (ORP)
Input Bus
lnput Bus
*Note: Y1 and
RESET
are multiplexed on the same pin
SCLK/Y2
Y0
Y1/
RESET
*
0139B(1a)-isp
3
Specifications
ispLSI 1016E
Absolute Maximum Ratings
1
Supply Voltage V
CC
................................ -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150
C
Case Temp. with Power Applied .............. -55 to 125
C
Max. Junction Temp. (T
J
) with Power Applied ... 150
C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
T
A
= 0
C to + 70
C
T
A
= -40
C to + 85
C
SYMBOL
Table 2-0005/1016E
V
CC
V
IH
V
IL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN.
MAX.
UNITS
4.75
4.5
2.0
0
5.25
5.5
V
cc
+1
0.8
V
V
V
V
Commercial
Industrial
Capacitance (T
A
=25
o
C, f=1.0 MHz)
Data Retention Specifications
C
SYMBOL
Table 2-0006/1016E
C
PARAMETER
Y0 Clock Capacitance
12
UNITS
TYPICAL
TEST CONDITIONS
1
2
8
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)
pf
pf
V = 5.0V, V = 2.0V
V = 5.0V, V = 2.0V
CC
CC
PIN
PIN
Table 2-0008/1016E
PARAMETER
Data Retention
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
20
10000
Years
Cycles
4
Specifications
ispLSI 1016E
Switching Test Conditions
Figure 2. Test Load
DC Electrical Characteristics
Over Recommended Operating Conditions
Input Pulse Levels
Table 2-0003/1016E
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
-125
-100, -80
2 ns
3 ns
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
R2
CL
A
470
390
35pF
B
390
35pF
470
390
35pF
Active High
Active Low
C
470
390
5pF
390
5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004/1016E
+ 5V
R1
R2
CL
*
Device
Output
Test
Point
*
CL includes Test Fixture and Probe Capacitance.
0213a
V
OL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V = 5V and T = 25
C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum I .
Table 2-0007/1016E
1
V
OH
I
IH
I
IL
I
IL-isp
PARAMETER
I
IL-PU
I
OS
2, 4
I
CC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
3.5V
V
V
0V
V
V (Max.)
0V
V
V
0V
V
V
V = 5V, V = 0.5V
V = 0.5V, V = 3.0V
f = 1 MHz
OL
OH
IN IL
IN CC
IN
IL
IN IL
CC OUT
CLOCK
IL
IH
CONDITION
MIN.
TYP.
MAX.
UNITS
3
2.4
90
90
0.4
10
-10
-150
-150
-200
V
V
A
A
A
A
mA
mA
mA
CC
A
OUT
CC
CC
Commercial
Industrial
5
Specifications
ispLSI 1016E
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
-125
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions Section.
Table 2-0030-16/125,100, 80
1
4
3
1
tsu2 + tco1
( )
-100
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
A
1
Data Prop. Delay, 4PT Bypass, ORP Bypass
7.5
10.0
ns
t
pd2
A
2
Data Prop. Delay, Worst Case Path
ns
f
max
A
3
Clk. Frequency with Int. Feedback
125
100
MHz
f
max (Ext.)
4
Clk. Frequency with Ext. Feedback
MHz
f
max (Tog.)
5
Clk. Frequency, Max. Toggle
MHz
t
su1
6
GLB Reg. Setup Time before Clk., 4 PT Bypass
ns
t
co1
A
7
GLB Reg. Clk. to Output Delay, ORP Bypass
ns
t
h1
8
GLB Reg. Hold Time after Clk., 4 PT Bypass
0.0
ns
t
su2
9
GLB Reg. Setup Time before Clk.
5.5
ns
t
co2
10 GLB Reg. Clk. to Output Delay
ns
t
h2
11 GLB Reg. Hold Time after Clk.
0.0
ns
t
r1
A
12 Ext. Reset Pin to Output Delay
ns
t
rw1
13 Ext. Reset Pulse Duration
5.0
ns
t
ptoeen
B
14 Input to Output Enable
ns
t
ptoedis
C
15 Input to Output Disable
ns
t
wh
18 Ext. Sync. Clk. Pulse Duration, High
3.0
4.0
ns
t
wl
19 Ext. Sync. Clk. Pulse Duration, Low
3.0
4.0
ns
t
su3
20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0
ns
t
h3
21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3)
0.0
ns
100
167
5.0
4.5
5.5
10.0
12.0
12.0
10.0
77.0
125
7.0
0.0
8.0
0.0
6.5
3.5
0.0
13.0
5.0
6.0
13.5
15.0
15.0
( )
1
twh + tw1
t
goeen
B
16 Global OE Output Enable
ns
7.0
9.0
t
goedis
C
17 Global OE Output Disable
ns
7.0
9.0
-80
MIN. MAX.
15.0
18.5
84.0
57.0
100
8.5
8.0
0.0
9.5
9.5
0.0
17.0
10.0
20.0
20.0
10.5
10.5
5.0
0.0
4.5
5.0
6
Specifications
ispLSI 1016E
Internal Timing Parameters
1
t
iobp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice hard macros.
Table 2-0036-16/125,100, 80
Inputs
UNITS
-125
MIN.
-100
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
22 I/O Register Bypass
0.4
ns
t
iolat
23 I/O Latch Delay
2.4
ns
t
grp1
29 GRP Delay, 1 GLB Load
1.9
ns
GLB
t
1ptxor
36 1 Product Term/XOR Path Delay
6.1
ns
t
20ptxor
37 20 Product Term/XOR Path Delay
6.1
ns
t
xoradj
38 XOR Adjacent Path Delay
6.6
ns
t
gbp
39 GLB Register Bypass Delay
1.6
ns
t
gsu
40 GLB Register Setup Time before Clock
0.2
ns
t
gh
41 GLB Register Hold Time after Clock
2.5
ns
t
gco
42 GLB Register Clock to Output Delay
1.9
ns
3
t
gro
43 GLB Register Reset to Output Delay
6.3
ns
t
ptre
44 GLB Product Term Reset to Register Delay
5.1
ns
t
ptoe
45 GLB Product Term Output Enable to I/O Cell Delay
7.1
ns
t
ptck
46 GLB Product Term Clock Delay
4.8
5.3
ns
ORP
0.3
1.8
GRP
1.8
t
4ptbpc
34 4 Product Term Bypass Path Delay (Combinatorial)
5.7
ns
4.4
4.4
4.4
1.0
3.9
t
4ptbpr
35 4 Product Term Bypass Path Delay (Registered)
5.6
ns
3.9
0.2
1.5
1.8
4.4
3.5
5.5
3.2
3.5
t
orp
47 ORP Delay
1.0
ns
t
orpbp
48 ORP Bypass Delay
0.0
ns
1.0
0.0
t
iosu
24 I/O Register Setup Time before Clock
3.0
3.5
ns
t
ioh
25 I/O Register Hold Time after Clock
-0.3
-0.4
ns
t
ioco
26 I/O Register Clock to Out Delay
5.0
ns
4.0
t
ior
27 I/O Register Reset to Out Delay
5.0
ns
4.0
t
din
28 Dedicated Input Delay
2.6
ns
2.2
-80
MIN. MAX.
0.6
3.6
4.5
-0.6
7.5
7.5
3.9
2.9
7.1
8.2
8.3
1.9
8.1
7.3
-0.6
4.3
2.9
7.0
7.2
9.7
6.8
7.5
1.5
0.0
t
grp16
32 GRP Delay, 16 GLB Loads
3.1
ns
t
grp4
30 GRP Delay, 4 GLB Loads
2.2
ns
2.4
1.9
t
grp8
31 GRP Delay, 8 GLB Loads
2.5
ns
2.1
4.7
3.3
3.8
7
Specifications
ispLSI 1016E
Internal Timing Parameters
1
t
ob
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Table 2-0037-16/125,100,80
Outputs
UNITS
-125
MIN.
-100
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
49 Output Buffer Delay
1.7
ns
t
gy0
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
1.3
1.4
1.4
ns
Global Reset
1.4
t
sl
50 Output Slew Limited Delay Adder
10.0
ns
10.0
t
oen
51 I/O Cell OE to Output Enabled
5.3
ns
4.3
Clocks
1.3
t
gr
59 Global Reset to GLB and I/O Registers
5.5
ns
3.2
t
odis
52 I/O Cell OE to Output Disabled
5.3
ns
4.3
t
goe
53 Global Output Enable
3.7
ns
2.7
t
gy1/2
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.3
2.4
2.9
ns
2.7
t
gcp
56 Clock Delay, Clock GLB to Global GLB Clock Line
0.8
0.8
1.8
ns
1.8
t
ioy1/2
57 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line
0.0
0.0
0.4
ns
0.3
t
iocp
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
0.8
0.8
1.8
ns
1.8
-80
MIN. MAX.
3.0
10.0
6.4
6.4
4.1
4.5
2.1
2.1
3.6
4.4
1.2
2.7
0.0
0.6
1.2
2.7
8
Specifications
ispLSI 1016E
ispLSI 1016E Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
Input
Register
Clock
Distribution
I/O Pin
(Input)
Y0
Y1,2
D
Q
GLB Reg Bypass
ORP Bypass
D
Q
RST
RE
OE
CK
I/O Reg Bypass
I/O Cell
ORP
GLB
GRP
I/O Cell
#23 - 27
#30
#35
#36-38
#55-58
#44-46
#54
#47
#48
Reset
Ded. In
GOE 0
#28
#22
RST
#59
#59
#39
#40-43
#51, 52
0491-16
Comb 4 PT Bypass #34
#53
GRP
Loading
Delay
#29, 31, 32
#49, 50
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
=
=
=
=
t
su
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) - (
t
iobp +
t
grp4 +
t
ptck(min))
(#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
(0.3 + 1.9 + 4.4) + (0.2) - (0.3 + 1.9 + 3.2)
1.4 ns
=
=
=
=
t
h
Clock (max) + Reg h - Logic
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gh) - (
t
iobp +
t
grp4 +
t
20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 1.9 + 3.5) + (1.5) - (0.3 + 1.9 + 4.4)
0.6 ns
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 1.9 + 3.5) + (1.8) + (1.0 + 1.4)
9.9 ns
Table 2-0042-16
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
=
=
=
=
t
su
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) - (
t
gy0(min) +
t
gco +
t
gcp(min))
(#22 + #30 + #37) + (#40) - (#54 + #42 + #56)
(0.3 + 1.9 + 4.4) + (0.2) - (1.3 + 1.8 + 0.8)
2.9 ns
=
=
=
=
t
h
Clock (max) + Reg h - Logic
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gh) - (
t
iobp +
t
grp4 +
t
20ptxor)
(#54 + #42 + #56) + (#41) - (#22 + #30 + #37)
(1.3 + 1.8 + 1.8) + (1.5) - (0.3 + 1.9 + 4.4)
-0.2 ns
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gco) + (
t
orp +
t
ob)
(#54 + #42 + #56) + (#42) + (#47 + #49)
(1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4)
9.1 ns
1. Calculations are based upon timing specifications for the ispLSI 1016E-
125
9
Specifications
ispLSI 1016E
Power Consumption
Power consumption in the ispLSI 1016E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3 shows the relationship between power and
operating speed.
80
110
0
20
40
60
80
100 120 140
f
max (MHz)
I
CC (mA)
Notes: Configuration of four 16-bit counters
Typical current at 5V, 25
C
ispLSI 1016E
100
0127B-16-80-isp/1016
ICC can be estimated for the ispLSI 1016E using the following equation:
ICC(mA) = 23 + (# of PTs * 0.52) + (# of nets * max freq * 0.004)
Where:
# of PTs = Number of product terms used in design
# of nets = Number of signals used in device
Max freq = Highest clock frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads
on average exists and the device is filled with four 16-bit counters. These values are for estimates only. Since the
value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
120
130
90
Figure 3. Typical Device Power Consumption vs fmax
Maximum GRP Delay vs GLB Loads
GLB Load
1
3
1
4
8
16
GRP Delay (ns)
2
16E GRP/GLB.eps
ispLSI 1016E-125
ispLSI 1016E-100
12
ispLSI 1016E-80
10
Specifications
ispLSI 1016E
Input - This pin performs two functions. When
ispEN
is logic low, it functions
as an input pin to load programming data into the device. It is a dedicated
input pin when
ispEN
is logic high.SDI/IN0 also is used as one of the two
control pins for the isp state machine.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
This pin performs two functions:
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK controls become active.
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
Input/Output Pins - These are the general purpose I/O pins used by the logic
array.
NAME
Table 2-0002C-16-isp
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
GOE 0/IN 3
2
Y1/
RESET
Y0
SDI/IN 0
1
ispEN
MODE/IN 2
1
Input - This pin performs two functions. When
ispEN
is logic low, it functions
as a pin to control the operation of the isp state machine. It is a dedicated
input pin when
ispEN
is logic high.
GND
Vcc
VCC
- Dedicated clock input. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or
I/O cell on the device.
Output/Input - This pin performs two functions. When
ispEN
is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when
ispEN
is logic high.
SDO/IN 1
1
Input - This pin performs two functions. When
ispEN
is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated clock
input when
ispEN
is logic high. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or I/O
cell on the device.
SCLK/Y2
1
Ground (GND)
- Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
PLCC
PIN NUMBERS
15,
19,
25,
29,
37,
41,
3,
7,
16,
20,
26,
30,
38,
42,
4,
8,
17,
21,
27,
31,
39,
43,
5,
9,
18,
22,
28,
32,
40,
44,
6,
10
2
35
11
14
13
36
1,
12,
24
33
23
34
1. Pins have dual function capability.
2. Pins have dual function capability which is software selectable.
TQFP
PIN NUMBERS
9,
13,
19,
23,
31,
35,
41,
1,
10,
14,
20,
24,
32,
36,
42,
2,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
40
29
5
8
7
30
17,
6,
18
27
39
28
Pin Description
11
Specifications
ispLSI 1016E
Pin Configurations
ispLSI 1016E 44-Pin PLCC Pinout Diagram
I/O 18
I/O 17
I/O 16
MODE/IN 2
1
Y1/RESET
VCC
SCLK/Y2
1
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
ispEN
1
SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0/IN 3
2
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1
SDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 1016E
Top View
7
8
9
10
12
11
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6
18
5
19
4
20
3
21
2
22
1
23
44
24
43
25
42
26
41
27
40
28
0123A-isp1016
1. Pins have dual function capability.
2. Pins have dual function capability which is software selectable.
ispLSI 1016E 44-Pin TQFP Pinout Diagram
I/O 18
I/O 17
I/O 16
MODE/IN 2
1
Y1/RESET
VCC
SCLK/Y2
1
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
ispEN
1
SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0/IN 3
2
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1
SDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 1016E
Top View
1
2
3
4
6
5
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
0851-16E/TQFP
1. Pins have dual function capability.
2. Pins have dual function capability which is software selectable.
12
Specifications
ispLSI 1016E
Part Number Description
ispLSI 1016E Ordering Information
Device Number
Grade
Blank = Commercial
I = Industrial
1016E
XXX
X
XXX
X
Speed
Power
L = Low
Package
J = PLCC
T44 = TQFP
Device Family
0212/1016E
ispLSI
125
100
80
=
=
=
125 MHz fmax
100 MHz fmax
84 MHz fmax
84
84
44-Pin PLCC
15
15
ispLSI 1016E-80LJ
44-Pin TQFP
ispLSI 1016E-80LT44
Table 2-0041A/1016E
FAMILY
fmax (MHz)
125
125
100
ORDERING NUMBER
PACKAGE
44-Pin PLCC
44-Pin TQFP
tpd (ns)
7.5
7.5
10
ispLSI
ispLSI 1016E-125LJ
ispLSI 1016E-125LT44
44-Pin PLCC
ispLSI 1016E-100LJ
100
44-Pin TQFP
10
ispLSI 1016E-100LT44
COMMERCIAL
Table 2-0041B/1016E
FAMILY
fmax (MHz)
84
84
ORDERING NUMBER
PACKAGE
44-Pin PLCC
44-Pin TQFP
tpd (ns)
15
15
ispLSI
ispLSI 1016E-80LJI
ispLSI 1016E-80LT44I
INDUSTRIAL
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