1
ispLSI
1048C
In-System Programmable High Density PLD
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
1048C_08
Functional Block Diagram
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool
Output Routing Pool
Output Routing Pool
CLK
E7 E6 E5 E4 E3 E2 E1 E0
C0 C1 C2 C3 C4 C5 C6 C7
D7
D6
D5
D4
D3
D2
D1
D0
Output Routing Pool
Logic
Array
D Q
D Q
D Q
D Q
Global Routing Pool (GRP)
GLB
0139G1A-isp
Description
The ispLSI 1048C is a High-Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, two Global Output Enables
(GOE), four Dedicated Clock Input pins and a Global
Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 1048C features 5-Volt in-system programming
and in-system diagnostic capabilities. It is the first device
which offers non-volatile reprogrammability of the logic,
and the interconnect to provide truly reconfigurable sys-
tems. Compared to the ispLSI 1048, the ispLSI 1048C
offers two additional dedicated inputs and two new Glo-
bal Output Enable pins.
The basic unit of logic on the ispLSI 1048C device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 in figure 1. There are a total of 48 GLBs in the ispLSI
1048C devices. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Features
HIGH-DENSITY PROGRAMMABLE LOGIC
-- 8000 PLD Gates
-- 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output
Enables
-- 288 Registers
-- High-Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
-- Small Logic Block Size for Random Logic
-- Security Cell Prevents Unauthorized Copying
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
--
f
max = 70 MHz Maximum Operating Frequency
--
f
max = 50 MHz for Industrial and Military/883 Devices
--
t
pd = 16 ns Propagation Delay
-- TTL Compatible Inputs and Outputs
-- Electrically Erasable and Reprogrammable
-- Non-Volatile E
2
CMOS
Technology
-- 100% Tested at Time of Manufacture
IN-SYSTEM PROGRAMMABLE
-- In-System ProgrammableTM (ISPTM) 5-Volt Only
-- Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
-- Reprogram Soldered Devices for Faster Debugging
COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
-- Complete Programmable Device Can Combine Glue
Logic and Structured Designs
-- Four Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERTTM LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZERTM
-- PC and UNIX Platforms
Copyright 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
August 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Specifications
ispLSI 1048C
2
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
The device also has a 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs have
selectable polarity, active high or active low. The signal
voltage levels are TTL-compatible, and the output drivers
can source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock as
shown in figure 1. The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1048C device contains six Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1048C device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0 on the
ispLSI 1048C device). The logic of this GLB allows the
user to create an internal clock from a combination of
internal signals.
Functional Block Diagram
Figure 1. ispLSI 1048C Functional Block Diagram
Output Routing Pool (ORP)
B0
B1
B2
B3
B4
B5
B6
B7
Output Routing Pool (ORP)
C0
C1
C2
C3
C4
C5
C6
C7
Output Routing Pool (ORP)
F7
F6
F5
F4
F3
F2
F1
F0
Input Bus
Output Routing Pool (ORP)
E7
E6
E5
E4
E3
E2
E1
E0
Input Bus
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
Megablock
Input Bus
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
D7
D6
D5
D4
D3
D2
D1
D0
Output Routing Pool (ORP)
I/O
94
I/O
95
I/O
93
I/O
92
I/O
91
I/O
90
I/O
89
I/O
88
I/O
87
I/O
86
I/O
85
I/O
84
I/O
83
I/O
82
I/O
81
I/O
80
IN
11
I/O
78
I/O
79
I/O
77
I/O
76
I/O
75
I/O
74
I/O
73
I/O
72
I/O
71
I/O
70
I/O
69
I/O
68
I/O
67
I/O
66
I/O
65
I/O
64
IN
9
IN
10
I/O
17
I/O
16
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
SDO/
IN3
Y
0
Y
1
Y
2
Y
3
I/O
33
I/O
32
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
I/O
44
I/O
45
I/O
46
I/O
47
SCLK/
IN 5
IN
4
IN 7
IN 6
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
I/O 4
I/O 5
ispEN
RESET
Input Bus
Input Bus
lnput Bus
0139F(2)-48B-isp
IN
8
GOE0
GOE1
IN2
Specifications
ispLSI 1048C
3
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150
C
Case Temp. with Power Applied .............. -55 to 125
C
Max. Junction Temp. (T
J
) with Power Applied ... 150
C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
V
V
PARAMETER
SYMBOL
MIN.
MAX.
UNITS
5.25
5.5
5.5
0.8
Vcc + 1
Supply Voltage
V
CC
V
IL
V
IH
Table 2- 0005Aisp w/mil.eps
4.75
4.5
4.5
0
2.0
Commercial T
A
=
0C to +70C
Industrial
T
A
= -40C to +85C
Military/883
T
C
= -55
C to +125
C
Input Low Voltage
Input High Voltage
V
Capacitance (T
A
=25
o
C, f=1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM
1
UNITS
TEST CONDITIONS
C
1
Commercial/Industrial
8
pf
V
CC
=5.0V, V
IN
=2.0V
Military
10
pf
V
CC
=5.0V, V
IN
=2.0V
C
2
I/O and Clock Capacitance
10
pf
V
CC
=5.0V, V
I/O
, V
Y
=2.0V
1. Characterized but not 100% tested.
Table 2- 0006
Dedicated Input Capacitance
Data Retention Specifications
Table 2- 0008B
PARAMETER
Data Retention
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
20
10000
--
--
Years
Cycles
Specifications
ispLSI 1048C
4
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Switching Test Conditions
DC Electrical Characteristics
Over Recommended Operating Conditions
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Time
3ns 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See figure 2
3-state levels are measured 0.5V from steady-state
active level.
Table 2- 0003
Output Load Conditions (see figure 2)
Test Condition
R1
R2
CL
A
470
390
35pF
B
Active High
390
35pF
Active Low
470
390
35pF
Active High to Z
390
5pF
C
at V
OH
- 0.5V
Active Low to Z
470
390
5pF
at V
OL
+ 0.5V
Table 2- 0004A
Figure 2. Test Load
+ 5V
R1
R2
CL
*
Device
Output
Test
Point
*
CL includes Test Fixture and Probe Capacitance.
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
V
V
A
A
A
A
mA
mA
mA
I
OL
=8 mA
I
OH
=-4 mA
0V
V
IN
V
IL
(MAX.)
3.5V
V
IN
V
CC
0V
V
IN
V
IL
(MAX.)
0V
V
IN
V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.5V, V
IH
= 3.0V Commercial
f
TOGGLE
= 1 MHz
Industrial/Military
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2,4
165
165
2.4
1. One output at a time for a maximum duration of one second. V
out
= 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Measured using twelve 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25
o
C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
I
CC
.
SYMBOL
MIN.
MAX.
TYP.
3
PARAMETER
CONDITION
UNITS
0.4
-10
10
-150
-150
-200
235
260
Table 2- 0007A-48-isp
Specifications
ispLSI 1048C
5
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
t
su3
t
h3
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
Clock Frequency, Max Toggle
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg. Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
20
21
22
23
A
A
A
A
A
B
C
B
C
DESCRIPTION
1
PARAMETER
#
2
MIN.
-70
-50
MAX.
MAX.
16.0
19.0
10.0
11.5
15.0
20.0
20.0
15.0
15.0
22.0
26.0
14.0
16.0
20.5
27.5
27.5
20.5
20.5
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
UNITS
Table 2- 0030-48C/70, 50
70.4
47.6
83.3
9.5
0
11.0
0
10.0
6.0
6.0
2.0
6.5
50.3
34.5
58.8
13.0
0
15.0
0
13.5
8.5
8.5
3.0
9.0
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
( )
1
twh + tw1
( )
1
tsu2 + tco1
TEST
4
COND.
Specifications
ispLSI 1048C
6
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Internal Timing Parameters
1
4.3
5.5
4.6
5.1
7.4
6.2
6.7
8.0
10.5
22.7
5.5
6.7
7.5
8.9
1.2
2.3
2.8
11.1
9.6
8.2
3.4
1.4
9.1
0.3
3.9
7.3
3.4
3.1
4.0
3.4
3.7
5.4
4.5
4.9
5.8
7.6
16.5
4.0
4.9
5.5
6.5
0.9
1.5
2.1
8.1
7.0
6.0
2.5
1.0
6.5
0.1
2.9
5.3
2.5
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
t
grp1
t
grp4
t
grp8
t
grp16
t
grp48
t
4ptbp
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
t
orp
t
orpbp
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN. MAX.
DESCRIPTION
PARAMETER
UNITS
-50
#
2
MIN. MAX.
-70
Inputs
I/O Register Bypass
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 48 GLB Loads
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay
3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
ORP Bypass Delay
GRP
GLB
ORP
Table 2- 0036-48C/70, 50
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Specifications
ispLSI 1048C
7
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Global OE
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset to GLB and I/O Registers
7.4
6.1
2.6
6.1
2.6
2.1
5.0
5.0
10.0
5.4
6.4
5.5
6.4
5.5
8.3
t
ob
t
oen
t
odis
t
goe
t
gy0
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
t
gr
50
51
52
53
54
55
56
57
58
59
2.9
6.9
6.9
13.6
7.4
8.7
7.6
8.7
7.6
11.4
5.4
4.5
1.9
4.5
1.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN. MAX.
DESCRIPTION
PARAMETER
UNITS
-50
#
2
MIN. MAX.
-70
Outputs
1. Internal Timing Parameters are not tested and are for reference only.
Global Reset
Table 2- 0037-48C/70, 50
Clocks
Internal Timing Parameters
1
Specifications
ispLSI 1048C
8
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
ispLSI 1048C Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
4 PT Bypass
20 PT
XOR Delays
Control
PTs
GRP
Loading
Delay
Input
Register
Clock
Distribution
I/O Pin
(Input)
Y0
Y1,2,3
D
Q
GRP 4
GLB Reg Bypass
ORP Bypass
D
Q
RST
RE
OE
CK
I/O Reg Bypass
I/O Cell
ORP
GLB
GRP
I/O Cell
#25 - 29
#32
#36
#37, 38, 39
#55, 56,
57, 58
#45, 46,
47
#54
#48
#49
Reset
Ded. In
#30
#24
RST
#59
#59
#40
#41, 42,
43, 44
#51, 52
#50
GOE0, 1
0491A/48
#53
#31, 33,
34, 35
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
t
su
= Logic + Reg su - Clock (min)
=
(t
iobp +
t
grp4 +
t
20ptxor
)
+
(t
gsu
) - (t
iobp +
t
grp4 +
t
ptck(min)
)
=
(
#24 + #32 + #38
)
+
(
#41
) - (
#24 + #32 + #47
)
5.9 ns = (3.1 + 4.9 + 5.5) + (2.9) - (3.1 + 4.9 + 2.5)
t
h
= Clock (max) + Reg h - Logic
=
(t
iobp +
t
grp4 +
t
ptck(max)
)
+
(t
gh
) - (t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#24 + #32 + #47
)
+
(
#42
) - (
#24 + #32 + #38
)
5.8 ns = (3.1 + 4.9 + 6.0) + (5.3) - (3.1 + 4.9 + 5.5)
t
co
= Clock (max) + Reg co + Output
=
(t
iobp +
t
grp4 +
t
ptck(max)
)
+
(t
gco
)
+
(t
orp +
t
ob
)
=
(
#24 + #32 + #47
)
+
(
#43
)
+
(
#48 + #50
)
20.1 ns = (3.1 + 4.9 +6.0) + (1.5) + (2.5 + 2.1)
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
t
su
= Logic + Reg su - Clock (min)
=
(t
iobp +
t
grp4 +
t
20ptxor
)
+
(t
gsu
) - (t
gy0(min) +
t
gco +
t
gcp(min)
)
=
(
#24 + #32 + #38
)
+
(
#41
) - (
#54 + #43 + #56
)
7.6 ns = (3.1 + 4.9 + 5.5) + (2.9) - (5.4 + 1.5 + 1.9)
t
h
= Clock (max) + Reg h - Logic
=
(t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(t
gh
) - (t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#54 + #43 + #56
)
+
(
#42
) - (
#24 + #32 + #38
)
4.2 ns = (5.4 + 1.5 + 5.5) + (5.3) - (3.1 + 4.9 + 5.5)
t
co
= Clock (max) + Reg co + Output
=
(t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(t
gco
)
+
(t
orp +
t
ob
)
=
(
#54 + #43 + #56
)
+
(
#43
)
+
(
#48 + #50
)
18.5 ns = (5.4 + 1.5 + 5.5) + (1.5) + (2.5 + 2.1)
1. Calculations are based upon timing specifications for the ispLSI 1048C-70
Table 2- 0042-48C
Specifications
ispLSI 1048C
9
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Maximum GRP Delay vs GLB Loads
ispLSI 1048C-70
4
5
6
4
8
12
16
GLB Loads
GRP
Delay (ns)
ispLSI 1048C-50
7
8
9
10
3
0126A-48C-80-isp
1
11
Power Consumption
Power consumption in the ispLSI 1048C device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
Figure 3. Typical Device Power Consumption vs fmax
ure 3 shows the relationship between power and operat-
ing speed.
50
100
150
200
250
0
10
20
30
40
50
60
70
f
max (MHz)
I
CC (mA)
Notes: Configuration of Twelve 16-bit Counters
Typical Current at 5V, 25C
ispLSI 1048C
80
0127A-48C-80-isp
ICC can be estimated for the ispLSI 1048C using the following equation:
ICC = 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.
Specifications
ispLSI 1048C
10
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Pin Description
Input Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
PQFP PIN NUMBERS
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 5
21, 22, 23, 24, 25, 26
I/O 6 - I/O 11
27, 28, 29, 30, 31, 32
I/O 12 - I/O 17
34, 35, 36, 37, 38, 39
I/O 18 - I/O 23
40, 41, 42, 43, 44, 45
I/O 24 - I/O 29
52, 53, 54, 55, 56, 57
I/O 30 - I/O 35
58, 59, 60, 61, 62, 63
I/O 36 - I/O 41
66, 67, 68, 69, 70, 71
I/O 42 - I/O 47
72, 73, 74, 75, 76, 77
I/O 48 - I/O 53
85, 86, 87, 88, 89, 90
I/O 54 - I/O 59
91, 92, 93, 94, 95, 96
I/O 60 - I/O 65
98, 99,100,101,102, 103
I/O 66 - I/O 71
104,105,106,107,108, 109
I/O 72 - I/O 77
117,118,119,120,121, 122
I/O 78 - I/O 83
123,124,125,126,127, 128
I/O 84 - I/O 89
2,
3,
4,
5,
6,
7
I/O 90 - I/O 95
8,
9, 10, 11, 12, 13
Ground (GND)
V
CC
GND
1, 17, 33, 49, 65, 81
97, 112
VCC
16, 48, 82, 113
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
RESET
19
Y0
15
Y1
83
Y2
80
Y3
79
ispEN
18
SDI/IN 0
1
20
MODE/IN 1
1
46
SDO/IN 3
1
50
SCLK/IN 5
1
78
IN 2, IN 4
47, 51
IN 6 - IN 11
84,110,111, 115,116, 14
Dedicated input pins to the device.
GOE0, GOE1
64, 114
Global output enables for all I/Os.
Table 2- 0002C-48C
NAME
DESCRIPTION
1. Pins have dual function capability.
Specifications
ispLSI 1048C
11
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Pin Description
GND
B2,
B8, B13,
C8,
H3, H12,
M8,
N2,
N8
VCC
C7, G2,
G3, G12, G13,
M7,
N7
I/O 0 - I/O 5
J2,
J3,
K1,
L1,
K2,
M1,
I/O 6 - I/O 11
L2,
K3,
N1,
M2,
L3,
P1,
I/O 12 - I/O 17
M3,
P2,
N3,
M4,
P3,
N4,
I/O 18 - I/O 23
P4,
M5,
N5, P5,
M6,
N6,
I/O 24 - I/O 29
N9,
M9, P10, P11, N10, P12,
I/O 30 - I/O 35
N11, M10, P13, N12, M11, P14,
I/O 36 - I/O 41
M12, N14, M13, L12, M14, L13,
I/O 42 - I/O 47
L14, K12, K13, K14, J12, J13,
I/O 48 - I/O 53
F13, F12, E14, D14, E13, C14,
I/O 54 - I/O 59
D13, E12, B14, C13, D12, A14,
I/O 60 - I/O 65
C12, A13, B12, C11, A12, B11,
I/O 66 - I/O 71
A11, C10, B10, A10,
C9,
B9,
I/O 72 - I/O 77
B6,
C6,
A5,
A4,
B5,
A3,
I/O 78 - I/O 83
B4,
C5,
A2,
B3,
C4,
A1,
I/O 84 - I/O 89
C3,
B1,
C2,
D3,
C1,
D2,
I/O 90 - I/O 95
D1,
E3,
E2,
E1,
F3,
F2
RESET
H1
Y0
G1
Y1
G14
Y2
H13
Y3
H14
IN 2, IN 4
P7,
P9
IN 6 - IN 11
F14,
A9,
A8,
A7,
A6,
F1
GOE0, GOE1
N13,
B7,
Input Dedicated in-system programming enable input pin. This
pin is brought low to enable the programming mode. The MODE,
SDI, SDO and SCLK options become active.
Input This pin performs two functions. It is a dedicated input pin
when
ispEN
is logic high. When
ispEN
is logic low, it functions as
an input pin to load programming data into the device. SDI/IN 0
also is used as one of the two control pins for the isp state machine.
Input This pin performs two functions. It is a dedicated input pin
when
ispEN
is logic high. When
ispEN
is logic low, it functions as
a pin to control the operation of the isp state machine.
Input/Output This pin performs two functions. It is a dedicated
input pin when
ispEN
is logic high. When
ispEN
is logic low, it
functions as an output pin to read serial shift register data.
Input This pin performs two functions. It is a dedicated input
when
ispEN
is logic high. When
ispEN
is logic low, it functions as
a clock pin for the Serial Shift Register.
Input/Output Pins - These are the general purpose I/O pins used
by the logic array.
Ground (GND)
V
CC
Active Low (0) Reset pin which resets all of the GLB and I/O
registers in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on
the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/
or any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on
the device.
Dedicated input pins to the device.
Global output enables for all I/Os.
Table 2- 0002C-48C/CPGA
DESCRIPTION
NAME
CPGA PIN NUMBERS
ispEN
H2
SDI/IN 0
1
J1
MODE/IN 1
1
P6
SDO/IN 3
1
P8
SCLK/IN 5
1
J14
1. Pins have dual function capability.
Specifications
ispLSI 1048C
12
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Pin Configuration
ispLSI 1048C 128-Pin PQFP Pinout Diagram
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN11
Y0
VCC
GND
ispEN
RESET
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
GND
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
IN 5/SCLK1
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
IN 9
VCC
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
1
MODE/IN 1
VCC
GND
1
SDO/IN 3
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
ispLSI 1048C
Top View
I/O 10
1 SDI/IN 0
I/O 59
GND
Y3
GND
GND
IN 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
128
127
126
125
124
123
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
64
96
122
GOE 0
GOE 1
0124-48C
1. Pins have dual function capability.
Specifications
ispLSI 1048C
13
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Pin Configuration
ispLSI 1048C 133-Pin CPGA Pinout Diagram
I/O59
I/O56
I/O53
I/O51
I/O50
IN6
Y1
Y3
I/O40
I/O37
I/O35
I/O61
GND
I/O57
I/O54
I/O52
I/O48
Vcc
Y2
I/O38
GOE0
I/O32
I/O64
I/O62
I/O55
I/O49
Vcc
I/O33
I/O29
IN8
GND
GND
SDO/
IN31
IN9
GOE1
Vcc
Vcc
Vcc
IN2
IN10
I/O72
I/O73
I/O22
I/O23
MODE/
IN11
I/O74
I/O76
I/O79
I/O19
I/O20
I/O21
I/O75
I/O78
I/O17
I/O18
I/O77
I/O81
I/O84
I/O91
I/O94
Vcc
I/O14
I/O16
I/O80
GND
I/O86
I/O89
I/O92
I/O95
Vcc
I/O9
GND
I/O13
I/O83
I/O85
I/O88
I/O90
I/O93
IN11
Y0
I/O5
I/O8
I/O11
ispLSI 1048C/883
Bottom View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1
133 CPGA Pinout.eps
I/O66
I/O65
I/O69
I/O68
IN7
I/O71
I/O30
I/O27
I/O28
I/O26
I/O24
IN4
I/O15
I/O12
I/O67
I/O70
GND
I/O60
I/O63
I/O82
I/O87
I/O58
GND
I/O1
I/O7
I/O10
I/O0
I/O4
I/O6
SDI/
IN01
I/O2
I/O3
SCLK/
IN51
I/O45
I/O42
I/O47
I/O44
I/O41
I/O46
I/O43
I/O39
I/O36
I/O34
I/O31
I/O25
GND
INDEX
GND
RESET
ispEN
1. Pins have dual function capability.
Specifications
ispLSI 1048C
14
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
COMMERCIAL
INDUSTRIAL
t
pd (ns)
f
max (MHz)
Ordering Number
Package
70
16
ispLSI 1048C-70LQ
128-Pin PQFP
50
22
128-Pin PQFP
Family
ispLSI
ispLSI 1048C-50LQ
t
pd (ns)
f
max (MHz)
Ordering Number
Package
50
22
ispLSI 1048C-50LQI
128-Pin PQFP
ispLSI
Family
MILITARY
t
pd (ns)
f
max (MHz)
Ordering Number
Package
50
22
ispLSI 1048C-50LG/883
133-Pin CPGA
ispLSI
Family
SMD Number
5962-9558701MXC
Table 2- 0041A-48C-isp
Ordering Information
Part Number Description
Grade
Blank = Commercial
I = Industrial
/883 = 883 Military Process
Device Number
1048C
XX
X
X
X
Speed
70 = 70 MHz
f
max
50 = 50 MHz
f
max
Power
L = Low
Package
Q = PQFP
G = CPGA
--
Device Family
0212-80B-isp1048C
ispLSI
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