ispLSI

1048EA

In-System Programmable High Density PLD

1048ea_03

Functional Block Diagram

Features

· HIGH DENSITY PROGRAMMABLE LOGIC

-- 8,000 PLD Gates
-- 96 I/O Pins, Eight Dedicated Inputs
-- 288 Registers
-- High-Speed Global Interconnects
-- Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

-- Small Logic Block Size for Random Logic
-- Functionally Compatible with ispLSI 1048C and 1048E

· NEW FEATURES

-- 100% IEEE 1149.1 Boundary Scan Testable
-- ispJTAGTM In-System Programmable Via IEEE 1149.1

(JTAG) Test Access Port

-- User Selectable 3.3V or 5V I/O supports Mixed

Voltage Systems (V

CCIO

Pin)

-- Open Drain Output Option

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

max = 170 MHz Maximum Operating Frequency

pd = 5.0 ns Propagation Delay

-- TTL Compatible Inputs and Outputs
-- Electrically Eraseable and Reprogrammable
-- Non-Volatile
-- 100% Tested at Time of Manufacture

· IN-SYSTEM PROGRAMMABLE

-- Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

-- Reprogram Soldered Devices for Faster Prototyping

· OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS

-- Complete Programmable Device Can Combine Glue

Logic and Structured Designs

-- Enhanced Pin Locking Capability
-- Four Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control to

Minimize Switching Noise

-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global

Interconnectivity

· ispDesignEXPERTTM LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZERTM

-- PC and UNIX Platforms

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

CLK

E7 E6 E5 E4 E3 E2 E1 E0

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

Logic

Array

D Q

Global Routing Pool (GRP)

GLB

0139A/1048EA

Description

The ispLSI 1048EA is a High Density Programmable
Logic Device containing 288 Registers, 96 Universal I/O
pins, eight Dedicated Input pins, four Dedicated Clock
Input pins, two dedicated Global OE input pins, and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 1048EA features 5V in-system programmability
and in-system diagnostic capabilities via IEEE 1149.1
Test Access Port. The ispLSI 1048EA offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect to provide truly reconfigurable systems. A functional
superset of the ispLSI 1048 architecture, the ispLSI
1048EA device adds user selectable 3.3V or 5V I/O and
open-drain output options.

The basic unit of logic on the ispLSI 1048EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1...F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

June 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Specifications

ispLSI 1048EA

Functional Block Diagram

Figure 1. ispLSI 1048EA Functional Block Diagram

The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered
input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source
2mA or sink 8mA. Each output can be programmed
independently for fast or slow output slew rate to
minimize overall output switching noise. By connecting
the VCCIO pin to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat-
ible voltages.

Eight GLBs, 16 I/O cells, dedicated inputs (if available)
and one ORP are connected together to make a
Megablock (Figure 1). The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1048EA device contains six Megablocks.

The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 1048EA device are selected using
the Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0). The logic
of this GLB allows the user to create an internal clock
from a combination of internal signals within the device.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 1048EA are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

Generic

Logic Blocks

(GLBs)

Megablock

Input Bus

Global

Routing

Pool

(GRP)

CLK 0

CLK 1
CLK 2
IOCLK 0
IOCLK 1

Clock

Distribution

Network

Output Routing Pool (ORP)

I/O

IN
11

I/O

IN
10

I/O

Y
0

Y
1

Y
2

Y
3

I/O

IN 7
IN 6

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58
I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

I/O 0
I/O 1

I/O 2

I/O 3

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13
I/O 14

I/O 15

TDI

TDO

TMS

TCK

I/O 4

I/O 5

VCCIO

RESET

Input Bus

lnput Bus

0139F/1048EA

GOE 0

GOE 1

IN 2

Specifications

ispLSI 1048EA

Symbol

Parameter

Min

Max

Units

btcp

TCK [BSCAN test] clock pulse width

100

btch

TCK [BSCAN test] pulse width high

tbtcl

TCK [BSCAN test] pulse width low

tbtsu

TCK [BSCAN test] setup time

tbth

TCK [BSCAN test] hold time

trf

TCK [BSCAN test] rise and fall time

mV/ns

tbtco

TAP controller falling edge of clock to valid output

tbtoz

TAP controller falling edge of clock to data output disable

tbtvo

TAP controller falling edge of clock to data output enable

tbtcpsu

BSCAN test Capture register setup time

tbtcph

BSCAN test Capture register hold time

tbtuco

BSCAN test Update reg, falling edge of clock to valid output

tbtuoz

BSCAN test Update reg, falling edge of clock to output disable

tbtuov

BSCAN test Update reg, falling edge of clock to output enable

Figure 2. Boundary Scan Waveforms and Timing Specifications

TMS

TDI

TCK

TDO

Data to be

captured

Data to be

driven out

Valid Data

Data Captured

btsu

bth

btcl

btch

btcp

btvo

btco

btoz

btcpsu

btcph

btuov

btuco

btuoz

Boundary Scan

Specifications

ispLSI 1048EA

Absolute Maximum Ratings

Supply Voltage V

. ................................. -0.5 to +7.0V

Input Voltage Applied ........................ -2.5 to V

+1.0V

Off-State Output Voltage Applied ..... -2.5 to V

+1.0V

Storage Temperature ................................ -65 to 150

Case Temp. with Power Applied .............. -55 to 125

Max. Junction Temp. (T

) with Power Applied ... 150

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

Capacitance (T

=25

C, f=1.0 MHz)

Erase/Reprogram Specifications

SYMBOL

Table 2-0006/1048EA

PARAMETER

Y0 Clock Capacitance

UNITS

TYPICAL

TEST CONDITIONS

Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance

V = 5.0V, V = 2.0V

= 0

C to + 70

SYMBOL

Table 2-0005/1048EA

CCIO

PARAMETER

Supply Voltage

Supply Voltage: Output Drivers

Input High Voltage

Input Low Voltage

MIN.

MAX.

UNITS

4.75

3.0

2.0

5.25

3.6

0.8

Commercial

3.3V

Table 2-0008/1048EA

PARAMETER

MINIMUM

MAXIMUM

UNITS

Erase/Reprogram Cycles

10000

Cycles

Specifications

ispLSI 1048EA

Switching Test Conditions

DC Electrical Characteristics

Over Recommended Operating Conditions

Output Load Conditions (see Figure 3)

Figure 3. Test Load

Input Pulse Levels

Table 2-0003/1048EA

Input Rise and Fall Time 10% to 90%

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to 3.0V

1.5V

See Figure 3

3-state levels are measured 0.5V from
steady-state active level.

1.5ns

+ 5V

Device

Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

0213a

TEST CONDITION

470

390

35pF

390

35pF

470

390

35pF

Active High

Active Low

470

390

5pF

390

5pF

Active Low to Z
at V +0.5V

Active High to Z
at V -0.5V

Table 2-0004a

SYMBOL

1. One output at a time for a maximum duration of one second. V

OUT

= 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.
2. Meaured using eight 16-bit counters.
3. Typical values are at V

= 5V and T

= 25

4. Unused inputs held at 0.0V.
5. Maximum I

varies widely with specific device configuration and operating frequency. Refer to the

Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book CD-ROM to estimate maximum I

Table 2-0007/1048EA

PARAMETER

IL-PU

2, 4, 5

Output Low Voltage

Output High Voltage

Input or I/O Low Leakage Current

Operating Power Supply Current

= 8 mA

(Max.)

= 0.0V, V

= 3.0V

CONDITION

MIN.

TYP.

MAX. UNITS

2.4

0.4

-10

2.4

Input or I/O High Leakage Current

CCIO

5.25V

CCIO

- 0.2)V

CCIO

I/O Active Pull-Up Current

-200

Output Short Circuit Current

CCIO

= 5.0V or 3.3V, V

OUT

= 0.5V

-240

190

TOGGLE

= 1 MHz

= -2 mA, V

CCIO

= 3.0V

= -4 mA, V

CCIO

= 4.75V

Specifications

ispLSI 1048EA

External Timing Parameters

Over Recommended Operating Conditions

pd1

UNITS

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model

in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.

Table 2-0030A/1048EA

v.2.0

1
tsu2 + tco1

( )

DESCRIPTION

PARAMETER

Data Propagation Delay, 4PT Bypass, ORP Bypass

pd2

Data Propagation Delay, Worst Case Path

max (Int.)

Clock Frequency with Internal Feedback

MHz

max (Ext.)

Clock Frequency with External Feedback

MHz

max (Tog.)

Clock Frequency, Max. Toggle

MHz

su1

GLB Reg. Setup Time before Clock,4 PT Bypass

co1

GLB Reg. Clock to Output Delay, ORP Bypass

GLB Reg. Hold Time after Clock, 4 PT Bypass

su2

GLB Reg. Setup Time before Clock

co2

GLB Reg. Clock to Output Delay

GLB Reg. Hold Time after Clock

Ext. Reset Pin to Output Delay

rw1

Ext. Reset Pulse Duration

ptoeen

Input to Output Enable

ptoedis

Input to Output Disable

External Synchronous Clock Pulse Duration, High

External Synchronous Clock Pulse Duration, Low

su3

I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)

I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

( )

1
twh + twl

goeen

Global OE Output Enable

goedis

Global OE Output Disable

-125

MIN. MAX.

7.5

125

0.0

5.5

0.0

5.0

3.0

0.0

100

167

4.5

5.5

10.0

12.0

10.0

7.0

-170

MIN. MAX.

5.0

170

0.0

4.5

0.0

4.0

2.25

3.0

0.0

125

222

3.5

4.5

7.0

9.0

7.0

6.5

-100

MIN. MAX.

10.0

100

4.0

125

6.0

0.0

7.0

0.0

6.5

3.5

0.0

12.5

6.0

7.0

13.5

15.0

9.0

Specifications

ispLSI 1048EA

Internal Timing Parameters

iobp

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.

Table 2-0036A/1048EA

v.2.0

Inputs

UNITS

DESCRIPTION

PARAMETER

22 I/O Register Bypass

iolat

23 I/O Latch Delay

grp1

29 GRP Delay, 1 GLB Load

GLB

1ptxor

36 1 Product Term/XOR Path Delay

20ptxor

37 20 Product Term/XOR Path Delay

xoradj

38 XOR Adjacent Path Delay

gbp

39 GLB Register Bypass Delay

gsu

40 GLB Register Setup Time before Clock

41 GLB Register Hold Time after Clock

gco

42 GLB Register Clock to Output Delay

gro

43 GLB Register Reset to Output Delay

ptre

44 GLB Product Term Reset to Register Delay

ptoe

45 GLB Product Term Output Enable to I/O Cell Delay

ptck

46 GLB Product Term Clock Delay

gfb

47 GLB Feedback Delay

ORP

GRP

4ptbpc

34 4 Product Term Bypass Path Delay (Combinatorial)

4ptbpr

35 4 Product Term Bypass Path Delay (Registered)

orp

48 ORP Delay

orpbp

49 ORP Bypass Delay

iosu

24 I/O Register Setup Time before Clock

ioh

25 I/O Register Hold Time after Clock

ioco

26 I/O Register Clock to Out Delay

ior

27 I/O Register Reset to Out Delay

din

28 Dedicated Input Delay

grp4

30 GRP Delay, 4 GLB Loads

grp8

31 GRP Delay, 8 GLB Loads

grp16

32 GRP Delay, 16 GLB Loads

grp48

33 GRP Delay, 48 GLB Loads

-100

MIN. MAX.

-170

MIN. MAX.

0.3

4.0

1.4

2.3

2.2

1.0

2.1

2.0

0.3

2.0

1.4

4.7

2.7

3.6

1.7

2.7

1.0

0.1

3.0

0.0

4.6

1.8

1.6

1.8

2.2

3.8

-125

MIN. MAX.

0.3

3.5

2.8

3.0

0.0

0.3

4.0

1.7

3.6

1.2

1.4

4.9

3.8

5.2

3.4

3.1

3.9

1.3

0.2

4.6

1.9

2.1

2.5

4.1

0.3

4.8

3.5

3.4

0.0

0.4

4.0

2.1

4.3

2.1

1.7

5.0

4.5

7.2

0.1

0.6

1.4

4.9

4.7

1.4

0.4

5.0

2.2

2.3

2.5

2.9

4.5

Specifications

ispLSI 1048EA

Internal Timing Parameters

1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.

Table 2-0037A/1048EA

v.2.0

Outputs

UNITS

-100

MIN. MAX.

DESCRIPTION

PARAMETER

50 Output Buffer Delay

oen

52 I/O Cell OE to Output Enabled

gy0

55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

Global Reset

Clocks

60 Global Reset to GLB and I/O Registers

odis

53 I/O Cell OE to Output Disabled

gy1/2

56 Clock Delay, Y1 or Y2 to Global GLB Clock Line

gcp

57 Clock Delay, Clock GLB to Global GLB Clock Line

ioy2/3

58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

iocp

59 Clock Delay, Clock GLB to I/O Cell Global Clock Line

goe

54 Global OE

51 Output Slew Limited Delay Adder

-125

MIN. MAX.

-170

MIN. MAX.

0.9

3.3

0.9

0.4

3.3

0.9

0.8

1.8

0.0

0.8

2.8

2.6

1.1

0.9

0.8

0.0

0.8

1.7

4.0

1.1

2.1

4.0

0.9

1.8

0.0

2.8

3.0

6.0

1.9

1.5

0.8

0.0

0.8

2.0

5.1

1.9

5.1

1.5

1.8

0.0

2.8

3.9

6.0

Specifications

ispLSI 1048EA

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

0491/1048EA

Feedback

#47

Reg 4 PT Bypass

20 PT

XOR Delays

Control
PTs

Input

Clock

Distribution

I/O Pin

(Input)

Y1,2,3

GRP4

GLB Reg Bypass

ORP Bypass

RST

I/O Reg Bypass

I/O Cell

ORP

GLB

GRP

I/O Cell

#23 - 27

#30

#35

#34 Comb 4 PT Bypass

#36 - 38

#56 - 59

#44 - 46

#55

#54

#48

#49

Reset

Ded. In

GOE 0,1

#28

#22

RST

#60

#39

#40 - 43

#52, 53

#50, 51

GRP Loading

Delay

#29, 31 - 33

Derivations of

su,

h and

co from the Product Term Clock

=
=
=
=

Logic + Reg su - Clock (min)
(

iobp +

grp4 +

20ptxor) + (

gsu) - (

iobp +

grp4 +

ptck(min))

(#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
(0.3 + 1.6 + 2.2) + (0.3) - (0.3 + 1.6 + 1.7)

0.8

2.5

7.9

1.3

2.0

7.4

=
=
=
=

Clock (max) + Reg h - Logic
(

iobp +

grp4 +

ptck(max)) + (

gh) - (

iobp +

grp4 +

20ptxor)

(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 1.6 + 2.7) + (2.0) - (0.3 + 1.6 + 2.2)

=
=
=
=

Clock (max) + Reg co + Output
(

iobp +

grp4 +

ptck(max)) + (

gco) + (

orp +

ob)

(#22 + #30 + #46) + (#42) + (#48 + #50)
(0.3 + 1.6 + 2.7) + (1.4) + (1.0 + 0.9)

Table 2-0042/1048EA

v.2.0

Derivations of

su,

h and

co from the Clock GLB

=
=
=
=

Logic + Reg (setup) - Clock (min)
(

iobp +

grp4 +

20ptxor) + (

gsu) - (

gy0(min) +

gco +

gcp(min))

(#22 + #30 + #37) + (#40) - (#55 + #42 + #57)
(0.3 + 1.6 + 2.2) + (0.3) - (0.9 + 1.4 + 0.8)

=
=
=
=

Clock (max) + Reg (hold) - Logic
(

gy0(max) +

gco +

gcp(max)) + (

gh) - (

iobp +

grp4 +

20ptxor)

(#55 + #42 + #57) + (#41) - (#22 + #30 + #37)
(0.9 + 1.4 + 1.8) + (2.0) - (0.3 + 1.6 + 2.2)

=
=
=
=

Clock (max) + Reg(clock-to-out) + Output
(

gy0(max) +

gco +

gcp(max)) + (

gco) + (

orp +

ob)

(#55 + #42 + #57) + (#42) + (#48 + #50)
(0.9 + 1.4 + 1.8) + (1.4) + (1.0 + 0.9)

1. Calculations are based upon timing specifications for the ispLSI 1048EA-170.

ispLSI 1048EA Timing Model

Specifications

ispLSI 1048EA

0127/1048EA

Icc can be estimated for the ispLSI 1048EA using the following equation:

Icc = 20mA + (# of PTs * .45) + (# of nets * Max Freq * .0087)

Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)

The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating
conditions and the program in the device, the actual Icc should be verified.

fmax (MHz)

Notes: Configuration of twelve 16-bit counters, Typical current at 5V, 25¡C

400

300

200

100

125

150

175

I CC (mA)

ispLSI 1048EA

500

Power Consumption

Power consumption in the ispLSI 1048EA device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms

used. Figure 4 shows the relationship between power
and operating speed.

Figure 4. Typical Device Power Consumption vs fmax

Package Thermal Characteristics

For the ispLSI 1048EA-170, it is strongly recommended
that the actual Icc be verified to ensure that the maximum
junction temperature (T

) with power supplied is not

exceeded. Depending on the specific logic design and
clock speed, airflow may be required to satisfy the maxi-

mum allowable junction temperature (T

) specification.

Please refer to the Thermal Management section of the
Lattice Semiconductor Data Book or CD-ROM for addi-
tional information on calculating T

Maximum GRP Delay vs. GLB Loads

GLB Load

GRP Delay (ns)

GRP/GLB/1048EA

ispLSI 1048EA-170

ispLSI 1048EA-125

ispLSI 1048EA-100

Specifications

ispLSI 1048EA

Pin Description

Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.

Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.

Input/Output Pins - These are the general purpose I/O pins used by the
logic array.

NAME

Table 2-0002C/1048EA

PQFP / TQFP PIN NUMBERS

DESCRIPTION

21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,

22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,

23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,

I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95

24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,

25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,

TMS

Input - Controls the operation of the ISP JTAG state machine.

Ground (GND)

GND

VCC

26,
32,
39,
45,
57,
63,
71,
77,
90,
96,
103,
109,
122,
128,
7,
13

Global Output Enable input pins.

GOE0, GOE1

Dedicated input pins to the device.

IN 2, IN 4, IN 6-IN 11

64,

114

47,

84,

110,

111,

115,

116,

Input - Functions as an input pin to load programming data into the
device and also is used as one of the two control pins for the ISP JTAG
state machine.

TDI

TDO

Output - Functions as an output pin to read serial shift register data.

TCK

Input - Functions as a clock pin for the Serial Shift Register.

Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.

RESET

Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.

Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.

1,
97,

17,
112

33,

49,

65,

81,

16,

48,

82,

113

Supply voltage for output drivers, 5V or 3.3V.

VCCIO

Specifications

ispLSI 1048EA

I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95

IN 11

VCC

GND

VCCIO

RESET

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9

GND

I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2

TCK

I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36

I/O 83

I/O 82

I/O 81

I/O 80

I/O 79

I/O 78

I/O 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

IN 10

IN 9

VCC

IN 8

IN 7

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 65

I/O 64

I/O 63

I/O 62

I/O 61

I/O 60

GND

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

TMS

VCC

GND

TDO

IN 4

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 32

I/O 33

I/O 34

I/O 35

ispLSI 1048EA

Top View

I/O 10

TDI

I/O 59

GND

IN 2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

20
21
22
23
24
25
26
27
28
29
30
31
32

33 34

95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

128

127

126

125

124

123

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

122

GOE 0

GOE 1

0124/1048EA

Pin Configuration

ispLSI 1048EA 128-Pin PQFP Pinout Diagram

Specifications

ispLSI 1048EA

Pin Configuration

ispLSI 1048EA 128-Pin TQFP Pinout Diagram

I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95

IN 11

VCC

GND

VCCIO

RESET

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9

GND

I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2

TCK
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36

I/O 83

I/O 82

I/O 81

I/O 80

I/O 79

I/O 78

I/O 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

IN 10

IN 9

VCC

IN 8

IN 7

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 65

I/O 64

I/O 63

I/O 62

I/O 61

I/O 60

GND

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

TMS

VCC

GND

TDO

IN 4

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 32

I/O 33

I/O 34

I/O 35

ispLSI 1048EA

Top View

I/O 10

TDI

I/O 59

GND

IN 2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

20
21
22
23
24
25
26
27
28
29
30
31
32

33 34

95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

128

127

126

125

124

123

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

122

GOE 0

GOE 1

128TQFP/1048EA

Specifications

ispLSI 1048EA

Part Number Description

ispLSI 1048EA Ordering Information

Grade
Blank = Commercial

Device Number

1048EA - XXX

XXXX

Speed
170 = 170 MHz

max

125 = 125 MHz

max

100 = 100 MHz

max

Power
L = Low

Package
Q128 = 128-Pin PQFP
T128 = 128-Pin TQFP

Device Family

0212/1048EA

ispLSI

Table 2-0041A/1048EA

FAMILY

fmax (MHz)

ORDERING NUMBER

PACKAGE

tpd (ns)

ispLSI

125

100

128-Pin PQFP

128-Pin TQFP

7.5

ispLSI 1048EA-125LQ128

ispLSI 1048EA-125LT128

170*

128-Pin PQFP

128-Pin TQFP

5.0

ispLSI 1048EA-170LQ128

ispLSI 1048EA-170LT128

128-Pin PQFP

ispLSI 1048EA-100LQ128

100

128-Pin TQFP

ispLSI 1048EA-100LT128

COMMERCIAL

*Note: Please refer to the Package Thermal Characteristics section of this data sheet for details.

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ispLSI1048EA-170LT128

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ispLSI1048EA-170LT128

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ispLSI1048EA-170LT128