Document Outline
- ispLSI 2032E Data Sheet
- DC Electrical Characteristics
- AC Characteristics
- Pin Configuration: 44 PLCC
- Pin Configuration: 44 TQFP
- Pin Configuration: 48 TQFP
- Ordering Information
2032e_04
1
ispLSI
2032E
In-System Programmable
SuperFASTTM High Density PLD
Features
SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
-- 1000 PLD Gates
-- 32 I/O Pins, Two Dedicated Inputs
-- 32 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
-- Small Logic Block Size for Random Logic
-- 100% Functionally and JEDEC Upward Compatible
with ispLSI 2032 Devices
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
--
f
max = 225 MHz Maximum Operating Frequency
--
t
pd = 3.5 ns Propagation Delay
-- TTL Compatible Inputs and Outputs
-- 5V Programmable Logic Core
-- ispJTAGTM In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
-- User-Selectable 3.3V or 5V I/O (48-Pin Package Only)
Supports Mixed Voltage Systems
-- PCI Compatible Outputs (48-Pin Package Only)
-- Open-Drain Output Option
-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- Unused Product Term Shutdown Saves Power
ispLSI OFFERS THE FOLLOWING ADDED FEATURES
-- Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
-- Reprogram Soldered Devices for Faster Prototyping
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
-- Complete Programmable Device Can Combine Glue
Logic and Structured Designs
-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control to
Minimize Switching Noise
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global
Interconnectivity
Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
A7
A6
A5
A4
Input Bus
Output Routing Pool (ORP)
A2
GLB
Logic
Array
D Q
D Q
D Q
D Q
0139Bisp/2000
Description
The ispLSI 2032E is a High Density Programmable Logic
Device. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2032E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2032E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
Specifications
ispLSI 2032E
2
Functional Block Diagram
Figure 1. ispLSI 2032E Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
A7
A6
A5
A4
Input Bus
Output Routing Pool (ORP)
A2
CLK 0
CLK 1
CLK 2
GOE 0
Notes:
*Y1 and RESET are multiplexed on the same pin
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
TDI/IN 0
TDO/IN 1
I/O 4
I/O 5
Y0
Y1*
TCK/Y2
BSCAN
TMS
0139/2032E
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro-
grammed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat-
ible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive (48-pin device
only).
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032E device contains one Megablock.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2032E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2032E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the Lattice software tools.
Specifications
ispLSI 2032E
3
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150
C
Case Temp. with Power Applied .............. -55 to 125
C
Max. Junction Temp. (T
J
) with Power Applied ... 150
C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
Capacitance (T
A
=25
C, f=1.0 MHz)
C
SYMBOL
Table 2-0006/2032E
C
PARAMETER
I/O Capacitance
UNITS
TEST CONDITIONS
1
2
Dedicated Input Capacitance
pf
pf
V = 5.0V, V = 2.0V
V = 5.0V, V = 2.0V
CC
CC
I/O
IN
C
Clock Capacitance
7
TYP
6
10
3
pf
V = 5.0V, V = 2.0V
CC
Y
Table 2-0008/2032E
PARAMETER
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
10,000
Cycles
T
A
= 0
C to +70
C
SYMBOL
Table 2-0005/2032E
V
CC
V
IH
V
IL
PARAMETER
Supply Voltage: Logic Core, Input Buffers
Input High Voltage
Input Low Voltage
1. 3.3V I/O operation not available for 44-pin packages.
MIN.
MAX.
UNITS
4.75
2.0
0
5.25
V
cc
+1
0.8
V
V
CCIO
1
Supply Voltage: Output Drivers
4.75
5.25
V
3.3V
5V
3.0
3.6
V
V
V
Erase/Reprogram Specification
Specifications
ispLSI 2032E
4
+ 5V
R1
R2
CL
*
Device
Output
Test
Point
*
CL includes Test Fixture and Probe Capacitance.
0213A
DC Electrical Characteristics
Over Recommended Operating Conditions
1
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
R2
CL
A
470
390
35pF
B
390
35pF
470
390
35pF
Active High
Active Low
C
470
390
5pF
390
5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2 - 0004A
Input Pulse Levels
Table 2-0003/2032E
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
1.5 ns
Figure 2. Test Load
V
OL
SYMBOL
1. One output at a time for a maximum duration of one second (V
OUT
= 0.5V). Characterized, but not 100% tested.
2. Meaured using two 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25
C.
4. Unused inputs held at 0.0V.
5. Available in 48-pin package only.
6. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum I
CC
.
Table 2-0007/2032E
V
OH
I
IH
I
IL
PARAMETER
I
IL-PU
I
OS
1
I
CC
2,4,6
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
I/O Active Pull-Up Current, non-PCI
Output Short Circuit Current, non-PCI
Operating Power Supply Current
I
OL
= 8 mA
I
OH
= -4 mA
0V
V
IN
V
IL
(Max.)
0V
V
IN
2.0V
V
CCIO
= 5V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 3.0V
CONDITION
MIN.
TYP.
3
MAX. UNITS
2.4
-10
0.4
10
-10
10
-150
-200
V
V
A
Input or I/O High Leakage Current
V
CCIO
V
IN
5.25V
(V
CCIO
- 0.2)V
V
IN
V
CCIO
A
A
A
I/O Active Pull-Up Current, PCI
5
0V
V
IN
2.0V
-10
-250
A
mA
Output Short Circuit Current, PCI
5
V
CCIO
= 5.0V or 3.3V, V
OUT
= 0.5V
-240
mA
85
mA
65
-225/-200
Others
mA
f
TOGGLE
= 1 MHz
Switching Test Conditions
Specifications
ispLSI 2032E
5
USE 2032E-225 FOR
NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
-200
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/2032E
1
1
tsu2 + tco1
( )
-180
MIN.
MAX.
MAX.
DESCRIPTION
#
2
4
PARAMETER
A
1
Data Prop. Delay, 4PT Bypass, ORP Bypass
3.5
5.0
ns
t
pd2
A
2
Data Prop. Delay
ns
f
max
A
3
Clk Frequency with Int. Feedback
3
200
180
MHz
f
max (Ext.)
4
Clk Frequency with Ext. Feedback
MHz
f
max (Tog.)
5
Clk Frequency, Max. Toggle
MHz
t
su1
6
GLB Reg. Setup Time before Clk, 4 PT Bypass
ns
t
co1
A
7
GLB Reg. Clk to Output Delay, ORP Bypass
ns
t
h1
8
GLB Reg. Hold Time after Clk, 4 PT Bypass
0.0
ns
t
su2
9
GLB Reg. Setup Time before Clk
3.5
ns
t
co2
10 GLB Reg. Clk to Output Delay
ns
t
h2
11 GLB Reg. Hold Time after Clk
0.0
ns
t
r1
A
12 Ext. Reset Pin to Output Delay, ORP Bypass
ns
t
rw1
13 Ext. Reset Pulse Duration
3.5
ns
t
ptoeen
B
14 Input to Output Enable
ns
t
ptoedis
C
15 Input to Output Disable
ns
t
goeen
B
16 Global OE Output Enable
ns
t
goedis
C
17 Global OE Output Disable
ns
t
wh
18 Ext. Synch. Clk Pulse Duration, High
2.0
ns
t
wl
19 Ext. Synch. Clk Pulse Duration, Low
2.0
ns
167
250
2.5
2.5
3.5
5.0
7.0
7.0
3.5
3.5
5.5
-225
MIN. MAX.
3.5
225
0.0
3.5
0.0
3.5
2.0
2.0
167
250
2.5
2.5
3.5
5.0
7.0
7.0
3.5
3.5
5.5
125
200
3.0
0.0
4.0
0.0
4.0
2.5
2.5
7.5
4.0
4.5
6.5
10.0
10.0
5.0
5.0
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