ispLSI

3256E

In-System Programmable High Density PLD

3256e_08

Features

· HIGH-DENSITY PROGRAMMABLE LOGIC

-- 256 I/O Pins
-- 12000 PLD Gates
-- 512 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

-- Small Logic Block Size for Random Logic

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

max = 100 MHz Maximum Operating Frequency

pd = 10 ns Propagation Delay

-- TTL Compatible Inputs and Outputs
-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- 100% Tested at Time of Manufacture
-- Unused Product Term Shutdown Saves Power

· IN-SYSTEM PROGRAMMABLE

-- 5V In-System Programmable (ISPTM) using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
-- Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

-- Reprogram Soldered Devices for Faster Debugging

· 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

· OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
-- Complete Programmable Device Can Combine Glue

Logic and Structured Designs

-- Five Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control to Mini-

mize Switching Noise

-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global

Interconnectivity

· ispDesignEXPERTTM LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZERTM

-- PC and UNIX Platforms

Functional Block Diagram

ORP

Global Routing Pool

ORP

Boundary

Scan

Array

D Q

Twin

GLB

Array

D Q

AND Array

ORP

0139A/3256E

ORP

Description

The ispLSI 3256E is a High Density Programmable Logic
Device containing 512 Registers, 256 Universal I/O pins,
five Dedicated Clock Input Pins, 16 Output Routing Pools
(ORP) and a Global Routing Pool (GRP) which allows
complete inter-connectivity between all of these ele-
ments. The ispLSI 3256E features 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256E offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.

The basic unit of logic on the ispLSI 3256E device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 Twin GLBs in the ispLSI 3256E
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays and eight
outputs which can be configured to be either combinato-
rial or registered. All Twin GLB inputs come from the
GRP.

Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

June 2002

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Specifications

ispLSI 3256E

Functional Block Diagram

Figure 1. ispLSI 3256E Functional Block Diagram

ORP

Global Routing Pool

(GRP)

CLK 1

CLK 0

CLK 2

IOCLK 1

IOCLK 0

GOE0

GOE1

TOE

ISP and

Boundary

Scan TAP

RESET

ORP

Input Bus

BSCAN/ispEN

TDI/SDI

TCLK/SCLK

TMS/MODE

TRST

TDO/SDO

0139isp/3256E

Generic

Logic

Blocks

I/O 24
I/O 26
I/O 28
I/O 30

I/O 25
I/O 27
I/O 29
I/O 31

I/O 8

I/O 10
I/O 12
I/O 14

I/O 9

I/O 11
I/O 13
I/O 15

I/O 0
I/O 2
I/O 4
I/O 6

I/O 1
I/O 3
I/O 5
I/O 7

I/O 16
I/O 18
I/O 20
I/O 22

I/O 17
I/O 19
I/O 21
I/O 23

I/O 96

I/O 98

I/O 100

I/O 102

I/O 97

I/O 99

I/O 101

I/O 103

I/O 104

I/O 106

I/O 108

I/O 110

I/O 105

I/O 107

I/O 109

I/O 111

I/O 112

I/O 114

I/O 116

I/O 118

I/O 113

I/O 115

I/O 117

I/O 119

I/O 120

I/O 122

I/O 124

I/O 126

I/O 121

I/O 123

I/O 125

I/O 127

I/O 88

I/O 90

I/O 92

I/O 94

I/O 80

I/O 82

I/O 84

I/O 86

I/O 72

I/O 74

I/O 76

I/O 78

I/O 64

I/O 66

I/O 68

I/O 70

I/O 65

I/O 67

I/O 89

I/O 91

I/O 93

I/O 95

I/O 81

I/O 83

I/O 85

I/O 87

I/O 73

I/O 75

I/O 77

I/O 79

I/O 69

I/O 71

I/O 56
I/O 58
I/O 60
I/O 62

I/O 57
I/O 59
I/O 61
I/O 63

I/O 48
I/O 50
I/O 52
I/O 54

I/O 49
I/O 51
I/O 53
I/O 55

I/O 40
I/O 42
I/O 44
I/O 46

I/O 41
I/O 43
I/O 45
I/O 47

I/O 32
I/O 34
I/O 36
I/O 38

I/O 33
I/O 35
I/O 37
I/O 39

I/O 190
I/O 188
I/O 186
I/O 184

I/O 191
I/O 189
I/O 187
I/O 185

I/O 182
I/O 180
I/O 178
I/O 176

I/O 183
I/O 181
I/O 179
I/O 177

I/O 166
I/O 164
I/O 162
I/O 160

I/O 167
I/O 165
I/O 163
I/O 161

I/O 174
I/O 172
I/O 170
I/O 168

I/O 175
I/O 173
I/O 171
I/O 169

I/O 158
I/O 156
I/O 154
I/O 152

I/O 159
I/O 157
I/O 155
I/O 153

I/O 150
I/O 148
I/O 146
I/O 144

I/O 151
I/O 149
I/O 147
I/O 145

I/O 134
I/O 132
I/O 130
I/O 128

I/O 135
I/O 133
I/O 131
I/O 129

I/O 142
I/O 140
I/O 138
I/O 136

I/O 143
I/O 141
I/O 139
I/O 137

I/O 254

I/O 252

I/O 250

I/O 248

I/O 255

I/O 253

I/O 251

I/O 249

I/O 246

I/O 244

I/O 242

I/O 240

I/O 247

I/O 245

I/O 243

I/O 241

I/O 230

I/O 228

I/O 226

I/O 224

I/O 231

I/O 229

I/O 227

I/O 225

I/O 238

I/O 236

I/O 234

I/O 232

I/O 239

I/O 237

I/O 235

I/O 233

I/O 222

I/O 220

I/O 218

I/O 216

I/O 223

I/O 221

I/O 219

I/O 217

I/O 214

I/O 212

I/O 210

I/O 208

I/O 215

I/O 213

I/O 211

I/O 209

I/O 198

I/O 196

I/O 194

I/O 192

I/O 199

I/O 197

I/O 195

I/O 193

I/O 206

I/O 204

I/O 202

I/O 200

I/O 207

I/O 205

I/O 203

I/O 201

Megablock

ORP

Specifications

ispLSI 3256E

Description (continued)

All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 256 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.

The 256 I/O Cells are grouped into 16 sets of 16 bits.
Pairs of these I/O groups are associated with a logic
Megablock through the use of the ORP. Each Megablock
is able to provide one Product Term Output Enable
(PTOE) signal which is globally distributed to all I/O cells.
That PTOE signal can be generated within any GLB in the
Megablock. Each I/O cell can select either a Global OE
or a PTOE.

Four Twin GLBs, 32 I/O Cells and two ORPs are con-
nected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of the four Twin GLBs are connected to a set of
32 I/O cells by the ORP. The ispLSI 3256E device
contains eight of these Megablocks.

The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equal-
ized to minimize timing skew and logic glitching.

Clocks in the ispLSI 3256E device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.

The table below lists key attributes of the device along
with the number of resources available.

An additional feature of the ispLSI 3256E is its Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device's input
and output pins. All I/O pins have associated boundary
scan registers, with 3-state I/O using three boundary
scan registers and inputs using one.

The ispLSI 3256E supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.

Key Attributes of the ispLSI 3256E

Specifications

ispLSI 3256E

Absolute Maximum Ratings

Supply Voltage V

........................................................................... -0.5 to +7.0V

Input Voltage Applied ........................................................................ -2.5 to V

+1.0V

Off-State Output Voltage Applied ..................................................... -2.5 to V

+1.0V

Storage Temperature ........................................................................ -65 to 150

Case Temp. with Power Applied ...................................................... -55 to 125

Max. Junction Temp. (T

) with Power Applied (304-Pin PQFP) ...... 150

Max. Junction Temp. (T

) with Power Applied (320-Ball BGA) ........ 140

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

Capacitance (T

=25

C,f=1.0 MHz)

SYMBOL

Table 2-0006/3256E

PARAMETER

Clock Capacitance

UNITS

TYPICAL

TEST CONDITIONS

V = 5.0V, V = 2.0V

I/O Capacitance

V = 5.0V, V = 2.0V

I/O

Data Retention Specifications

Table 2-0008/3256E

PARAMETER

Data Retention

MINIMUM

MAXIMUM

UNITS

ispLSI Erase/Reprogram Cycles

10000

Years

Cycles

SYMBOL

Table 2-0005/3256E

PARAMETER

Ambient Temperature

Supply Voltage

Input High Voltage

Input Low Voltage

MIN.

MAX.

UNITS

4.75

2.0

5.25

V +1

0.8

Specifications

ispLSI 3256E

Switching Test Conditions

Input Pulse Levels

Table 2-0003/3256E

Input Rise and Fall Time

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to 3.0V

3ns 10% to 90%

1.5V

See Figure 2

3-state levels are measured 0.5V from
steady-state active level.

Output Load conditions (See Figure 2)

TEST CONDITION

470

390

35pF

390

35pF

470

390

35pF

Active High

Active Low

470

390

5pF

390

5pF

Active Low to Z
at V +0.5V

Active High to Z
at V -0.5V

Table 2 - 0004A

Figure 2. Test Load

+ 5V

Device
Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

0213A

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using sixteen 16-bit counters.
3. Typical values are at V

= 5V and T

= 25

4. Maximum I

varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum I

Table 2 - 0007isp/3256E

IL-isp

PARAMETER

IL-PU

2,4

Output Low Voltage

Output High Voltage

Input or I/O High Leakage Current

Input or I/O Low Leakage Current

Bscan/ispEN Input Low Leakage Current

I/O Active Pull-Up Current

Output Short Circuit Current

Operating Power Supply Current

I = 8 mA

I = -4 mA

3.5V

V (Max.)

V = 5V, V = 0.5V

V = 0.0V, V = 3.0V
f = 1 MHz

IN IL

IN CC

IN IL

CC OUT

TOGGLE

IL IH

CONDITION

MIN.

TYP.

MAX.

UNITS

2.4

300

0.4

-10

-150

-200

OUT

Specifications

ispLSI 3256E

External Switching Characteristics

1, 2, 3

Over Recommended Operating Conditions

)

(

)

(

)

(

)

(

)

(

)

(

)

(

Specifications

ispLSI 3256E

Internal Timing Parameters

Over Recommended Operating Conditions

)

(

)

(

Specifications

ispLSI 3256E

Internal Timing Parameters

Over Recommended Operating Conditions

Specifications

ispLSI 3256E

ispLSI 3256E Timing Model

Note: Calculations are based upon timing specifications for the ispLSI 3256E-100L.

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

4 PT Bypass

20 PT

XOR Delays

Control
PTs

Input

I/O Pin

(Input)

Y0,1,2

Y3,4

GRP

GLB Reg Bypass

ORP Bypass

RST

I/O Reg Bypass

I/O Cell

ORP

GLB

GRP

I/O Cell

#25 - 29

#30

#32

#31

#33 - 35

#41 - 43

#50

#53

#54

#44

#45

Reset

#24

#51

RST

#52

#36

#37 - 40

#48, 49

#46, 47

GOE0,1

TOE

0902/3256E

Derivations of

su,

h and

co from the Product Term Clock

=
=
=
=

Logic + Reg su - Clock (min)
(

iobp +

grp +

20ptxor) + (

gsu) - (

iobp +

grp +

ptck(min))

(#24+ #30+ #34) + (#37) - (#24+ #30+ #43)
(2.4 + 2.3 + 4.1) + (0.3) - (2.4 + 2.3 + 3.0)

1.4 ns

=
=
=
=

Clock (max) + Reg h - Logic
(

iobp +

grp +

ptck(max)) + (

gh) - (

iobp +

grp +

20ptxor)

(#24+ #30+ #43) + (#38) - (#24+ #30+ #34)
(2.4 + 2.3 + 3.6) + (5.0) - (2.4 + 2.3 + 4.1)

4.5 ns

=
=
=
=

Clock (max) + Reg co + Output
(

iobp +

grp +

ptck(max)) + (

gco) + (

orp +

ob)

(#24 + #30 + #43) + (#39) + (#44 + #46)
(2.4 + 2.3 + 3.6) + (1.6) + (1.2 + 2.6)

13.7 ns

Table 2- 0042-3256E

Specifications

ispLSI 3256E

Power Consumption

Figure 3 shows the relationship between power and
operating speed.

Power consumption in the ispLSI 3256E device depends
on two primary factors: the speed at which the device is
operating and the number of product terms used.

0127/3256E

ICC can be estimated for the ispLSI 3256E using the following equation:

ICC = 60 + (# of PTs * 0.48) + (# of nets * Max. freq * 0.0106) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device

The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two
GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to
operating conditions and the program in the device, the actual ICC should be verified.

200

400

600

500

300

100

max (MHz)

(mA)

Notes: Configuration of 16 16-bit Counters
Typical Current at 5V, 25

ispLSI 3256E

Figure 3. Typical Device Power Consumption vs fmax

Specifications

ispLSI 3256E

Pin Locations

GOE0, GOE1

195, 185

AD11, AC14

TOE

215

AC6

RESET

A17

Y0, Y1, Y2, Y3, Y4 43, 33, 205, 175, 165

A14, B11, AD8, AB16, AA18

ispEN

/BSCAN

B19

SDI/TDI

SCLK/TCK

D20

MODE/TMS

TRST

/NC

225

AA5

SDO/TDO

155

AB21

GND

9, 19, 39, 49, 69, 85, 95, 115, 125, 145, 161, 171,

D6, C8, B13, A16, D19, F21, H22, N23, T24, W21,

191, 201, 221, 237, 247, 267, 277, 297

AA19, AB17, AC12, AD9, AA6, W4, U3, M2, J1, F4

VCC

1, 29, 59, 77, 105, 135, 153, 181, 211, 229, 257,

D4, B10, B18, D21, K23, V23, AA21, AC15, AC7,

287, 304

AA4, R2, G2, C3

A1, A2, A23, A24, B1, B2, B23, B24, AC1, AC2,
AC23, AC24, AD1, AD2, AD23, AD24

Pin Description

Signal 304-Pin PQFP 320-Ball BGA

I/O

Input/Output pins These are the general purpose I/O pins used by the logic array.

GOE0, GOE1

Global Output Enable input pins.

TOE

Test Output Enable pin This pin tristates all I/O pins when a logic low is driven.

RESET

Active Low (0) Reset pin Resets all of the GLB and I/O registers in the device.

Y0, Y1, Y2

Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on
the device.

Y3, Y4

Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells
on the device.

BSCAN/

ispEN

Input Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP
controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP State
Machine control pins MODE, SDI, SDO and SCLK are enabled. High-to-low transition of this pin will put
the device in the programming mode and put all I/O pins in the high-Z state.

TDI/SDI

Input This pin performs two functions. It is the Test Data input pin when

ispEN

is logic high. When

ispEN

is logic low, it functions as an input pin to load programming data into the device. SDI is also

used as one of the two control pins for the ISP State Machine.

TCK/SCLK

Input This pin performs two functions. It is the Test Clock input pin when

ispEN

is logic high. When

ispEN

is logic low, it functions as a clock pin for the Serial Shift Register.

TMS/MODE

Input This pin performs two functions. It is the Test Mode Select input pin when

ispEN

is logic high.

When

ispEN

is logic low, it functions as a pin to control the operation of the ISP State Machine.

TRST

/NC

Input Test Reset, active low to reset the Boundary Scan State Machine.

TDO/SDO

Output This pin performs two functions. When

ispEN

is logic low, it functions as the pin to read the

ISP data. When

ispEN

is high, it functions as Test Data Out.

GND

Ground (GND)

VCC

Vcc

No Connect.

Pin Name Description

1. NC pins are not to be connected to any active signals, VCC or GND.

Specifications

ispLSI 3256E

I/O 0

C13

I/O 1

D13

I/O 2

A13

I/O 3

B14

I/O 4

C14

I/O 5

D14

I/O 6

A15

I/O 7

B15

I/O 8

C15

I/O 9

D15

I/O 10

B16

I/O 11

C16

I/O 12

B17

I/O 13

D16

I/O 14

A18

I/O 15

C17

I/O 16

A19

I/O 17

D17

I/O 18

C18

I/O 19

A20

I/O 20

D18

I/O 21

C19

I/O 22

B20

I/O 23

A21

I/O 24

C20

I/O 25

B21

I/O 26

A22

I/O 27

C21

I/O 28

B22

I/O 29

C22

I/O 30

C23

I/O 31

D22

I/O 32

C24

I/O 33

E21

I/O 34

D23

I/O 35

E22

I/O 36

D24

I/O 37

E23

I/O 38

F22

I/O 39

E24

I/O 40

G21

I/O 41

F23

I/O 42

G22

I/O 43

F24

I/O 44

H21

I/O 45

G23

I/O 46

G24

I/O 47

J21

I/O 48

H23

I/O 49

J22

I/O 50

100

H24

I/O 51

101

J23

I/O 52

102

K21

I/O 53

103

K22

I/O 54

104

J24

I/O 55

106

K24

I/O 56

107

L21

I/O 57

108

L22

I/O 58

109

L23

I/O 59

110

L24

I/O 60

111

M24

I/O 61

112

M21

I/O 62

113

M22

I/O 63

114

M23

I/O 64

116

N22

I/O 65

117

N21

I/O 66

118

N24

I/O 67

119

P24

I/O 68

120

P23

I/O 69

121

P22

I/O 70

122

P21

I/O 71

123

R24

I/O 72

124

R23

I/O 73

126

R22

I/O 74

127

R21

I/O 75

128

T23

I/O 76

129

U24

I/O 77

130

T22

I/O 78

131

U23

I/O 79

132

T21

I/O 80

133

V24

I/O 81

134

U22

I/O 82

136

W24

I/O 83

137

U21

I/O 84

138

V22

I/O 85

139

W23

I/O 86

140

Y24

I/O 87

141

V21

I/O 88

142

W22

I/O 89

143

Y23

I/O 90

144

AA24

I/O 91

146

Y22

I/O 92

147

AA23

I/O 93

148

AB24

I/O 94

149

Y21

I/O 95

150

AA22

I/O 96

151

AB23

I/O 97

152

AB22

I/O 98

154

AC22

I/O 99

156

AD22

I/O 100 157

AA20

I/O 101 158

AC21

I/O 102 159

AB20

I/O 103 160

AD21

I/O 104 162

AC20

I/O 105 163

AB19

I/O 106 164

AD20

I/O 107 166

AC19

I/O 108 167

AB18

I/O 109 168

AD19

I/O 110 169

AA17

I/O 111 170

AC18

I/O 112 172

AD18

I/O 113 173

AA16

I/O 114 174

AC17

I/O 115 176

AD17

I/O 116 177

AC16

I/O 117 178

AA15

I/O 118 179

AB15

I/O 119 180

AD16

I/O 120 182

AD15

I/O 121 183

AA14

I/O 122 184

AB14

I/O 123 186

AD14

I/O 124 187

AD13

I/O 125 188

AA13

I/O 126 189

AB13

I/O 127 190

AC13

I/O 128 192

AB12

I/O 129 193

AA12

I/O 130 194

AD12

I/O 131 196

AC11

I/O 132 197

AB11

I/O 133 198

AA11

I/O 134 199

AD10

I/O 135 200

AC10

I/O 136 202

AB10

I/O 137 203

AA10

I/O 138 204

AC9

I/O 139 206

AB9

I/O 140 207

AC8

I/O 141 208

AA9

I/O 142 209

AD7

I/O 143 210

AB8

I/O 144 212

AD6

I/O 145 213

AA8

I/O 146 214

AB7

I/O 147 216

AD5

I/O 148 217

AA7

I/O 149 218

AB6

I/O 150 219

AC5

I/O 151 220

AD4

I/O 152 222

AB5

I/O 153 223

AC4

I/O 154 224

AD3

I/O 155 226

AB4

I/O 156 227

AC3

I/O 157 228

AB3

I/O 158 230

AB2

I/O 159 231

AA3

I/O 160 232

AB1

I/O 161 233

I/O 162 234

AA2

I/O 163 235

I/O 164 236

AA1

I/O 165 238

I/O 166 239

I/O 167 240

I/O 168 241

I/O 169 242

I/O 170 243

I/O 171 244

I/O 172 245

I/O 173 246

I/O 174 248

I/O 175 249

I/O 176 250

I/O 177 251

I/O 178 252

I/O 179 253

I/O 180 254

I/O 181 255

I/O 182 256

I/O 183 258

I/O 184 259

I/O 185 260

I/O 186 261

I/O 187 262

I/O 188 263

I/O 189 264

I/O 190 265

I/O 191 266

I/O 192 268

I/O 193 269

I/O 194 270

I/O 195 271

I/O 196 272

I/O 197 273

I/O 198 274

I/O 199 275

I/O 200 276

I/O 201 278

I/O 202 279

I/O 203 280

I/O 204 281

I/O 205 282

I/O 206 283

I/O 207 284

I/O 208 285

I/O 209 286

I/O 210 288

I/O 211 289

I/O 212 290

I/O 213 291

I/O 214 292

I/O 215 293

I/O 216 294

I/O 217 295

I/O 218 296

I/O 219 298

I/O 220 299

I/O 221 300

I/O 222 301

I/O 223 302

I/O 224 303

I/O 225

I/O 226

I/O 227

I/O 228

I/O 229

I/O 230

I/O 231

I/O 232

I/O 233

I/O 234

I/O 235

I/O 236

I/O 237

I/O 238

I/O 239

I/O 240

I/O 241

I/O 242

I/O 243

I/O 244

I/O 245

D10

I/O 246

C10

I/O 247

I/O 248

A10

I/O 249

D11

I/O 250

C11

I/O 251

A11

I/O 252

A12

I/O 253

D12

I/O 254

C12

I/O 255

B12

I/O Locations

Signal PQFP BGA

Specifications

ispLSI 3256E

Pin Configuration

ispLSI 3256E 304-Pin PQFP Pinout Diagram

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153

304

303

302

301

300

299

298

297

296

295

294

293

292

291

290

289

288

287

286

285

284

283

282

281

280

279

278

277

276

275

274

273

272

271

270

269

268

267

266

265

264

263

262

261

260

259

258

257

256

255

254

253

252

251

250

249

248

247

246

245

244

243

242

241

240

239

238

237

236

235

234

233

232

231

230

229

VCC

I/O 225
I/O 226
I/O 227
I/O 228
I/O 229
I/O 230
I/O 231

GND

I/O 232
I/O 233
I/O 234

MODE/TMS

I/O 235
I/O 236
I/O 237
I/O 238
I/O 239

GND

I/O 240
I/O 241
I/O 242

SDI/TDI

I/O 243
I/O 244
I/O 245
I/O 246
I/O 247

VCC

I/O 248
I/O 249
I/O 250

I/O 251
I/O 252
I/O 253
I/O 254
I/O 255

GND
I/O 0
I/O 1
I/O 2

I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9

I/O 10

RESET

I/O 11
I/O 12
I/O 13
I/O 14
I/O 15

VCC

I/O 16
I/O 17
I/O 18

ispEN/BSCAN

I/O 19
I/O 20
I/O 21
I/O 22
I/O 23

GND

I/O 24
I/O 25
I/O 26

SCLK/TCK

I/O 27
I/O 28
I/O 29

VCC

I/O 30

I/O 31

I/O 32

I/O 33

I/O 34

I/O 35

I/O 36

GND

I/O 37

I/O 38

I/O 39

I/O 40

I/O 41

I/O 42

I/O 43

I/O 44

I/O 45

GND

I/O 46

I/O 47

I/O 48

I/O 49

I/O 50

I/O 51

I/O 52

I/O 53

I/O 54

VCC

I/O 55

I/O 56

I/O 57

I/O 58

I/O 59

I/O 60

I/O 61

I/O 62

I/O 63

GND

I/O 64

I/O 65

I/O 66

I/O 67

I/O 68

I/O 69

I/O 70

I/O 71

I/O 72

GND

I/O 73

I/O 74

I/O 75

I/O 76

I/O 77

I/O 78

I/O 79

I/O 80

I/O 81

VCC

I/O 82

I/O 83

I/O 84

I/O 85

I/O 86

I/O 87

I/O 88

I/O 89

I/O 90

GND

I/O 91

I/O 92

I/O 93

I/O 94

I/O 95

I/O 96

I/O 97

I/O 157
I/O 156
I/O 155
TRST/NC

I/O 154
I/O 153
I/O 152
GND
I/O 151
I/O 150
I/O 149
I/O 148
I/O 147
TOE
I/O 146
I/O 145
I/O 144
VCC
I/O 143
I/O 142
I/O 141
I/O 140
I/O 139
Y2
I/O 138
I/O 137
I/O 136
GND
I/O 135
I/O 134
I/O 133
I/O 132
I/O 131
GOE0
I/O 130
I/O 129
I/O 128
GND
I/O 127
I/O 126
I/O 125
I/O 124
I/O 123
GOE1
I/O 122
I/O 121
I/O 120
VCC
I/O 119
I/O 118
I/O 117
I/O 116
I/O 115
Y3
I/O 114
I/O 113
I/O 112
GND
I/O 111
I/O 110
I/O 109
I/O 108
I/O 107
Y4
I/O 106
I/O 105
I/O 104
GND
I/O 103
I/O 102
I/O 101
I/O 100
I/O 99
SDO/TDO
I/O 98
VCC

VCC

I/O 224

I/O 223

I/O 222

I/O 221

I/O 220

I/O 219

GND

I/O 218

I/O 217

I/O 216

I/O 215

I/O 214

I/O 213

I/O 212

I/O 211

I/O 210

VCC

I/O 209

I/O 208

I/O 207

I/O 206

I/O 205

I/O 204

I/O 203

I/O 202

I/O 201

GND

I/O 200

I/O 199

I/O 198

I/O 197

I/O 196

I/O 195

I/O 194

I/O 193

I/O 192

GND

I/O 191

I/O 190

I/O 189

I/O 188

I/O 187

I/O 186

I/O 185

I/O 184

I/O 183

VCC

I/O 182

I/O 181

I/O 180

I/O 179

I/O 178

I/O 177

I/O 176

I/O 175

I/O 174

GND

I/O 173

I/O 172

I/O 171

I/O 170

I/O 169

I/O 168

I/O 167

I/O 166

I/O 165

GND

I/O 164

I/O 163

I/O 162

I/O 161

I/O 160

I/O 159

I/O 158

VCC

ispLSI 3256E

Top View

304MQFP.3256E

1. NC pins are not to be connected to any active signals, VCC or GND.

Specifications

ispLSI 3256E

Signal Configuration

ispLSI 3256E 320-Ball BGA Signal Diagram

1. NC pins are not to be connected to any active signals, VCC or GND.

Note: Ball A1 indicator dot on top side of package.

ispLSI 3256E

Bottom View

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

GND

VCC

TOE

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

RESET

I/O

252

I/O

251

I/O

248

I/O

247

I/O

243

I/O

240

I/O

237

I/O

234

I/O

231

I/O

227

I/O

225

I/O

229

I/O

232

I/O

235

I/O

239

I/O

242

I/O

244

I/O

255

I/O

254

I/O

250

I/O

246

SDI/

TDI

I/O

236

I/O

233

I/O

230

I/O

226

I/O

224

I/O

221

I/O

218

I/O

220

I/O

223

I/O

222

I/O

219

I/O

216

I/O

215

I/O

211

I/O

207

I/O

205

I/O

203

I/O

209

I/O

206

I/O

204

I/O

199

I/O

195

I/O

194

I/O

188

I/O

187

I/O

183

I/O

181

I/O

180

I/O

175

I/O

172

I/O

176

I/O

178

I/O

174

I/O

173

I/O

170

I/O

168

I/O

171

I/O

167

I/O

164

I/O

162

I/O

159

I/O

148

I/O

145

I/O

141

I/O

137

I/O

133

I/O

129

I/O

125

I/O

121

I/O

117

I/O

113

I/O

110

I/O

100

I/O

102

I/O

105

I/O

108

I/O

118

I/O

122

I/O

126

I/O

128

I/O

132

I/O

136

I/O

139

I/O

143

I/O

146

I/O

149

I/O

152

I/O

155

I/O

157

I/O

156

I/O

153

I/O

150

I/O

140

I/O

138

I/O

135

I/O

131

I/O

127

I/O

116

I/O

114

I/O

111

I/O

107

I/O

104

I/O

101

I/O

103

I/O

106

I/O

109

I/O

112

I/O

115

I/O

119

I/O

120

I/O

123

I/O

124

I/O

130

I/O

134

I/O

142

I/O

144

I/O

147

I/O

151

I/O

154

GOE

I/O

158

I/O

160

SDO/

TDO

I/O

165

I/O

163

I/O

161

TRST/

I/O

169

I/O

166

I/O

177

I/O

179

I/O

182

I/O

186

I/O

185

I/O

184

I/O

191

I/O

190

I/O

189

I/O

192

I/O

193

I/O

196

I/O

197

I/O

198

I/O

200

I/O

201

I/O

202

I/O

212

I/O

208

I/O

213

I/O

210

I/O

217

I/O

214

I/O

228

I/O

238

I/O

241

I/O

245

I/O

249

I/O

253

I/O

MODE/

TMS

SCLK/

TCK

ispEN

BSCAN

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ispLSI3256E-100LQ

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ispLSI3256E-100LQ