Linear Integrated Systems
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 FAX: (510) 353-0261
FEATURES
VERY HIGH INPUT IMPEDANCE
HIGH GATE BREAKDOWN
ULTRA LOW LEAKAGE
LOW CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
(T
A
= 25
C unless otherwise noted)
Drain-Source or Drain-Gate Voltage (NOTE 2)
3N165
40 V
3N166
30 V
Transient G-S Voltage (NOTE 3)
125 V
Gate-Gate Voltage
80 V
Drain Current (NOTE 2)
50 mA
Storage Temperature
-65
C to +200
C
Operating Temperature
-55
C to +150
C
Lead Temperature (Soldering, 10 sec.)
+300
C
Power Dissipation (One Side)
300 mW
Total Derating above 25
C
4.2 mW/
C
MONOLITHIC DUAL P-CHANNEL
ENHANCEMENT MODE
MOSFET
3N165, 3N166
TO-99
Bottom View
Device Schematic
S
D1
G1
C
G2
D2
1
7
5
4
8
3
LIMITS
SYMBOL CHARACTERISTICS
MIN.
MAX.
UNITS
CONDITIONS
I
GSSR
Gate Reverse Leakage Current
--
10
V
GS
= 40 V
I
GSSF
Gate Forward Leakage Current
--
-10
V
GS
= -40 V
--
-25
pA
T
A
=+125
C
I
DSS
Drain to Source Leakage Current
--
-200
V
DS
= -20 V
I
SDS
Source to Drain Leakage Current
--
-400
V
SD
= -20 V
V
DB
= 0
I
D(on)
On Drain Current
-5
-30
mA
V
DS
= -15 V
V
GS
= -10 V
V
GS(th)
Gate Source Threshold Voltage
-2
-5
V
V
DS
= -15 V
I
D
= -10
A
V
GS(th)
Gate Source Threshold Voltage
-2
-5
V
V
DS
= V
GS
I
D
= -10
A
r
DS(on)
Drain Source ON Resistance
--
300
ohms
V
GS
= -20 V
I
D
= -100
A
g
fs
Forward Transconductance
1500
3000
s
V
DS
= -15V
I
D
= -10mA
f=1kHz
g
os
Output Admittance
--
300
s
C
iss
Input Capacitance
--
3.0
C
rss
Reverse Transfer Capacitance
--
0.7
pF
V
DS
= -15V
I
D
= -10mA f=1MHz
C
oss
Output Capacitance
--
3.0
(NOTE 4)
R
E
(Y
fs
)
Common Source Forward Transconductance
1200
--
s
V
DS
= -15V
I
D
= -10mA
f=100MHz
(NOTE 4)
ELECTRICAL CHARACTERISTICS (T
A
=25
C and V
BS
=0 unless otherwise specified)
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 FAX: (510) 353-0261
LIMITS
SYMBOL CHARACTERISTICS
MIN. MAX. UNITS CONDITIONS
Y
fs1
/Y
fs2
Forward Transconductance Ratio
0.90
1.0
V
DS
= -15 V
I
D
= -500
A
f=1kHz
V
GS1-2
Gate Source Threshold Voltage Differential
--
100
mV
V
DS
= -15 V
I
D
= -500
A
V
GS1-2
/
T
Gate Source Threshold Voltage Differential
--
100
V/
C
V
DS
= -15 V
I
A
= -500
A
Change with Temperature
T
A
= -55
C to = +25
C
MATCHING CHARACTERISTICS 3N165
90%
Switching Times Test Circuit
V
DD
1
2
OUT
V
R
R
50
Switching Times Test Circuit
t
10%
10%
10%
10%
t
on
r
off
t
INPUT PULSE
Rise Time 2ns
Pulse Width 200ns
SAMPLING SCOPE
T 0.2ns
C 2pF
R 10M
r
IN
IN
TYPICAL SWITCHING WAVEFORM
NOTES:
1. MOS field-effect transistors have extremely high input resistance and can be damaged by the accumulation of excess static
charge. To avoid possible damage to the device while wiring, testing, or in actual operation, follow these procedures:
To avoid the build-up of static charge, the leads of the devices should remain shorted together with a metal ring except when
being tested or used. Avoid unnecessary handling. Pick up devices by the case instead of the leads. Do not insert or remove
devices from circuits with the power on, as transient voltages may cause permanant damage to the devices.
2. Per transistor.
3. Devices must mot be tested at
125V more than once, nor for longer than 300ms.
4. For design reference only, not 100% tested.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
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