Linear Integrated Systems
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 FAX: (510) 353-0261
TO-72
Bottom View
DIE MAP
ELECTRICAL CHARACTERISTICS @ 25
C (unless otherwise specified)
LIMITS
SYMBOL CHARACTERISTICS
MIN.
MAX.
UNITS
CONDITIONS
I
GSS
Gate-Body Leakage Current
--
10
pA
V
GS
= -35 V
V
DS
= 0
BV
DSS
Drain-Source Breakdown Voltage
25
--
V
GS
= 0
I
D
= 10 mA
V
GS(th)
Threshold Voltage 3N170
1.0
2.0
V
3N171
1.5
3.0
V
DS
= -10V
I
D
= 10
A
I
DSS
Zero Gate Voltage Drain Current
--
10
nA
V
DS
= -10 V
V
GS
= 0
r
DS(on)
Drain-Source ON Resistance
--
200
ohms
V
GS
= -10 V
I
D
= 0
f=1KHz
I
D(on)
ON Drain Current
10
--
mA
V
GS
= -10 V
V
DS
= -10 V
V
DS(on)
Drain-Source ON Voltage
--
2.0
V
V
GS
= -10 V
I
D
= 10 mA
|Y
fs
|
Forward Transfer Admittance
1000
--
s
V
DS
= -10V
I
D
= 2.0mA
f=1KHz
C
rss
Reverse Transfer Capacitance
--
1.3
V
GS
= 0
V
DS
= 0
f=1MHz
C
iss
Input Capacitance
--
5.0
pF
V
GS
= 0
V
DS
= -10V
f=1MHz
C
d(sub)
Drain Substrate Capacitance
--
5.0
V
D(SUB)
=-10V
f=1MHz
td
(on)
Turn-On Delay Time
--
3.0
V
DD
= -10V
I
D(on)
= 10mA
t
r
Rise Time
--
10
V
GS(on)
= -10V
V
GS(off)
= of=1KHz
td
(off)
Turn-Off Delay Time
--
3.0
ns
R
G
= 50
t
f
Fall Time
--
15
NOTES: 1. These ratings are limiting values above which the serviceability of the semiconductor may be impaired.
3N170, 3N171
N-CHANNEL ENHANCEMENT MODE
MOSFET
FEATURES
VERY HIGH INPUT IMPEDANCE
LOW SWITCHING VOLTAGES
LOW DRAIN-SOURCE RESISTANCE
LOW REVERSE TRANSFER CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
(T
A
= 25
C unless otherwise noted)
Drain-Gate Voltage
35V
Drain-Source Voltage
25V
Gate-Gate Voltage
35V
Drain Current
30mA
Storage Temperature
-65
C to +200
C
Operating Temperature
-55
C to +125
C
Power Dissipation
300 mW
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 FAX: (510) 353-0261
LIMITS
SYMBOL CHARACTERISTICS
MIN. MAX. UNITS CONDITIONS
Y
fs1
/Y
fs2
Forward Transconductance Ratio
0.90
1.0
V
DS
= -15 V
I
D
= -500
A
f=1kHz
V
GS1-2
Gate Source Threshold Voltage Differential
--
100
mV
V
DS
= -15 V
I
D
= -500
A
V
GS1-2
/
T
Gate Source Threshold Voltage Differential
--
100
V/
C
V
DS
= -15 V
I
A
= -500
A
Change with Temperature
T
A
= -55
C to = +25
C
MATCHING CHARACTERISTICS 3N165
90%
Switching Times Test Circuit
V
DD
1
2
OUT
V
R
R
50
Switching Times Test Circuit
t
10%
10%
10%
10%
t
on
r
off
t
INPUT PULSE
Rise Time 2ns
Pulse Width 200ns
SAMPLING SCOPE
T 0.2ns
C 2pF
R 10M
r
IN
IN
TYPICAL SWITCHING WAVEFORM
NOTES:
1. MOS field-effect transistors have extremely high input resistance and can be damaged by the accumulation of excess static
charge. To avoid possible damage to the device while wiring, testing, or in actual operation, follow these procedures:
To avoid the build-up of static charge, the leads of the devices should remain shorted together with a metal ring except when
being tested or used. Avoid unnecessary handling. Pick up devices by the case instead of the leads. Do not insert or remove
devices from circuits with the power on, as transient voltages may cause permanant damage to the devices.
2. Per transistor.
3. Devices must mot be tested at
125V more than once, nor for longer than 300ms.
4. For design reference only, not 100% tested.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
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