LT1054/LT1054L

Switched-Capacitor Voltage

Converter with Regulator

FEATURE

ESCRIPTIO

Available in Space Saving SO-8 Package

Output Current: 100mA (LT1054)

125mA (LT1054L)

Low Loss: 1.1V at 100mA

Operating Range:3.5V to 15V (LT1054)

3.5V to 7V (LT1054L)

Reference and Error Amplifier for Regulation

External Shutdown

External Oscillator Synchronization

Can Be Paralleled

Pin Compatible with the LTC

1044/LTC7660

The LT

1054 is a monolithic, bipolar, switched-capacitor

voltage converter and regulator. The LT1054 provides
higher output current than previously available converters
with significantly lower voltage losses. An adaptive switch
driver scheme optimizes efficiency over a wide range of
output currents. Total voltage loss at 100mA output current
is typically 1.1V. This holds true over the full supply voltage
range of 3.5V to 15V. Quiescent current is typically 2.5mA.

The LT1054 also provides regulation, a feature not previ-
ously available in switched-capacitor voltage converters.
By adding an external resistive divider a regulated output
can be obtained. This output will be regulated against
changes in both input voltage and output current. The
LT1054 can also be shut down by grounding the feedback
pin. Supply current in shutdown is less than 100

The internal oscillator of the LT1054 runs at a nominal
frequency of 25kHz. The oscillator pin can be used to adjust
the switching frequency or to externally synchronize the
LT1054.

The LT1054 is pin compatible with previous converters
such the LTC1044/LTC7660.

OUTPUT CURRENT (mA)

VOLTAGE LOSS (V)

1054 TA01·

100

125

= 125

= 25

= 55

LT1054

LT1054L

3.5V

15V (LT1054)

3.5V

7V (LT1054L)

= C

OUT

= 100

INDICATES GUARANTEED
TEST POINT

, LTC and LT are registered trademarks of Linear Technology Corporation.

LT1054/LT1054L Voltage Loss

Voltage Inverter

Voltage Regulator

Negative Voltage Doubler

Positive Voltage Doubler

PPLICATI

REFERENCE

OSC

DRIVE

OSC

CAP

GND

CAP

FEEDBACK/

SHUTDOWN

*EXTERNAL CAPACITORS

2.5V

OUT

LT1054 · BD

REF

OUT

BLOCK DIAGRA

LT1054/LT1054L

BSOLUTE

Supply Voltage (Note 2)

LT1054 ................................................................ 16V
LT1054L ................................................................ 7V

Input Voltage

Pin 1 ................................................. 0V

PIN1

Pin 3 (S Package) ............................. 0V

PIN3

Pin 7 ............................................. 0V

PIN7

REF

Pin 13 (S Package) ...................... 0V

PIN13

REF

Operating Junction Temperature Range

LT1054C/LT1054LC ............................. 0

C to 100

LT1054I ........................................... 40

C to 100

LT1054M ......................................... 55

C to 125

Maximum Junction Temperature (Note 3)

LT1054C/LT1054LC ........................................ 125

LT1054I ............................................................ 125

LT1054M ......................................................... 150

Storage Temperature Range
H, J8, N8 and S8 Packages ................ 55

C to 150

S Package ........................................ 65

C to 150

Lead Temperature (Soldering, 10 sec)................. 300

PACKAGE/ORDER I FOR ATIO

ORDER PART

NUMBER

LT1054CH
LT1054MH

JMAX

= 150

= 45

C/W

TOP VIEW

OSC

FB/SHDN

REF

OUT

GND

CAP

CASE

OUT

CAP

H PACKAGE

8-LEAD TO-5 METAL CAN

JMAX

= 125

= 120

C/W

ORDER PART

NUMBER

JMAX

= 125

= 150

C/W

TOP VIEW

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

N8 PACKAGE

8-LEAD PLASTIC DIP

J8 PACKAGE

8-LEAD CERAMIC DIP

JMAX

= 150

= 100

C/ W (J8)

JMAX

= 125

= 130

C/ W (N8)

TOP VIEW

OSC

REF

OUT

FB/SHDN

CAP

GND

CAP

S8 PACKAGE

8-LEAD PLASTIC SO

SEE REGULATION AND CAPACITOR SELECTION SECTIONS
IN THE APPLICATIONS INFORMATION FOR IMPORTANT
INFORMATION ON THE S8 DEVICE

(Note 6)

ORDER PART

NUMBER

LT1054CS8
LT1054LCS8

S8 PART

MARKING

1054
1054L

(Note 1)

ORDER PART

NUMBER

LT1054CSW
LT1054ISW

LT1054CJ8
LT1054CN8
LT1054IN8
LT1054MJ8

TOP VIEW

SW PACKAGE

16-LEAD PLASTIC SO

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

OT RECO

DED

FOR EW

DESIG

LT1054/LT1054L

ELECTRICAL C

HARA TERISTICS

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Current

LOAD

= 0mA

LT1054:

= 3.5V

2.5

4.0

= 15V

3.0

5.0

LT1054L: V

= 3.5V

2.5

4.0

= 7V

3.0

5.0

Supply Voltage Range

LT1054

3.5

LT1054L

3.5

Voltage Loss (V

OUT

)

= C

OUT

= 100

F Tantalum (Note 4)

OUT

= 10mA

0.35

0.55

OUT

= 100mA

1.10

1.60

OUT

= 125mA (LT1054L)

1.35

1.75

Output Resistance

OUT

= 10mA to 100mA (Note 5)

Oscillator Frequency

LT1054: 3.5V

15V

kHz

LT1054L: 3.5V

kHz

Reference Voltage

REF

= 60

A, T

= 25

2.35

2.50

2.65

2.25

2.75

Regulated Voltage

= 7V, T

= 25

C, R

= 500

(Note 6)

4.70

5.00

5.20

Line Regulation

LT1054: 7V

12V, R

= 500

(Note 6)

Load Regulation

= 7V, 100

500

(Note 6)

Maximum Switch Current

300

Supply Current in Shutdown

PIN1

= 0V

100

200

(Note 7)

Note 5: Output resistance is defined as the slope of the curve, (

OUT

), for output currents of 10mA to 100mA. This represents the linear

portion of the curve. The incremental slope of the curve will be higher at
currents < 10mA due to the characteristics of the switch transistors.

Note 6: All regulation specifications are for a device connected as a
positive-to-negative converter/regulator with R1 = 20k, R2 = 102.5k,
C1 = 0.002

F, (C1 = 0.05

F S package) C

= 10

F tantalum,

OUT

= 100

F tantalum.

Note 7: The S8 package uses a different die than the H, J8, N8 and S
packages. The S8 device will meet all the existing data sheet parameters.
See Regulation and Capacitor Selection in the Applications Information
section for differences in application requirements.

The

denotes specifications which apply over the full operating

temperature range.

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The absolute maximum supply voltage rating of 16V is for
unregulated circuits using LT1054. For regulation mode circuits using
LT1054 with V

OUT

15V at Pin 5 (Pin 11 on S package), this rating may

be increased to 20V. The absolute maximum supply voltage for LT1054L
is 7V.

Note 3: The devices are guaranteed by design to be functional up to the
absolute maximum junction temperature.

Note 4: For voltage loss tests, the device is connected as a voltage
inverter, with pins 1, 6, and 7 (3, 12, and 13 S package) unconnected.
The voltage losses may be higher in other configurations.

LT1054/LT1054L

HARA TERISTICS

TYPICAL PERFOR

Shutdown Threshold

TEMPERATURE (°C)

FREQUENCY (kHz)

LT1054 · TPC03

100 125

= 15V

= 3.5V

INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

= 0

LT1054 · TPC02

Supply Current in Shutdown

INPUT VOLTAGE (V)

QUIESCENT CURRENT (

120

LT1054 · TPC04

100

PIN1

= 0V

OUTPUT CURRENT (mA)

AVERAGE INPUT CURRENT (mA)

100

140

LT1050 · TPC05

120

100

INPUT CAPACITANCE (

VOLTAGE LOSS (V)

0.2

0.6

0.8

1.0

1.4

LT1054 · TPC06

0.4

1.2

90 100

20 30

INVERTER CONFIGURATION
C

OUT

= 100

F TANTALUM

OSC

= 25kHz

OUT

= 100mA

OUT

= 50mA

OUT

= 10mA

OSCILLATOR FREQUENCY (kHz)

VOLTAGE LOSS (V)

100

LT1054 · TPC07

INVERTER CONFIGURATION
C

= 10

F TANTALUM

OUT

= 100

F TANTALUM

OUT

= 100mA

OUT

= 50mA

OUT

= 10mA

OSCILLATOR FREQUENCY (kHz)

VOLTAGE LOSS (V)

100

LT1054 · TPC08

INVERTER CONFIGURATION
C

= 100

F TANTALUM

OUT

= 100

F TANTALUM

OUT

= 100mA

OUT

= 50mA

OUT

= 10mA

TEMPERATURE (°C)

SHUTDOWN THRESHOLD (V)

0.4

0.5

0.6

LT1054 · TPC01

0.3

0.2

100

125

0.1

PIN1

Supply Current

Oscillator Frequency

Average Input Current

Output Voltage Loss

LT1054/LT1054L

HARA TERISTICS

TYPICAL PERFOR

TEMPERATURE (°C)

100

REFERENCE VOLTAGE CHANGE (mV) 80

100

LT1054 · TPC10

100

125

REF

AT 0 = 2.500V

TEMPERATURE (°C)

12.6

OUTPUT VOLTAGE (V)

12.4

12.0

11.8

11.6

4.7

5.0

LT1054 · TPC09

12.2

4.9

4.8

5.1

100

125

Regulated Output Voltage

Reference Voltage Temperature
Coefficient

CTIO

Pin 1 is also the inverting input of the LT1054's error
amplifier and as such can be used to obtain a regulated
output voltage.

CAP

/CAP

(Pin 2/Pin 4): Pin 2, the positive side of the

input capacitor (C

), is alternately driven between V

and

ground. When driven to V

, Pin 2 sources current from V

When driven to ground Pin 2 sinks current to ground. Pin
4, the negative side of the input capacitor, is driven alter-
nately between ground the V

OUT

. When driven to ground,

Pin 4 sinks current to ground. When driven to V

OUT

Pin 4

sources current from C

OUT

. In all cases current flow in the

switches is unidirectional as should be expected using
bipolar switches.

OUT

(Pin 5): In addition to being the output pin this pin is

also tied to the substrate of the device. Special care must
be taken in LT1054 circuits to avoid pulling this pin
positive with respect to any of the other pins. Pulling Pin
5 positive with respect to Pin 3 (GND) will forward bias the
substrate diode which will prevent the device from starting.
This condition can occur when the output load driven by the
LT1054 is referred to its positive supply (or to some other
positive voltage). Note that most op amps present just such
a load since their supply currents flow from their V

terminals to their V

terminals. To prevent start-up prob-

lems with this type of load an external transistor must be
added as shown in Figure 1. This will prevent V

OUT

(Pin 5)

FB/SHDN (Pin 1): Feedback/Shutdown Pin. This pin has
two functions. Pulling Pin 1 below the shutdown threshold
(

0.45V) puts the device into shutdown. In shutdown the

reference/regulator is turned off and switching stops. The
switches are set such that both C

and C

OUT

are dis-

charged through the output load. Quiescent current in
shutdown drops to approximately 100

A (see Typical

Performance Characteristics). Any open-collector gate can
be used to put the LT1054 into shutdown. For normal
(unregulated) operation the device will start back up when
the external gate is shut off. In LT1054 circuits that use the
regulation feature, the external resistor divider can provide
enough pull-down to keep the device in shutdown until the
output capacitor (C

OUT

) has fully discharged. For most

applications where the LT1054 would be run intermittently,
this does not present a problem because the discharge time
of the output capacitor will be short compared to the off-
time of the device. In applications where the device has to
start up before the output capacitor (C

OUT

) has fully dis-

charged, a restart pulse must be applied to Pin 1 of the
LT1054. Using the circuit of Figure 5, the restart signal can
be either a pulse (t

> 100

s) or a logic high. Diode coupling

the restart signal into Pin 1 will allow the output voltage to
come up and regulate without overshoot. The resistor
divider R3/R4 in Figure 5 should be chosen to provide a
signal level at pin 1 of 0.7V to 1.1V.

LT1054/LT1054L

CTIO

from being pulled above the ground pin (Pin 3) during
start-up. Any small, general purpose transistor such as
2N2222 or 2N2219 can be used. R

should be chosen to

provide enough base drive to the external transistor so that
it is saturated under nominal output voltage and maximum
output current conditions. In some cases an N-channel
enhancement mode MOSFET can be used in place of the
transistor.

(

OUT

)

OUT

LOAD

OUT

LT1054 · F01

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

REF

(Pin 6): Reference Output. This pin provides a 2.5V

reference point for use in LT1054-based regulator circuits.
The temperature coefficient of the reference voltage has
been adjusted so that the temperature coefficient of the
regulated output voltage is close to zero. This requires the
reference output to have a positive temperature coefficient
as can be seen in the typical performance curves. This
nonzero drift is necessary to offset a drift term inherent in
the internal reference divider and comparator network tied
to the feedback pin. The overall result of these drift terms
is a regulated output which has a slight positive tempera-
ture coefficient at output voltages below 5V and a slight
negative TC at output voltages above 5V. Reference output
current should be limited, for regulator feedback networks,
to approximately 60

A. The reference pin will draw

100

A when shorted to ground and will not affect the

internal reference/regulator, so that this pin can also be
used as a pull-up for LT1054 circuits that require synchro-
nization.

OSC (Pin 7): Oscillator Pin. This pin can be used to raise or
lower the oscillator frequency or to synchronize the device
to an external clock. Internally Pin 7 is connected to the
oscillator timing capacitor (C

150pF) which is alternately

charged and discharged by current sources of

A so that

the duty cycle is

50%. The LT1054 oscillator is designed

to run in the frequency band where switching losses are
minimized. However the frequency can be raised, lowered,
or synchronized to an external system clock if necessary.

The frequency can be lowered by adding an external
capacitor (C1, Figure 2) from Pin 7 to ground. This will
increase the charge and discharge times which lowers the
oscillator frequency. The frequency can be increased by
adding an external capacitor (C2, Figure 2, in the range of
5pF to 20pF) from Pin 2 to Pin 7. This capacitor will couple
charge into C

at the switch transitions, which will shorten

the charge and discharge time, raising the oscillator fre-
quency. Synchronization can be accomplished by adding
an external resistive pull-up from Pin 7 to the reference pin
(Pin 6). A 20k pull-up is recommended. An open collector
gate or an NPN transistor can then be used to drive the
oscillator pin at the external clock frequency as shown in
Figure 2. Pulling up Pin 7 to an external voltage is
not recommended. For circuits that require both fre-
quency synchronization and regulation, an external refer-
ence can be used as the reference point for the top of the
R1/R2 divider allowing Pin 6 to be used as a pull-up point
for Pin 7.

Figure 1

(Pin 8): Input Supply. The LT1054 alternately charges

to the input voltage when C

is switched in parallel with

the input supply and then transfers charge to C

OUT

when

is switched in parallel with C

OUT

. Switching occurs at

OUT

LT1054 · F02

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

Figure 2

LT1054/LT1054L

the oscillator frequency. During the time that C

is charg-

ing, the peak supply current will be approximately equal to
2.2 times the output current. During the time that C

delivering charge to C

OUT

the supply current drops to

approximately 0.2 times the output current. An input
supply bypass capacitor will supply part of the peak input
current drawn by the LT1054 and average out the current

drawn from the supply. A minimum input supply bypass
capacitor of 2

F, preferably tantalum or some other low

ESR type is recommended. A larger capacitor may be
desirable in some cases, for example, when the actual input
supply is connected to the LT1054 through long leads, or
when the pulse current drawn by the LT1054 might affect
other circuitry through supply coupling.

CTIO

APPLICATIO

S I

FOR

ATIO

Theory of Operation

To understand the theory of operation of the LT1054, a
review of a basic switched-capacitor building block is
helpful.

In Figure 3 when the switch is in the left position, capacitor
C1 will charge to voltage V1. The total charge on C1 will be
q1 = C1V1. The switch then moves to the right, discharging
C1 to voltage V2. After this discharge time the charge on C1
is q2 = C1V2. Note that charge has been transferred from
the source V1 to the output V2. The amount of charge
transferred is:

q = q1 q2 = C1(V1 V2)

If the switch is cycled f times per second, the charge
transfer per unit time (i.e., current) is:

I = (f)(

q) = (f)[C1(V1 V2)]

To obtain an equivalent resistance for the switched-capaci-
tor network we can rewrite this equation in terms of voltage
and impedance equivalence:

I =

V1 V2

(1/fC1)

V1 V2

EQUIV

A new variable R

EQUIV

is defined such that R

EQUIV

= 1/fC1.

Thus the equivalent circuit for the switched-capacitor
network is as shown in Figure 4. The LT1054 has the same
switching action as the basic switched-capacitor building
block. Even though this simplification doesn't include finite
switch on-resistance and output voltage ripple, it provides
an intuitive feel for how the device works.

These simplified circuits explain voltage loss as a function
of frequency (see Typical Performance Characteristics). As
frequency is decreased, the output impedance will eventu-

LT1054 · F03

Figure 3. Switched-Capacitor Building Block

EQUIV

LT1054 · F04

fC1

Figure 4. Switched-Capacitor Equivalent Circuit

ally be dominated by the 1/fC1 term and voltage losses will
rise.

Note that losses also rise as frequency increases. This is
caused by internal switching losses which occur due to
some finite charge being lost on each switching cycle. This
charge loss per-unit-cycle, when multiplied by the switch-
ing frequency, becomes a current loss. At high frequency
this loss becomes significant and voltage losses again rise.

The oscillator of the LT1054 is designed to run in the
frequency band where voltage losses are at a minimum.

Regulation

The error amplifier of the LT1054 servos the drive to the
PNP switch to control the voltage across the input capaci-
tor (C

) which in turn will determine the output voltage.

Using the reference and error amplifier of the LT1054, an
external resistive divider is all that is needed to set the
regulated output voltage. Figure 5 shows the basic regu-
lator configuration and the formula for calculating the
appropriate resistor values. R1 should be chosen to be

LT1054/LT1054L

APPLICATIO

S I

FOR

ATIO

voltage. For the basic configuration,

OUT

referred to the

ground pin of the LT1054 must be less than the total of the
supply voltage minus the voltage loss due to the switches.
The voltage loss versus output current due to the switches
can be found in Typical Performance Characteristics. Other
configurations such as the negative doubler can provide
higher output voltages at reduced output currents (see
Typical Applications).

Capacitor Selection

For unregulated circuits the nominal values of C

and C

OUT

should be equal. For regulated circuits see the section on
Regulation. While the exact values of C

and C

OUT

are

noncritical, good quality, low ESR capacitors such as solid
tantalum are necessary to minimize voltage losses at high
currents. For C

the effect of the ESR of the capacitor will

be multiplied by four due to the fact that switch currents are
approximately two times higher than output current and
losses will occur on both the charge and discharge cycle.
This means that using a capacitor with 1

of ESR for C

will have the same effect as increasing the output imped-
ance of the LT1054 by 4

. This represents a significant

increase in the voltage losses. For C

OUT

the affect of ESR is

less dramatic. C

OUT

is alternately charged and discharged

at a current approximately equal to the output current and
the ESR of the capacitor will cause a step function to occur
in the output ripple at the switch transitions. This step
function will degrade the output regulation for changes in
output load current and should be avoided. Realizing that
large value tantalum capacitors can be expensive, a tech-
nique that can be used is to parallel a smaller tantalum
capacitor with a large aluminum electrolytic capacitor to
gain both low ESR and reasonable cost. Where physical
size is a concern some of the newer chip type surface
mount tantalum capacitors can be used. These capacitors
are normally rated at working voltages in the 10V to 20V
range and exhibit very low ESR (in the range of 0.1

Output Ripple

The peak-to-peak output ripple is determined by the value
of the output capacitor and the output current. Peak-to-
peak output ripple may be approximated by the formula:

dV =

OUT

2fC

OUT

RESTART SHUTDOWN

TANTALUM

OUT

100

TANTALUM

OUT

LT1054 · F05

2.2

R2
R1

+ 1

WHERE V

REF

= 2.5V NOMINAL

*CHOOSE THE CLOSEST 1% VALUE

FOR EXAMPLE: TO GET V

OUT

= 5V REFERRED TO THE GROUND

PIN OF THE LT1054, CHOOSE R1 = 20k, THEN

OUT

)

REF

40mV

R2 = 20k

= 102.6k*

+ 1

)

2.5V

40mV

)

+ 1

OUT

1.21V

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

Figure 5

20k or greater because the reference output current is
limited to

100

A. R2 should be chosen to be in the range

of 100k to 300k. For optimum results the ratio of C

OUT

is recommended to be 1/10. C1, required for good load
regulation at light load currents, should be 0.002

F for all

output voltages.

A new die layout was required to fit into the physical
dimensions of the S8 package. Although the new die of the
LT1054CS8 will meet all the specifications of the existing
LT1054 data sheet, subtle differences in the layout of the
new die require consideration in some application cir-
cuits. In regulating mode circuits using the 1054CS8 the
nominal values of the capacitors, C

and C

OUT

, must be

approximately equal for proper operation at elevated
junction temperatures. This is different from the earlier
part. Mismatches within normal production tolerances
for the capacitors are acceptable. Making the nominal
capacitor values equal will ensure proper operation at
elevated junction temperatures at the cost of a small
degradation in the transient response of regulator cir-
cuits. For unregulated circuits the values of C

and C

OUT

are normally equal for all packages. For S8 applications
assistance in unusual applications circuits, please consult
the factory.

It can be seen from the circuit block diagram that the
maximum regulated output voltage is limited by the supply

LT1054/LT1054L

APPLICATIO

S I

FOR

ATIO

= V

/(4.4 I

OUT

)

where

[(LT1054 Voltage Loss)(1.3) +

OUT

]

and I

OUT

= maximum required output current. The factor of

1.3 will allow some operating margin for the LT1054.

For example: assume a 12V to 5V converter at 100mA
output current. First calculate the power dissipation with-
out an external resistor:

P = (12V

)(100mA) + (12V)(100mA)(0.2)

P = 700mW + 240mW = 940mW

of 130

C/W for a commercial plastic device this

would cause a junction temperature rise of 122

C so that

the device would exceed the maximum junction tempera-
ture at an ambient temperature of 25

C. Now calculate the

power dissipation with an external resistor (R

). First find

how much voltage can be dropped across R

. The maxi-

mum voltage loss of the LT1054 in the standard regulator
configuration at 100mA output current is 1.6V, so

= 12V [(1.6V)(1.3) +

] = 4.9V and

= 4.9V/(4.4)(100mA) = 11

This resistor will reduce the power dissipated by the
LT1054 by (4.9V)(100mA) = 490mW. The total power
dissipated by the LT1054 would then be (940mW
490mW) = 450mW. The junction temperature rise would
now be only 58

C. Although commercial devices are

guaranteed to be functional up to a junction temperature
of 125

C, the specifications are only guaranteed up to a

junction temperature of 100

C, so ideally you should limit

the junction temperature to 100

C. For the above example

this would mean limiting the ambient temperature to 42

Other steps can be taken to allow higher ambient tempera-
tures. The thermal resistance numbers for the LT1054
packages represent worst case numbers with no heat
sinking and still air. Small clip-on type heat sinks can be
used to lower the thermal resistance of the LT1054 pack-
age. In some systems there may be some available airflow
which will help to lower the thermal resistance. Wide PC
board traces from the LT1054 leads can also help to
remove heat from the device. This is especially true for
plastic packages.

where dV = peak-to-peak ripple and f = oscillator frequency.

For output capacitors with significant ESR a second term
must be added to account for the voltage step at the switch
transitions. This step is approximately equal to:

(2I

OUT

)(ESR of C

OUT

)

Power Dissipation

The power dissipation of any LT1054 circuit must be
limited such that the junction temperature of the device
does not exceed the maximum junction temperature rat-
ings. The total power dissipation must be calculated from
two components, the power loss due to voltage drops in the
switches and the power loss due to drive current losses.
The total power dissipated by the LT1054 can be calculated
from:

OUT

)(I

OUT

) + (V

)(I

OUT

)(0.2)

where both V

and V

OUT

are referred to the ground pin (Pin

3) of the LT1054. For LT1054 regulator circuits, the power
dissipation will be equivalent to that of a linear regulator.
Due to the limited power handling capability of the LT1054
packages, the user will have to limit output current require-
ments or take steps to dissipate some power external to the
LT1054 for large input/output differentials. This can be
accomplished by placing a resistor in series with C

shown in Figure 6. A portion of the input voltage will then
be dropped across this resistor without affecting the output
regulation. Because switch current is approximately 2.2
times the output current and the resistor will cause a
voltage drop when C

is both charging and discharging,

the resistor should be chosen as:

OUT

LT1054 · F06

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

Figure 6

LT1054/LT1054L

TYPICAL APPLICATIO

Basic Voltage Inverter

Positive Doubler

Negative Voltage Doubler

100mA Regulating Negative Doubler

1N4002

HP5082-2810

3.5 TO 15V

20k

1N4002

0.002

LT1054 · TAO6

2.2

R1
40k

OUT

SET

PIN 2
LT1054 #1

OUT

100mA MAX

R2
500k

1N4002

, REFER TO FIGURE 5

= 3.5 TO 15V

OUT

MAX

+ [1054 VOLTAGE LOSS + 2(V

DIODE

)]

R2
R1

+ 1

OUT

)

REF

40mV

)

+ 1

OUT

1.21V

100

LT1054 #1

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

LT1054 #2

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

Basic Voltage Inverter/Regulator

0.002

100

REFER TO FIGURE 5

OUT

LT1054 · TA03

R2
R1

+ 1

OUT

)

REF

40mV

)

+ 1 ,

OUT

1.21V

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

100

OUT

LT1054 · TAO2

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

100

= 3.5V TO 15V

OUT

= 2V

+ (LT1054 VOLTAGE LOSS) + (Q

SATURATION VOLTAGE)

*SEE FIGURE 3

OUT

LT1054 · TAO4

100

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

1N4001

= 3.5V TO 15V

OUT

+ 2V

DIODE

)

= LT1054 VOLTAGE LOSS

3.5V TO 15V

LT1054 · TAO5

1N4001

OUT

50mA

100

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

LT1054/LT1054L

TYPICAL APPLICATIO

5V to

12V Converter

Bipolar Supply Doubler

20k

1N914

= 5V

TO PIN 4

LT1054 #1

OUT

12V

OUT

= 25mA

OUT

12V

OUT

= 25mA

LT1054 · TAO8

2N2219

100

LT1054 #2

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

LT1054 #1

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

3.5V TO 15V

OUT

LT1054 · TAO7

OUT

= 1N4001

= 3.5V TO 15V

OUT

+ 2V

DIODE

)

OUT

+ (V

+ 2V

DIODE

)

= LT1054 VOLTAGE LOSS

100

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

200k

100

TANTALUM

LT1054 · TAO9

0.022

2N2222

A = 125 FOR 0V TO 3V OUT FROM FULL-SCALE
BRIDGE OUTPUT OF 24mV

100k

10k

ZERO
TRIM

GAIN

TRIM

10k

301k

1/2 LT1013

10k

2N2907

INPUT TTL

OR CMOS

LOW FOR ON

350

1/2 LT1013

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

Strain Gauge Bridge Signal Conditioner

LT1054/LT1054L

TYPICAL APPLICATIO

3.5V to 5V Regulator

Regulating 200mA, 12V to 5V Converter

Digitally Programmable Negative Supply

20k

OUT

= V

(PROGRAMMED)

20k

15V

LT1004-2.5
2.5V

LT1054 · TA12

AD558

DIGITAL
INPUT

100

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

0.002

HP5082-2810

OUT

= 5V

OUT

= 0mA to 200mA

12V

39.2k

R2
200k

20k

1/2W

LT1054 · TA11

1/2W

200

LT1054 #1

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

LT1054 #2

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

REFER TO FIGURE 5

R2
R1

+ 1

OUT

)

REF

40mV

)

+ 1 ,

OUT

1.21V

100

20k

1N914

20k

1N914

= 3.5V TO 5.5V

OUT

= 5V

OUT(MAX)

= 50mA

1N914

1N5817

3.5V TO 5.5V

LT1054 · TA10

LTC1044

0.002

R2
125k

1N914

125k

2N2219

OUT

= 5V

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

LT1054/LT1054L

Dimensions in inches (millimeters) unless otherwise noted.

PACKAGE DESCRIPTIO

H Package

8-Lead TO-5 Metal Can (0.200 PCD)

(LTC DWG # 05-08-1320)

J8 1197

0.014 0.026

(0.360 0.660)

0.200

(5.080)

MAX

0.015 0.060

(0.381 1.524)

0.125

3.175

MIN

0.100

0.010

(2.540

0.254)

0.300 BSC

(0.762 BSC)

0.008 0.018

(0.203 0.457)

0.005

(0.127)

MIN

0.405

(10.287)

MAX

0.220 0.310

(5.588 7.874)

0.025

(0.635)

RAD TYP

0.045 0.068

(1.143 1.727)

FULL LEAD

OPTION

0.023 0.045

(0.584 1.143)

HALF LEAD

OPTION

CORNER LEADS OPTION

(4 PLCS)

0.045 0.068

(1.143 1.727)

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS

J8 Package

8-Lead CERDIP (Narrow 0.300, Hermetic)

(LTC DWG # 05-08-1110)

0.050

(1.270)

MAX

0.016 0.021**

(0.406 0.533)

0.010 0.045*

(0.254 1.143)

SEATING

PLANE

0.040

(1.016)

MAX

0.165 0.185

(4.191 4.699)

GAUGE
PLANE

REFERENCE
PLANE

0.500 0.750

(12.700 19.050)

0.305 0.335

(7.747 8.509)

0.335 0.370

(8.509 9.398)

DIA

0.200

(5.080)

TYP

0.027 0.045

(0.686 1.143)

0.028 0.034

(0.711 0.864)

0.110 0.160

(2.794 4.064)

INSULATING

STANDOFF

TYP

H8(TO-5) 0.200 PCD 1197

LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND 0.045" BELOW THE REFERENCE PLANE

FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS

0.016 0.024

(0.406 0.610)

PIN 1

LT1054/LT1054L

Dimensions in inches (millimeters) unless otherwise noted.

PACKAGE DESCRIPTIO

N8 1197

0.100

0.010

(2.540

0.254)

0.065

(1.651)

TYP

0.045 0.065

(1.143 1.651)

0.130

0.005

(3.302

0.127)

0.020

(0.508)

MIN

0.018

0.003

(0.457

0.076)

0.125

(3.175)

MIN

0.255

0.015*

(6.477

0.381)

0.400*

(10.160)

MAX

0.009 0.015

(0.229 0.381)

0.300 0.325

(7.620 8.255)

0.325

+0.035
0.015

+0.889
0.381

8.255

(

)

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

N8 Package

8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

SO8 0996

0.053 0.069

(1.346 1.752)

0.014 0.019

(0.355 0.483)

0.004 0.010

(0.101 0.254)

0.050

(1.270)

TYP

0.016 0.050
0.406 1.270

0.010 0.020

(0.254 0.508)

TYP

0.008 0.010

(0.203 0.254)

0.150 0.157**

(3.810 3.988)

0.189 0.197*

(4.801 5.004)

0.228 0.244

(5.791 6.197)

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

LT1054/LT1054L

Dimensions in inches (millimeters) unless otherwise noted.

PACKAGE DESCRIPTIO

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

S16 (WIDE) 0396

NOTE 1

0.398 0.413*

(10.109 10.490)

0.394 0.419

(10.007 10.643)

0.037 0.045

(0.940 1.143)

0.004 0.012

(0.102 0.305)

0.093 0.104

(2.362 2.642)

0.050

(1.270)

TYP

0.014 0.019

(0.356 0.482)

TYP

NOTE 1

0.009 0.013

(0.229 0.330)

0.016 0.050

(0.406 1.270)

0.291 0.299**

(7.391 7.595)

0.010 0.029

(0.254 0.737)

NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

SW Package

16-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

LT1054/LT1054L

LINEAR TECHNOLOGY CORPORATION 1987

1054ld LT/TP 1298 2K REV D · PRINTED IN USA

TYPICAL APPLICATIO

Negative Doubler with Regulator

3.5V TO 15V

100

R2
1M

1N4001

LT1054 · TA14

100

0.002

OUT

= 3.5V TO 15V

OUT(MAX)

+ (V

+ 2V

DIODE

)

= LT1054 VOLTAGE LOSS

, REFER TO FIGURE 5

R2
R1

+ 1

OUT

)

REF

40mV

)

+ 1

OUT

1.21V

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

R1, 20k

0.03

= 5V

50k

1N5817

LT1054 · TA13

10k

5.5k

2.5k

0.1

LT1006

100

OUT

50mA

LT1054

FB/SHDN

CAP

GND

CAP

OSC

REF

OUT

Positive Doubler with Regulation

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1144

Switched-Capacitor Voltage Converter

Wide Input Voltage Range, 2V to 18V

LTC1514/LTC1515

Step-Up/Step-Down Switched Capacitor DC/DC Converters

Regulated 5V Doublers

LT1611

Micropower Inverting DC/DC Converter

150mA Output

LT1614

Micropower Inverting DC/DC Converter

250mA Output

THE TYPICAL APPLICATIONS CIRCUITS WERE VERIFIED USING THE STANDARD LT1054. FOR S8 APPLICATIONS
ASSISTANCE IN ANY OF THE UNUSUAL APPLICATIONS CIRCUITS PLEASE CONSULT THE FACTORY

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LT1054

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LT1054