1
LT1371
500kHz High Efficiency
3A Switching Regulator
The LT
1371 is a monolithic high frequency current mode
switching regulator. It can be operated in all standard
switching configurations including boost, buck, flyback,
forward, inverting and "Cuk." A 3A high efficiency switch
is included on the die, along with all oscillator, control and
protection circuitry.
The LT1371 typically consumes only 4mA quiescent
current and has higher efficiency than previous parts.
High frequency switching allows for very small inductors
to be used.
New design techniques increase flexibility and maintain
ease of use. Switching is easily synchronized to an exter-
nal logic level source. A logic low on the Shutdown pin
reduces supply current to 12
A. Unique error amplifier
circuitry can regulate positive or negative output voltage
while maintaining simple frequency compensation tech-
niques. Nonlinear error amplifier transconductance re-
duces output overshoot on start-up or overload recovery.
Oscillator frequency shifting protects external compo-
nents during overload conditions.
DESCRIPTIO
N
U
s
Faster Switching with Increased Efficiency
s
Uses Small Inductors: 4.7
H
s
All Surface Mount Components
s
Low Minimum Supply Voltage: 2.7V
s
Quiescent Current: 4mA Typ
s
Current Limited Power Switch: 3A
s
Regulates Positive or Negative Outputs
s
Shutdown Supply Current: 12
A Typ
s
Easy External Synchronization
s
Boost Regulators
s
Laptop Computer Supplies
s
Multiple Output Flyback Supplies
s
Inverting Supplies
APPLICATIO
N
S
U
TYPICAL APPLICATIO
N
U
5V to 12V Boost Converter
OUTPUT CURRENT (A)
0.01
50
EFFICIENCY (%)
60
70
80
90
0.1
1
LT1371 TA02
100
V
IN
= 5V
12V Output Efficiency
LT1371
V
IN
V
C
5V
GND
FB
LT1371 TA01
V
SW
S/S
L1*
4.7
H
C1**
22
F
25V
C4**
22
F
25V
2
C2
0.047
F
C3
0.0047
F
R3
2k
R2
6.19k
1%
R1
53.6k
1%
V
OUT
12V
D1
MBRS330T3
ON
OFF
*
**
COILCRAFT DO3316P-472 (4.7
H),
DO3316P-103 (10
H) OR
SUMIDA CD104-100MC (10
H)
AVX TPSD226M025R0200
+
+
L1
4.7
H
10
H
I
OUT
0.7A
0.8A
MAX I
OUT
FEATURES
, LTC and LT are registered trademarks of Linear Technology Corporation.
2
LT1371
A
U
G
W
A
W
U
W
A
R
BSOLUTE
XI
TI
S
Supply Voltage ....................................................... 30V
Switch Voltage
LT1371 ............................................................... 35V
LT1371HV .......................................................... 42V
S/S, SHDN, SYNC Pin Voltage ................................ 30V
Feedback Pin Voltage (Transient, 10ms) ..............
10V
Feedback Pin Current ........................................... 10mA
Negative Feedback Pin Voltage
(Transient, 10ms) .............................................
10V
Operating Ambient Temperature Range ...... 0
C to 70
C
Operating Junction Temperature Range
Commercial .......................................... 0
C to 125
C
Industrial ......................................... 40
C to 125
C
Short Circuit ......................................... 0
C to 150
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec) ................. 300
C
ELECTRICAL C
C
HARA TERISTICS
V
IN
= 5V, V
C
= 0.6V, V
FB
= V
REF
, V
SW
, S/S, SHDN, SYNC and NFB pins open, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
REF
Reference Voltage
Measured at Feedback Pin
1.230
1.245
1.260
V
V
C
= 0.8V
q
1.225
1.245
1.265
V
I
FB
Feedback Input Current
V
FB
= V
REF
250
550
nA
q
900
nA
Reference Voltage Line Regulation
2.7V
V
IN
25V, V
C
= 0.8V
q
0.01
0.03
%/V
W
U
U
PACKAGE/ORDER I FOR ATIO
T
JMAX
= 125
C,
JA
= 30
C/W
R PACKAGE
7-LEAD PLASTIC DD
FRONT VIEW
TAB
IS
GND
V
IN
S/S
V
SW
GND
NFB
FB
V
C
7
6
5
4
3
2
1
ORDER PART
NUMBER
WITH PACKAGE SOLDERED TO 0.5 INCH
2
COPPER
AREA OVER BACKSIDE GROUND PLANE OR INTERNAL
POWER PLANE.
JA
CAN VARY FROM 20
C/W TO
> 40
C/W DEPENDING ON MOUNTING TECHNIQUE
ORDER PART
NUMBER
T7 PACKAGE
7-LEAD TO-220
V
IN
S/S
V
SW
GND
NFB
FB
V
C
FRONT VIEW
7
6
5
4
3
2
1
TAB
IS
GND
T
JMAX
= 125
C,
JA
= 50
C/W,
JC
= 4
C/W
ORDER PART
NUMBER
T
JMAX
= 125
C,
JA
= 50
C/W
JA
WILL VARY FROM APPROXIMATELY 40
C/W WITH
0.75 INCH
2
OF 1 OZ COPPER TO 50
C/W WITH 0.33 INCH
2
OF 1 OZ COPPER ON A DOUBLE-SIDED BOARD
1
2
3
4
5
6
7
8
9
10
TOP VIEW
SW PACKAGE
20-LEAD PLASTIC SO WIDE
20
19
18
17
16
15
14
13
12
11
V
C
FB
NFB
GND
GND
GND
GND
SHDN
SYNC
V
IN
V
SW
NC
V
SW
GND
GND
GND
GND
NC
NC
GND
LT1371CR
LT1371HVCR
LT1371IR
LT1371HVIR
LT1371CT7
LT1371HVCT7
LT1371IT7
LT1371HVIT7
LT1371CSW
LT1371HVCSW
LT1371ISW
LT1371HVISW
Consult factory for Military grade parts.
3
LT1371
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
NFB
Negative Feedback Reference Voltage
Measured at Negative Feedback Pin
2.540
2.490
2.440
V
Feedback Pin Open, V
C
= 0.8V
q
2.570
2.490
2.410
V
I
NFB
Negative Feedback Input Current
V
NFB
= V
NFR
q
45
30
15
A
Negative Feedback Reference Voltage
2.7V
V
IN
25V, V
C
= 0.8V
q
0.01
0.05
%/V
Line Regulation
g
m
Error Amplifier Transconductance
I
C
=
25
A
1100
1500
1900
mho
q
700
2300
mho
Error Amplifier Source Current
V
FB
= V
REF
150mV, V
C
= 1.5V
q
120
200
350
A
Error Amplifier Sink Current
V
FB
= V
REF
+ 150mV, V
C
= 1.5V
q
1400
2400
A
Error Amplifier Clamp Voltage
High Clamp, V
FB
= 1V
1.70
1.95
2.30
V
Low Clamp, V
FB
= 1.5V
0.25
0.40
0.52
V
A
V
Error Amplifier Voltage Gain
500
V/ V
V
C
Pin Threshold
Duty Cycle = 0%
0.8
1
1.25
V
f
Switching Frequency
2.7V
V
IN
25V
450
500
550
kHz
0
C
T
J
125
C
q
430
500
580
kHz
40
C
T
J
0
C (I Grade)
400
580
kHz
Maximum Switch Duty Cycle
q
85
95
%
Switch Current Limit Blanking Time
130
260
ns
BV
Output Switch Breakdown Voltage
LT1371
q
35
47
V
LT1371HV
0
C
T
J
125
C
q
42
47
V
40
C
T
J
0
C (I Grade)
40
V
V
SAT
Output Switch ON Resistance
I
SW
= 2A
q
0.25
0.45
I
LIM
Switch Current Limit
Duty Cycle = 50%
q
3.0
3.8
5.4
A
Duty Cycle = 80% (Note 1)
q
2.6
3.4
5.0
A
I
IN
Supply Current Increase During Switch ON Time
15
25
mA/A
I
SW
Control Voltage to Switch Current
4
A/V
Transconductance
Minimum Input Voltage
q
2.4
2.7
V
I
Q
Supply Current
2.7V
V
IN
25V
q
4
5.5
mA
Shutdown Supply Current
2.7V
V
IN
25V, V
S/S
0.6V
0
C
T
J
125
C
q
12
30
A
40
C
T
J
0
C (I Grade)
50
A
Shutdown Threshold
2.7V
V
IN
25V
q
0.6
1.3
2
V
Shutdown Delay
q
5
12
25
s
S/S or SHDN Pin Input Current
0V
V
S/S
or V
SHDN
5V
q
10
15
A
Synchronization Frequency Range
q
600
800
kHz
ELECTRICAL C
C
HARA TERISTICS
V
IN
= 5V, V
C
= 0.6V, V
FB
= V
REF
, V
SW
, S/S, SHDN, SYNC and NFB pins open, unless otherwise noted.
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: For duty cycles (DC) between 50% and 90%, minimum
guaranteed switch current is given by I
LIM
= 1.33 (2.75 DC).
4
LT1371
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
Error Amplifier Output Current
vs Feedback Pin Voltage
Shutdown Delay and Threshold
vs Temperature
TEMPERATURE (
C)
50
0
SHUTDOWN DELAY (
s)
SHUTDOWN THRESHOLD (V)
2
6
8
10
20
14
0
50
75
LT1371 G04
4
16
18
12
0
0.2
0.6
0.8
1.0
2.0
1.4
0.4
1.6
1.8
1.2
25
25
100 125
150
SHUTDOWN THRESHOLD
SHUTDOWN DELAY
S/S or SHDN Pin Input Current
vs Voltage
Error Amplifier Transconductance
vs Temperature
Switching Frequency
vs Feedback Pin Voltage
FEEDBACK PIN VOLTAGE (V)
400
ERROR AMPLIFIER OUTPUT CURRENT (
A)
300
200
100
300
100
0.1
0.1
200
0
0.3
0.2
V
REF
55
C
125
C
25
C
LT1371 G06
Minimum Synchronization
Voltage vs Temperature
TEMPERATURE (
C)
50
0
MINIMUM SYNCHRONIZATION VOLTAGE (V
P-P
)
0.5
1.0
1.5
2.0
0
50
100
150
LT1371 G05
2.5
3.0
25
25
75
125
f
SYNC
= 700kHz
VOLTAGE (V)
1
INPUT CURRENT (
A)
1
3
5
7
LT1371 G07
1
3
0
2
4
2
4
5
1
3
5
0
8
2
4
6
9
V
IN
= 5V
FEEDBACK PIN VOLTAGE (V)
0
SWITCHING FREQUENCY (% OF TYPICAL)
70
90
110
0.8
LT1371 G08
50
30
60
80
100
40
20
10
0.2
0.4
0.6
0.1
0.9
0.3
0.5
0.7
1.0
TEMPERATURE (
C)
50
0
TRANSCONDUCTANCE (
mho)
200
600
800
1000
2000
1400
0
50
75
LT1371 G09
400
1600
1800
1200
25
25
100 125
150
g
m
=
I (V
C
)
V (FB)
Switch Saturation Voltage
vs Switch Current
TEMPERATURE (
C)
50
1.8
INPUT VOLTAGE (V)
2.0
2.2
2.4
2.6
0
50
100
150
LT1371 G03
2.8
3.0
25
25
75
125
Minimum Input Voltage
vs Temperature
DUTY CYCLE (%)
0
SWITCH CURRENT LIMIT (A)
2
4
6
1
3
5
20
40
60
80
LT1371 G02
100
10
0
30
50
70
90
25
C AND
125
C
55
C
Switch Current Limit
vs Duty Cycle
SWITCH CURRENT (A)
0
SWITCH SATURATION VOLTAGE (V)
0.6
0.8
1.0
3.2
LT1371 G01
0.4
0.2
0.5
0.7
0.9
0.3
0.1
0
0.8
1.6
2.4
4.0
2.8
0.4
1.2
2.0
3.6
100
C
150
C
25
C
55
C
5
LT1371
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
TEMPERATURE (
C)
50
FEEDBACK INPUT CURRENT (nA)
400
500
600
150
LT1371 G11
300
200
0
0
50
100
100
800
700
25
25
75
125
V
FB
=V
REF
Feedback Input Current
vs Temperature
TEMPERATURE (
C)
50
50
NEGATIVE FEEDBACK INPUT CURRENT (
A)
30
0
0
50
75
LT1371 G12
40
10
20
25
25
100 125
150
V
NFB
=V
NFR
Negative Feedback Input Current
vs Temperature
V
C
Pin Threshold and High
Clamp Voltage vs Temperature
TEMPERATURE (
C)
50
0.4
V
C
PIN VOLTAGE (V)
0.6
1.0
1.2
1.4
2.4
1.8
0
50
75
LT1371 G10
0.8
2.0
2.2
1.6
25
25
100 125
150
V
C
HIGH CLAMP
V
C
THRESHOLD
PI
N
FU
N
CTIO
N
S
U
U
U
V
C
: The Compensation pin is used for frequency compen-
sation, current limiting and soft start. It is the output of the
error amplifier and the input of the current comparator.
Loop frequency compensation can be performed with an
RC network connected from the V
C
pin to ground.
FB: The Feedback pin is used for positive output voltage
sensing and oscillator frequency shifting. It is the invert-
ing input to the error amplifier. The noninverting input of
this amplifier is internally tied to a 1.245V reference. Load
on the FB pin should not exceed 250
A when NFB pin is
used. See Applications Information.
NFB: The Negative Feedback pin is used for negative
output voltage sensing. It is connected to the inverting
input of the negative feedback amplifier through a 100k
source resistor.
S/S (R and T7 Packages Only): Shutdown and Synchroni-
zation Pin. The S/S pin is logic level compatible. Shutdown
is active low and the shutdown threshold is typically 1.3V.
For normal operation, pull the S/S pin high, tie it to V
IN
or
leave it floating. To synchronize switching, drive the S/S
pin between 600kHz and 800kHz.
SHDN: (SW Package Only): The Shutdown pin is active
low and the shutdown threshold is typically 1.3V. For
normal operation, pull the SHDN pin high, tie it to V
IN
or
leave it floating.
SYNC (SW Package Only): To synchronize switching,
drive the SYNC pin between 600kHz and 800kHz. If not
used, the SYNC pin can be tied high, low or left floating.
V
IN
: Bypass Input Supply pin with a low ESR capacitor,
10
F or more. The regulator goes into undervoltage lock-
out when V
IN
drops below 2.5V. Undervoltage lockout
stops switching and pulls the V
C
pin low.
V
SW
: The Switch pin is the collector of the power switch
and has large currents flowing through it. Keep the traces
to the switching components as short as possible to
minimize radiation and voltage spikes.
GND: Tie all Ground pins to a good quality ground plane.
6
LT1371
BLOCK DIAGRA
M
W
OPERATIO
N
U
The LT1371 is a current mode switcher. This means that
switch duty cycle is directly controlled by switch current
rather than by output voltage. Referring to the block
diagram, the switch is turned ON at the start of each
oscillator cycle. It is turned OFF when switch current
reaches a predetermined level. Control of output voltage is
obtained by using the output of a voltage sensing error
amplifier to set current trip level. This technique has
several advantages. First, it has immediate response to
input voltage variations, unlike voltage mode switchers
which have notoriously poor line transient response.
Second, it reduces the 90
phase shift at mid-frequencies
in the energy storage inductor. This greatly simplifies
closed-loop frequency compensation under widely vary-
ing input voltage or output load conditions. Finally, it
allows simple pulse-by-pulse current limiting to provide
maximum switch protection under output overload or
short conditions. A low dropout internal regulator pro-
vides a 2.3V supply for all internal circuitry. This low
dropout design allows input voltage to vary from 2.7V to
25V with virtually no change in device performance. A
500kHz oscillator is the basic clock for all internal timing.
It turns ON the output switch via the logic and driver
circuitry. Special adaptive anti-sat circuitry detects onset
of saturation in the power switch and adjusts driver
current instantaneously to limit switch saturation. This
minimizes driver dissipation and provides very rapid turn-
off of the switch.
A 1.245V bandgap reference biases the positive input of
the error amplifier. The negative input of the amplifier is
brought out for positive output voltage sensing. The error
amplifier has nonlinear transconductance to reduce out-
put overshoot on start-up or overload recovery. When
the feedback voltage exceeds the reference by 40mV,
error amplifier transconductance increases 10 times,
which reduces output overshoot. The feedback input also
invokes oscillator frequency shifting, which helps pro-
tect components during overload conditions. When the
feedback voltage drops below 0.6V, the oscillator fre-
quency is reduced 5:1. Lower switching frequency allows
full control of switch current limit by reducing minimum
switch duty cycle.
+
NFBA
NFB
SHDN
S/S*
SYNC
FB
100k
50k
0.04
+
EA
V
C
V
IN
GND
LT1371 BD
GND SENSE
*R AND T7 PACKAGES ONLY
1.245V
REF
5:1 FREQUENCY
SHIFT
OSC
SYNC
SHUTDOWN
DELAY AND RESET
LOW DROPOUT
2.3V REG
ANTI-SAT
LOGIC
DRIVER
SW
SWITCH
+
IA
A
V
6
COMP
7
LT1371
APPLICATIO S I FOR ATIO
U
U
W
U
Unique error amplifier circuitry allows the LT1371 to
directly regulate negative output voltages. The negative
feedback amplifier's 100k source resistor is brought out
for negative output voltage sensing. The NFB pin regulates
at 2.49V while the amplifier output internally drives the
FB pin to 1.245V. This architecture, which uses the same
main error amplifier, prevents duplicating functions and
maintains ease of use. Consult LTC Marketing for units
that can regulate down to 1.25V.
The error signal developed at the amplifier output is
brought out externally. This pin (V
C
) has three different
functions. It is used for frequency compensation, current
limit adjustment and soft starting. During normal regula-
tor operation this pin sits at a voltage between 1V (low
output current) and 1.9V (high output current). The error
amplifier is a current output (g
m
) type, so this voltage can
be externally clamped for lowering current limit. Like-
wise, a capacitor coupled external clamp will provide soft
start. Switch duty cycle goes to zero if the V
C
pin is pulled
below the control pin threshold, placing the LT1371 in an
idle mode.
Positive Output Voltage Setting
The LT1371 develops a 1.245V reference (V
REF
) from the
FB pin to ground. Output voltage is set by connecting the
FB pin to an output resistor divider (Figure 1). The FB pin
bias current represents a small error and can usually be
ignored for values of R2 up to 7k. The suggested value for
R2 is 6.19k. The NFB pin is normally left open for positive
output applications. Positive fixed voltage versions are
available (consult LTC Marketing).
Negative Output Voltage Setting
The LT1371 develops a 2.49V reference (V
NFR
) from the
NFB pin to ground. Output voltage is set by connecting the
NFB pin to an output resistor divider (Figure 2). The
30
A NFB pin bias current (I
NFB
) can cause output
voltage errors and should not be ignored. This has been
accounted for in the formula in Figure 2. The suggested
value for R2 is 2.49k. The FB pin is normally left open for
negative output applications. See Dual Polarity Output
Voltage Sensing for limitations on FB pin loading when
using the NFB pin.
Dual Polarity Output Voltage Sensing
Certain applications benefit from sensing both positive
and negative output voltages. One example is the "Dual
Output Flyback Converter with Overvoltage Protection"
circuit shown in the Typical Applications section. Each
output voltage resistor divider is individually set as de-
scribed above. When both the FB and NFB pins are used,
R1
V
OUT
= V
REF
1 +
R2
FB
PIN
V
REF
V
OUT
( )
R1
R2
R1 = R2
1
(
)
V
OUT
1.245
LT1371 F01
the LT1371 acts to prevent either output from going
beyond its set output voltage. For example, in this applica-
tion if the positive output were more heavily loaded than
the negative, the negative output would be greater and
would regulate at the desired set-point voltage. The posi-
tive output would sag slightly below its set-point voltage.
This technique prevents either output from going unregu-
lated high at no load. Please note that the load on the FB
pin should not exceed 250
A when the NFB pin is used.
This situation occurs when the resistor dividers are used
at
both FB and NFB. True load on FB is not the full divider
current unless the positive output is shorted to ground.
See Dual Output Flyback Converter application.
APPLICATIO S I FOR ATIO
U
U
W
U
Figure 1. Positive Output Resistor Divider
Figure 2. Negative Output Resistor Divider
R1
V
OUT
= V
NFB
+ I
NFB
(R1)
1 +
R2
LT1371 F02
NFB
PIN
V
NFR
I
NFB
V
OUT
( )
R1
R2
R1 =
+ 30 10
6
V
OUT
2.49
( ) ( )
2.49
R2
8
LT1371
Shutdown and Synchronization
The 7-pin R and T7 package devices have a dual function
S/S pin which is used for both shutdown and synchroni-
zation. The SW package device has both a Shutdown
(SHDN) pin and a Synchronization (SYNC) pin which can
be used separately or tied together. These pins are logic
level compatible and can be pulled high, tied to V
IN
or left
floating for normal operation. A logic low on the S/S pin or
SHDN pin activates shutdown, reducing the part's supply
current to 12
A. Typical synchronization range is from
1.05 to 1.8 times the part's natural switching frequency,
but is only guaranteed between 600kHz and 800kHz. A
12
s resetable shutdown delay network guarantees the
part will not go into shutdown while receiving a synchro-
nization signal when the functions are combined.
Caution should be used when synchronizing above 700kHz
because at higher sync frequencies the amplitude of the
internal slope compensation used to prevent subharmonic
switching is reduced. This type of subharmonic switching
only occurs when the duty cycle of the switch is above 50%.
Higher inductor values will tend to eliminate problems.
Thermal Considerations
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces-
sive die temperatures. Typical thermal resistance is
30
C/W for the R package and 50
C/W for the SW and T7
packages but these numbers will vary depending on the
mounting techniques (copper area, air flow, etc.). Heat is
transferred from the R and T7 packages via the tab and
from the SW package via pins 4 to 7 and 14 to 17.
Average supply current (including driver current) is:
I
IN
= 4mA + DC [I
SW
/60 + I
SW
(0.004)]
I
SW
= switch current
DC = switch duty cycle
Switch power dissipation is given by:
P
SW
= (I
SW
)
2
(R
SW
)(DC)
R
SW
= output switch ON resistance
Total power dissipation of the die is the sum of supply
current times supply voltage, plus switch power:
P
D(TOTAL)
= (I
IN
)(V
IN
) + P
SW
Surface mount heat sinks are also becoming available
which can lower package thermal resistance by 2 or 3
times. One manufacturer is Wakefield Engineering who
offers surface mount heat sinks for both the R package
(DD) and SW package (SW20) and can be reached at (617)
245-5900.
Choosing the Inductor
For most applications the inductor will fall in the range of
2.2
H to 22
H. Lower values are chosen to reduce physi-
cal size of the inductor. Higher values allow more output
current because they reduce peak current seen by the
power switch, which has a 3A limit. Higher values also
reduce input ripple voltage and reduce core loss.
When choosing an inductor you might have to consider
maximum load current, core and copper losses, allowable
component height, output voltage ripple, EMI, fault
current in the inductor, saturation and, of course, cost.
The following procedure is suggested as a way of handling
these somewhat complicated and conflicting requirements.
1. Assume that the average inductor current for a boost
converter is equal to load current times V
OUT
/ V
IN
and
decide whether or not the inductor must withstand
continuous overload conditions. If average inductor
current at maximum load current is 1A, for instance, a
1A inductor may not survive a continuous 3A overload
condition. Also be aware that boost converters are not
short-circuit protected and that, under output short
conditions, inductor current is limited only by the
available current of the input supply.
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be significantly higher than output current, espe-
cially with smaller inductors and lighter loads, so don't
omit this step. Powdered iron cores are forgiving
because they saturate softly, whereas ferrite cores
APPLICATIO S I FOR ATIO
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9
LT1371
APPLICATIO S I FOR ATIO
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saturate abruptly and other core materials fall in be-
tween. The following formula assumes continuous
mode operation but it errs only slightly on the high side
for discontinuous mode, so it can be used for all
conditions.
I
PEAK
= (I
OUT
)
V
IN
= Minimum Input Voltage
f = 500kHz Switching Frequency
+
V
OUT
V
IN
V
IN
(V
OUT
V
IN
)
2(f)(L)(V
OUT
)
)
)
3. Decide if the design can tolerate an "open" core geom-
etry, like a rod or barrel, which has high magnetic field
radiation, or whether it needs a closed core, like a
toroid, to prevent EMI problems. One would not want an
open core next to a magnetic storage media, for in-
stance! This is a tough decision because the rods or
barrels are temptingly cheap and small and there are no
helpful guidelines to calculate when the magnetic field
radiation will be a problem.
4. Start shopping for an inductor which meets the re-
quirements of core shape, peak current (to avoid
saturation), average current (to limit heating) and fault
current. If the inductor gets too hot, wire insulation will
melt and cause turn-to-turn shorts. Keep in mind that
all good things like high efficiency, low profile and high
temperature operation will increase cost, sometimes
dramatically.
5. After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the LTC Applications Department if
you feel uncertain about the final choice. They have
experience with a wide range of inductor types and can
tell you about the latest developments in low profile,
surface mounting, etc.
Output Capacitor
The output capacitor is normally chosen by its effective
series resistance (ESR), because this is what determines
output ripple voltage. At 500kHz any polarized capacitor
is essentially resistive. To get low ESR takes
volume, so
physically smaller capacitors have high ESR. The ESR
range needed for typical LT1371 applications is 0.025
to 0.2
. A typical output capacitor is an AVX type TPS,
22
F at 25V (2 each), with a guaranteed ESR less than
0.2
. This is a "D" size surface mount solid tantalum
capacitor. TPS capacitors are specially constructed and
tested for low ESR, so they give the lowest ESR for a given
volume. To further reduce ESR, multiple output capaci-
tors can be used in parallel. The value in microfarads is
not particularly critical, and values from 22
F to greater
than 500
F work well, but you cannot cheat mother
nature on ESR. If you find a tiny 22
F solid tantalum
capacitor, it will have high ESR and output ripple voltage
will be terrible. Table 1 shows some typical solid tantalum
surface mount capacitors.
Table 1. Surface Mount Solid Tantalum Capacitor
ESR and Ripple Current
E CASE SIZE
ESR (MAX
)
RIPPLE CURRENT (A)
AVX TPS, Sprague 593D
0.1 to 0.3
0.7 to 1.1
AVX TAJ
0.7 to 0.9
0.4
D CASE SIZE
AVX TPS, Sprague 593D
0.1 to 0.3
0.7 to 1.1
AVX TAJ
0.9 to 2.0
0.36 to 0.24
C CASE SIZE
AVX TPS
0.2 (Typ)
0.5 (Typ)
AVX TAJ
1.8 to 3.0
0.22 to 0.17
B CASE SIZE
AVX TAJ
2.5 to 10
0.16 to 0.08
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true and AVX type TPS capacitors are
specially tested for surge capability, but surge ruggedness
is not a critical issue with the
output capacitor. Solid
tantalum capacitors fail during very high
turn-on surges,
which do not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead-shorted, do not harm the capacitors.
Single inductor boost regulators have large RMS ripple
current in the output capacitor, which must be rated to
handle the current. The formula to calculate this is:
10
LT1371
APPLICATIO S I FOR ATIO
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generates a loop "zero" at 5kHz to 50kHz that is instrumen-
tal in giving acceptable loop phase margin. Ceramic ca-
pacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
They are appropriate for input bypassing because of their
high ripple current ratings and tolerance of turn-on surges.
Output Diode
The suggested output diode (D1) is a 1N5821 Schottky or
its Motorola equivalent MBR330. It is rated at 3A average
forward current and 30V reverse voltage. Typical forward
voltage is 0.6V at 3A. The diode conducts current only
during switch OFF time. Peak reverse voltage for boost
converters is equal to regulator output voltage. Average
forward current in normal operation is equal to output
current.
Frequency Compensation
Loop frequency compensation is performed on the output
of the error amplifier (V
C
pin) with a series RC network.
The main pole is formed by the series capacitor and the
output impedance (
500k
) of the error amplifier. The
pole falls in the range of 2Hz to 20Hz. The series resistor
creates a "zero" at 1kHz to 5kHz, which improves loop
stability and transient response. A second capacitor, typi-
cally one-tenth the size of the main compensation capaci-
tor, is sometimes used to reduce the switching frequency
ripple on the V
C
pin. V
C
pin ripple is caused by output
voltage ripple attenuated by the output divider and multi-
plied by the error amplifier. Without the second capacitor,
V
C
pin ripple is:
V
C
Pin Ripple =
V
RIPPLE
= Output ripple (V
PP
)
g
m
= Error amplifier transconductance
(
1500
mho)
R
C
= Series resistor on V
C
pin
V
OUT
= DC output voltage
1.245(V
RIPPLE
)(g
m
)(R
C
)
(V
OUT
)
To prevent irregular switching, V
C
pin ripple should be
kept below 50mV
PP
.
Worst-case V
C
pin ripple occurs at
Output Capacitor Ripple Current (RMS)
I
RIPPLE
(RMS) = I
OUT
= I
OUT
V
OUT
V
IN
V
IN
DC
1 DC
DC = Switch Duty Cycle
Input Capacitors
The input capacitor of a boost converter is less critical due
to the fact that the input current waveform is triangular and
does not contain large squarewave currents as is found in
the output capacitor. Capacitors in the range of 10
F to
100
F, with an ESR of 0.2
or less, work well up to full 3A
switch current. Higher ESR capacitors may be acceptable
at low switch currents. Input capacitor ripple current for a
boost converter is :
I
RIPPLE
=
f = 500kHz Switching Frequency
0.3(V
IN
)(V
OUT
V
IN
)
(f)(L)(V
OUT
)
The input capacitor can see a very high surge current when
a battery or high capacitance source is connected "live"
and solid tantalum capacitors can fail under this condition.
Several manufacturers have developed tantalum capaci-
tors specially tested for surge capability (AVX TPS series,
for instance) but even these units may fail if the input
voltage approaches the maximum voltage rating of the
capacitor during a high surge. AVX recommends derating
capacitor voltage by 2:1 for high surge applications.
Ceramic, OS-CON and aluminum electrolytic capacitors
may also be used and have a high tolerance to turn-on
surges.
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
11
LT1371
APPLICATIO S I FOR ATIO
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maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047
F capacitor on the V
C
pin reduces
switching frequency ripple to only a few millivolts. A low
value for R
C
will also reduce V
C
pin ripple, but loop phase
margin may be inadequate.
Layout Considerations
For maximum efficiency, LT1371 switch rise and fall times
are made as short as possible. To prevent radiation and
high frequency resonance problems, proper layout of the
components connected to the switch node is essential. B
field (magnetic) radiation is minimized by keeping output
diode, Switch pin and output bypass capacitor leads as
short as possible. Figures 3, 4 and 5 show recommended
positions for these components. E field radiation is kept
low by minimizing the length and area of all traces con-
nected to the Switch pin. A ground plane should always be
used under the switcher circuitry to prevent interplane
coupling.
The high speed switching current path is shown schemati-
cally in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, output diode and output capacitor is
the only one containing nanosecond rise and fall times.
Keep this path as short as possible.
V
IN
S/S
GND
FB
V
SW
V
C
NFB
CONNECT
GROUND PIN
AND TAB DIRECTLY
TO GROUND PLANE
C
D
KEEP PATH FROM
V
SW
,
OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
C
LT1371 F03
Figure 3. Layout Considerations-- R Package
V
IN
S/S
GND
FB
V
SW
V
C
NFB
CONNECT
GROUND PIN
AND TAB DIRECTLY
TO GROUND PLANE.
TAB MAY BE
SOLDERED OR
BOLTED TO
GROUND PLANE*
C
D
KEEP PATH FROM
V
SW
,
OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
*SEE T7 PACKAGE LAYOUT CONSIDERATIONS FOR VERTICAL MOUNTING
OF THE T7 PACKAGE
C
LT1371 F04
Figure 4. Layout Considerations-- T7 Package
Figure 6
LOAD
V
OUT
L1
SWITCH
NODE
LT1371 F06
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
D
CONNECT ALL GROUND PINS TO GROUND PLANE
C
C
KEEP PATH FROM
V
SW
,
OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
LT1371 F05
V
SW
NC
V
SW
GND
GND
GND
GND
NC
NC
GND
V
C
FB
NFB
GND
GND
GND
GND
SHDN
SYNC
V
IN
Figure 5. Layout Considerations-- SW Package
12
LT1371
APPLICATIO S I FOR ATIO
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LT1371T7
V
IN
V
IN
V
C
TAB
SYSTEM GROUND
FLOATING NODE
(TAB TIES INTERNALLY
TO PIN 4 GROUND)
4
2
1
5
7
GND
GND
FB
LT1371 F07
V
SW
V
OUT
Figure 7. Tab Connections for Vertically Mounted T7 Package
T7 Package Layout Considerations
Electrical connection to the tab of a T7 package is required
for proper device operation. If the tab is tied directly to the
ground plane (Figure 4) no other considerations are nec-
essary. If the tab is not connected directly to the ground
plane, as in a vertically mounted application, a separate
electrical connection from the tab to a "floating node" is
required. Ground returns for the V
IN
capacitor, V
C
compo-
nents and output feedback resistor divider are then con-
nected to the floating node. This is shown schematically in
Figure 7. All other system ground connections are made to
Pin 4.
The electrical connection from the T7 package tab to the
floating node must be a low resistance (< 0.1
), low
inductance (< 20nH) path which can be accomplished with
a jumper wire or an electrically conductive heat sink.
Bolt the jumper wire directly to the tab using a solder tail
to maintain low resistance. The jumper wire length should
not exceed 3/4 inch of 24 AWG gauge wire or larger to
minimize the inductance.
Vertically mounted electrically conductive heat sinks are
available from many heat sink manufacturers. These heat
sinks also have tabs that solder directly to the board
creating the required low resistance, low inductance path
from the tab to the floating node. The tab should be bolted
or soldered directly to the heat sink to maintain low
resistance. Heat sinks are available in clip-on styles but are
only recommended if the tab to heat sink contact resis-
tance can be maintained below 0.1
for the life of the
product.
More Help
For more detailed information on switching regulator
circuits, please see Application Note 19. Linear Technol-
ogy also offers a computer software program,
SwitcherCAD, to assist in designing switching converters.
In addition, our Applications Department is always ready
to lend a helping hand.
13
LT1371
TYPICAL APPLICATIO
N
S
N
U
Positive-to-Negative Converter with Direct Feedback
Dual Output Flyback Converter with Overvoltage Protection
2 Li-Ion Cells to 5V SEPIC Converter**
Single Li-Ion Cell to 5V
LT1371
V
IN
GND
V
IN
4V TO 9V
V
C
FB
LT1371 TA05
V
SW
S/S
C1
33
F
20V
C4
0.047
F
C5
0.0047
F
R1
2k
R3
6.19k
1%
R2
18.7k
1%
V
OUT
5V
C3
100
F
10V
2
ON
OFF
L1A*
10
H
L1B*
10
H
C2
4.7
F
C1 = AVX TPSD 336M020R0200
C2 = TOKIN 1E475ZY5U-C304
C3 = AVX TPSD107M010R0100
SINGLE INDUCTOR WITH TWO WINDINGS
COILTRONICS CTX10-4
INPUT VOLTAGE MAY BE GREATER OR
LESS THAN OUTPUT VOLTAGE
+
+
MBRS330T3
V
IN
4V
5V
7V
9V
I
OUT
0.85A
1A
1.3A
1.5A
MAX I
OUT
*
**
LT1371
V
IN
V
C
V
IN
2.7V TO 13V
*COILTRONICS CTX10-4
GND
NFB
LT1371 TA03
V
SW
S/S
D2
P6KE-15A
D3
1N4148
D1
MBRS330T3
C1
100
F
C2
0.047
F
C3
0.0047
F
R1
2k
R3
2.49k
1%
R2
2.49k
1%
V
OUT
5V
+
C4
100
F
2
+
ON
OFF
V
IN
3V
5V
9V
I
OUT
0.6A
1.0A
1.5A
2
1
4
T1*
3
MAX I
OUT
LT1371
V
IN
V
C
GND
FB
LT1371 TA06
V
SW
S/S
L1*
C1**
100
F
10V
SINGLE
Li-Ion
CELL
C4**
100
F
10V
2
C2
0.047
F
C3
0.0047
F
R3
2k
R2
6.19k
1%
R1
18.7k
1%
V
OUT
5V
D1
MBRS320T3
ON
OFF
*
**
COILCRAFT DO3316P-103
AVX TPSD107M010R0100
+
+
+
V
IN
2.7V
3.3V
3.6V
I
OUT
1.2A
1.6A
1.8A
MAX I
OUT
LT1371
V
IN
FB
V
C
V
IN
2.7V TO 10V
*DALE LPE-5047-100MB
GND
NFB
LT1371 TA04
V
SW
S/S
P6KE-20A
1N4148
MBRS360T3
MBRS360T3
C1
22
F
R2
6.19k
1%
R1
68.1k
1%
C2
0.047
F
C3
0.0047
F
R3
2k
R5
2.49k
1%
R4
12.1k
1%
V
OUT
15V
V
OUT
15V
+
C4
47
F
+
C5
47
F
+
ON
OFF
2, 3
8, 9
7
T1*
4
10
1
14
LT1371
TYPICAL APPLICATIO
N
S
N
U
20W CCFL Supply
Laser Power Supply
LASER
190
1%
1N4002
(ALL)
0.1
F
10k
V
IN
10
F
V
C
V
IN
FB
GND
2.2
F
V
IN
12V TO 25V
150
MUR405
L2
82
H
LT1371
L1
5
4
1
3
2
8
11
HV DIODES
1800pF
10kV
0.01
F
5kV
1800pF
10kV
47k
5W
2.2
F
0.47
F
L1 =
L2 =
Q1, Q2 =
0.47
F =
HV DIODES =
LASER =
COILTRONICS CTX02-11128
GOWANDA GA40-822K
ZETEX ZTX849
WIMA 3X 0.15
F TYPE MKP-20
SEMTECH-FM-50
HUGHES 3121H-P
COILTRONICS (407) 241-7876
+
+
10k
LT1371 TA08
V
SW
+
Q1
Q2
140
1
F
2.2
F
V
C
V
IN
FB
GND
2.2
F
V
IN
9V
TO
15V
150
MUR405
L2
15
H
LT1371
L1
5
4
1
3
2
8
11
22
F
0.47
F
L1=COILTRONICS CTX02-11128
L2=COILCRAFT DO3316P-153
Q1, Q2=ZETEX ZTX849, ZDT1048 OR ROHM 2SC5001
0.47
F=WIMA 3X 0.15
F TYPE MKP-20
COILTRONICS (407) 241-7876
+
+
10k
LT1371 TA07
V
SW
1N4148
LAMP
47pF
1N4148
1N4148
INTENSITY
CONTROL
22k
Q1
Q2
+
15
LT1371
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
N
U
Dimensions in inches (millimeters) unless otherwise noted.
R Package
7-Lead Plastic DD Pak
(LTC DWG # 05-08-1462)
S20 (WIDE) 0695
NOTE 1
0.496 0.512*
(12.598 13.005)
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
0.394 0.419
(10.007 10.643)
9
10
11
12
0.037 0.045
(0.940 1.143)
0.004 0.012
(0.102 0.305)
0.093 0.104
(2.362 2.642)
0.050
(1.270)
TYP
0.014 0.019
(0.356 0.482)
TYP
0
8
TYP
NOTE 1
0.009 0.013
(0.229 0.330)
0.016 0.050
(0.406 1.270)
0.291 0.299**
(7.391 7.595)
45
0.010 0.029
(0.254 0.737)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
SW Package
20-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
R (DD7) 0695
0.026 0.036
(0.660 0.914)
0.143
+0.012
0.020
(
)
3.632
+0.305
0.508
0.040 0.060
(1.016 1.524)
0.013 0.023
(0.330 0.584)
0.095 0.115
(2.413 2.921)
0.004
+0.008
0.004
(
)
0.102
+0.203
0.102
0.050
0.012
(1.270
0.305)
0.059
(1.499)
TYP
0.045 0.055
(1.143 1.397)
0.165 0.180
(4.191 4.572)
0.330 0.370
(8.382 9.398)
0.060
(1.524)
TYP
0.390 0.415
(9.906 10.541)
15
TYP
0.300
(7.620)
0.075
(1.905)
0.183
(4.648)
0.060
(1.524)
0.060
(1.524)
0.256
(6.502)
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAK SINK
16
LT1371
LINEAR TECHNOLOGY CORPORATION 1995
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX
: (408) 434-0507
q
TELEX
: 499-3977
LT/GP 0996 5K REV A PRINTED IN THE USA
PACKAGE DESCRIPTIO
N
U
Dimensions in inches (millimeters) unless otherwise noted.
T7 Package
7-Lead Plastic TO-220 (Standard)
(LTC DWG # 05-08-1422)
PART NUMBER
DESCRIPTION
COMMENTS
LT1171
100kHz 2.5A Boost Switching Regulator
Good for Up to V
IN
= 40V
LTC
1265
12V 1.2A Monolithic Buck Converter
Converts 5V to 3.3V at 1A with 90% Efficiency
LT1302
Micropower 2A Boost Converter
Converts 2V to 5V at 600mA in SO-8 Packages
LT1372
500kHz 1.5A Boost Switching Regulator
Also Regulates Negative Flyback Outputs
LT1373
Low Supply Current 250kHz 1.5A Boost Switching Regulator
90% Efficient Boost Converter with Constant Frequency
LT1376
500kHz 1.5A Buck Switching Regulator
Steps Down from Up to 25V Using 4.7
H Inductors
LT1512
500kHz 1.5A SEPIC Battery Charger
Input Voltage May Be Greater or Less Than Battery Voltage
LT1513
500kHz 3A SEPIC Battery Charger
Input Voltage May Be Greater or Less Than Battery Voltage
RELATED PARTS
0.040 0.060
(1.016 1.524)
0.026 0.036
(0.660 0.914)
T7 (TO-220) (FORMED) 0695
0.135 0.165
(3.429 4.191)
0.700 0.728
(17.780 18.491)
0.045 0.055
(1.143 1.397)
0.165 0.180
(4.293 4.572)
0.095 0.115
(2.413 2.921)
0.013 0.023
(0.330 0.584)
0.620
(15.75)
TYP
0.155 0.195
(3.937 4.953)
0.152 0.202
(3.860 5.130)
0.260 0.320
(6.604 8.128)
0.147 0.155
(3.734 3.937)
DIA
0.390 0.415
(9.906 10.541)
0.330 0.370
(8.382 9.398)
0.460 0.500
(11.684 12.700)
0.570 0.620
(14.478 15.748)
0.230 0.270
(5.842 6.858)
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