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1
LT1970
1970f
500mA Power Op Amp with
Adjustable Precision Current Limit
s
500mA Minimum Output Current
s
Independent Adjustment of Source and
Sink Current Limits
s
2% Current Limit Accuracy
s
Operates with Single or Split Supplies
s
Shutdown/Enable Control Input
s
Open Collector Status Flags:
Sink Current Limit
Source Current Limit
Thermal Shutdown
s
Fail Safe Current Limit and Thermal Shutdown
s
1.6V/
s Slew Rate
s
3.6MHz Gain Bandwidth Product
s
Fast Current Limit Response: 2MHz Bandwidth
s
Specified Temperature Range: 40
C to 85
C
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
Automatic Test Equipment
s
Laboratory Power Supplies
s
Motor Drivers
s
Thermoelectric Cooler Driver
A
V
= 2 Amplifier with Adjustable
500mA Full-Scale
Current Limit and Fault indication
Current Limited Sinewave Into 10
Load
V
CC
COMMON
V
EE
V
+
V
VC
SRC
VC
SNK
ISNK
ISRC
SENSE
SENSE
+
TSD
I
OUT
OUT
R
CS
1
1/4W
3k
+IN
15V
LT1970
15V
15V
IN
LOAD
R1
10k
R2
10k
1970 TA01
V
LIMIT
0V TO 5V
V
IN
V
LIMIT
10 R
CS
I
OUT(LIMIT)
=
The LT
1970 is a
500mA power op amp with precise
externally controlled current limiting. Separate control
voltages program the sourcing and sinking current limit
sense thresholds with 2% accuracy. Output current may
be boosted by adding external power transistors.
The circuit operates with single or split power supplies from
5V to 36V total supply voltage. In normal operation, the
input stage supplies and the output stage supplies are con-
nected (V
CC
to V
+
and V
EE
to V
). To reduce power dissi-
pation it is possible to power the output stage (V
+
, V
) from
independent, lower voltage rails. The amplifier is unity-gain
stable with a 3.6MHz gain bandwidth product and slews at
1.6V/
s. The current limit circuits operate with a 2MHz re-
sponse between the VC
SRC
or VC
SNK
control inputs and
the amplifier output.
Open collector status flags signal current limit circuit
activation, as well as thermal shutdown of the amplifier. An
enable logic input puts the amplifier into a low power, high
impedance output state when pulled low. Thermal shut-
down and a
800mA fixed current limit protect the chip
under fault conditions.
The LT1970 is packaged in a 20-lead TSSOP package with
a thermally conductive copper bottom plate to facilitate
heat sinking.
V
LOAD
4V
2V
0V
2V
VC
SRC
= 4V
20
s/DIV
1970 TA02
VC
SNK
= 2V
R
CS
= 1
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LT1970
1970f
(Note 1)
Supply Voltage (V
CC
to V
EE
).................................... 36V
Positive High Current Supply (V
+
) .................. V
to V
CC
Negative High Current Supply(V
) ................... V
EE
to V
+
Amplifier Output (OUT) ..................................... V
to V
+
Current Sense Pins
(SENSE
+
, SENSE
, FILTER) .......................... V
to V
+
Logic Outputs (ISRC, ISNK, TSD) ....... COMMON to V
CC
Input Voltage (IN, +IN) .......... V
EE
0.3V to V
EE
+ 36V
Input Current ....................................................... 10mA
Current Control Inputs
(VC
SRC
, VC
SNK
) ............. COMMON to COMMON + 7V
Enable Logic Input .............................. COMMON to V
CC
COMMON ..................................................... V
EE
to V
CC
Output Short-Circuit Duration ......................... Indefinite
Operating Temperature Range (Note 2) .. 40
C to 85
C
Specified Temperature Range (Note 3) ... 40
C to 85
C
Maximum Junction Temperature ......................... 150
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
ORDER PART
NUMBER
LT1970CFE
T
JMAX
= 150
C,
JA
= 40
C/ W (NOTE 6)
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= 25
C. See Test Circuit for standard test conditions.
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
ELECTRICAL CHARACTERISTICS
FE PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
V
EE
V
OUT
SENSE
+
FILTER
SENSE
V
CC
IN
+IN
V
EE
V
EE
V
+
TSD
ISNK
ISRC
ENABLE
COMMON
VC
SRC
VC
SNK
V
EE
+
Consult LTC Marketing for parts specified with wider operating temperature ranges.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Op Amp Characteristics
V
OS
Input Offset Voltage
200
600
V
0
C < T
A
< 70
C
q
800
V
40
C < T
A
< 85
C
q
1000
V
Input Offset Voltage Drift (Note 4)
q
10
4
10
V/
C
I
OS
Input Offset Current
V
CM
= 0V
q
100
100
nA
I
B
Input Bias Current
V
CM
= 0V
q
600
160
nA
Input Noise Voltage
0.1Hz to 10Hz
3
V
P-P
e
n
Input Noise Voltage Density
1kHz
15
nV/
Hz
i
n
Input Noise Current Density
1kHz
3
pA/
Hz
R
IN
Input Resistance
Common Mode
500
k
Differential Mode
100
k
C
IN
Input Capacitance
Pin 8 and Pin 9 to Ground
6
pF
V
CM
Input Voltage Range
Typical
14.5
13.6
V
Guaranteed by CMRR Test
q
12.0
12.0
V
CMRR
Common Mode Rejection Ratio
12V < V
CM
< 12V
q
92
105
dB
PSRR
Power Supply Rejection Ratio
V
EE
= V
= 5V, V
CC
= V
+
= 3V to 30V
q
90
100
dB
V
EE
= V
= 5V, V
CC
= 30V, V
+
= 2.5V to 30V
q
110
130
dB
V
EE
= V
= 3V to 30V, V
CC
= V
+
= 5V
q
90
100
dB
V
EE
= 30V, V
= 2.5V to 30V, V
CC
= V
+
= 5V
q
110
130
dB
UNDERSIDE METAL CONNECTED TO V
EE
3
LT1970
1970f
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= 25
C. See Test Circuit for standard test conditions.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
A
VOL
Large-Signal Voltage Gain
R
L
= 1k, 12.5V < V
OUT
< 12.5V
100
150
V/mV
q
75
V/mV
R
L
= 100
, 12.5V < V
OUT
< 12.5V
80
120
V/mV
q
40
V/mV
R
L
= 10
, 5V < V
OUT
< 5V, V
+
= V
= 8V
20
60
V/mV
q
5
V/mV
V
OL
Output Sat Voltage Low
V
OL
= V
OUT
V
R
L
= 100, V
CC
= V
+
= 15V, V
EE
= V
= 15V
q
1.9
2.4
V
R
L
= 10, V
CC
= V
EE
= 15V, V
+
= V
= 5V
0.8
V
V
OH
Output Sat Voltage High
V
OH
= V
+
V
OUT
R
L
= 100, V
CC
= V
+
= 15V, V
EE
= V
= 15V
q
1.7
2.2
V
R
L
= 10, V
CC
= V
EE
= 15V, V
+
= V
= 5V
1.0
V
I
SC
Output Short-Circuit Current
Output Low, R
SENSE
= 0
500
800
1200
mA
Output High, R
SENSE
= 0
1000
800
500
mA
SR
Slew Rate
10V < V
OUT
< 10V, R
L
= 1k
0.7
1.6
V/
s
FPBW
Full Power Bandwidth
V
OUT
= 10V
PEAK
(Note 5)
11
kHz
GBW
Gain Bandwidth Product
f = 10kHz
3.6
MHz
t
S
Settling Time
0.01%, V
OUT
= 0V to 10V, A
V
= 1, R
L
= 1k
8
s
Current Sense Characteristics
V
SENSE(MIN)
Minimum Current Sense Voltage
VC
SRC
= VC
SNK
= 0V
0.1
4
7
mV
q
0.1
10
mV
V
SENSE(4%)
Current Sense Voltage 4% of Full Scale
VC
SRC
= VC
SNK
= 0.2V
q
15
20
25
mV
V
SENSE(10%)
Current Sense Voltage 10% of Full Scale
VC
SRC
= VC
SNK
= 0.5V
q
45
50
55
mV
V
SENSE(FS)
Current Sense Voltage 100% of Full Scale
VC
SRC
= VC
SNK
= 5V
490
500
510
mV
q
480
500
520
mV
I
BI
Current Limit Control Input Bias Current
VC
SRC
, VC
SNK
Pins
q
1
0.2
0.1
A
I
SENSE
SENSE
Input Current
0V < (VC
SRC
, VC
SNK
) < 5V
q
200
200
nA
I
FILTER
FILTER Input Current
0V < (VC
SRC
, VC
SNK
) < 5V
q
200
200
nA
I
SENSE
+
SENSE
+
Input Current
VC
SRC
= VC
SNK
= 0V
q
500
500
nA
VC
SRC
= 5V, VC
SNK
= 0V
q
200
250
300
A
VC
SRC
= 0V, VC
SNK
= 5V
q
300
250
200
A
VC
SRC
= VC
SNK
= 5V
q
25
25
A
Current Sense Change with Output Voltage VC
SRC
= VC
SNK
= 5V, 12.5V < V
OUT
< 12.5V
q
0.1
0.1
%
Current Sense Change with Supply Voltage VC
SRC
= VC
SNK
= 5V, 6V < (V
CC
, V
+
) < 18V
0.05
%
2.5V < V
+
< 18V, V
CC
= 18V
0.01
%
18V < (V
EE
, V
) < 2.5V
0.05
%
18V < V
< 2.5V, V
EE
= 18V
0.01
%
Current Sense Bandwidth
2
MHz
R
CSF
Resistance FILTER to SENSE
q
750
1000
1250
Logic I/O Characteristics
Logic Output Leakage ISRC, ISNK, TSD
V = 15V
q
1
A
Logic Low Output Level
I = 5mA
q
0.2
0.4
V
Logic Output Current Limit
q
25
mA
V
ENABLE
Enable Logic Threshold
q
0.8
1.6
2.4
V
I
ENABLE
Enable Pin Bias Current
q
1
1
A
4
LT1970
1970f
Warm-Up Drift V
IO
vs Time
Input Bias Current vs V
CM
COMMON MODE INPUT VOLTAGE (V)
15 12 9 6 3
0
3
6
9
12 15
INPUT BIAS CURRENT (nA)
100
120
140
160
180
200
220
240
260
1970 G05
V
S
=
15V
I
BIAS
+I
BIAS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
SUPPLY
Total Supply Current
V
CC
, V
+
and V
, V
EE
Connected
q
7
13
mA
I
CC
V
CC
Supply Current
V
CC
, V
+
and V
, V
EE
Separate
q
3
7
mA
I
CC(STBY)
Supply Current Disabled
V
CC
, V
+
and V
, V
EE
Connected, V
ENABLE
0.8V
q
0.6
1.5
mA
t
ON
Turn-On Delay
(Note 7)
10
s
t
OFF
Turn-Off Delay
(Note 7)
10
s
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= 25
C. See Test Circuit for standard test conditions.
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1970C is guaranteed functional over the operating
temperature range of 40
C and 85
C.
Note 3: The LT1970C is guaranteed to meet specified performance from
0
C to 70
C. The LT1970C is designed, characterized and expected to
meet specified performance from 40
C to 85
C but is not tested or QA
sampled at these temperatures.
Note 4: This parameter is not 100% tested.
Note 5: Full power bandwidth is calculated from slew rate measurements:
FPBW = SR/(2
V
P
)
Note 6: Thermal resistance varies depending upon the amount of PC board
metal attached to the device. If the maximum dissipation of the package is
exceeded, the device will go into thermal shutdown and be protected.
Note 7: Turn-on and turn-off delay are measured from V
ENABLE
crossing
1.6V to the OUT pin at 90% of normal output voltage.
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Total Supply Current
vs Supply Voltage
SUPPLY VOLTAGE (
V)
0
14
TOTAL SUPPLY CURRENT (mA)
10
6
2
14
6
4
8
10
18
1970 G15
10
2
12
8
4
12
4
8
0
2
6
12
14
16
I
CC
+ I
V
+
I
EE
+ I
V
25
C
25
C
55
C
55
C
125
C
125
C
0V
V
OS
1000 (50mV/DIV)
TIME (100ms/DIV)
1970 G04
5
LT1970
1970f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Slew Rate vs Supply Voltage
Slew Rate vs Temperature
TEMPERATURE (
C)
50
25
0
SLEW RATE (V/
s)
1.0
2.5
0
50
75
1970 G24
0.5
2.0
1.5
25
100
125
V
S
=
15V
FALLING
RISING
SUPPLY VOLTAGE (
V)
4
SLEW RATE (V/
s)
1.7
10
1970 G23
1.4
1.2
6
8
12
1.1
1.0
1.8
1.6
1.5
1.3
14
16
18
FALLING
RISING
A
V
= 1
R
F
= R
G
= 1k
T
A
= 25
C
Supply Current vs Supply Voltage
Open-Loop Gain and Phase
vs Frequency
Phase Margin vs Supply Voltage
SUPPLY VOLTAGE (
V)
2
4
6
0
SUPPLY CURRENT (mA)
0.5
1.5
2.0
2.5
14
16
18
4.5
I
V
+
I
V
1870 G16
1.0
8
10
12
20
3.0
3.5
4.0
T
A
= 25
C
V
CC
= V
+
= V
EE
= V
I
VCC
I
VEE
FREQUENCY (Hz)
100
1k
10
OPEN-LOOP GAIN (dB)
PHASE MARGIN (DEG)
20
30
40
50
10k
100k
1M
10M
100M
1970 G18
0
10
20
30
60
70
40
50
60
70
80
30
20
10
0
90
100
PHASE
GAIN
TOTAL SUPPLY VOLTAGE (V)
0
40
PHASE MARGIN (DEG)
42
46
48
50
60
54
8
16
20
36
1970 G21
44
56
58
52
4
12
24
28
32
A
V
= 1
R
F
= R
G
= 1k
T
A
= 25
C
V
OUT
= V
S
/2
Large-Signal Response, A
V
= 1
Small-Signal Response, A
V
= 1
Small-Signal Response, A
V
= 1
10V
0V
10V
R
L
= 1k
20
s/DIV
1970 G40
C
L
= 1000pF
R
L
= 1k
500ns/DIV
1970 G41
R
L
= 1k
2
s/DIV
1970 G42
C
L
= 1000pF
Large-Signal Response, A
V
= 1
10V
0V
10V
R
L
= 1k
20
s/DIV
1970 G39
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