LTC2401/LTC2402

1-/2-Channel 24-Bit

Power

No Latency

ADCs in MSOP-10

Weight Scales

Direct Temperature Measurement

Gas Analyzers

Strain Gauge Transducers

Instrumentation

Data Acquisition

Industrial Process Control

No Latency

is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

Pseudo Differential Bridge Digitizer

, LTC and LT are registered trademarks of Linear Technology Corporation.

The LTC

2401/LTC2402 are 1- and 2-channel 2.7V to 5.5V

micropower 24-bit analog-to-digital converters with an
integrated oscillator, 4ppm INL and 0.6ppm RMS noise.
These ultrasmall devices use delta-sigma technology and
a new digital filter architecture that settles in a single cycle.
This eliminates the latency found in conventional

converters and simplifies multiplexed applications.

Through a single pin, the LTC2401/LTC2402 can be
configured for better than 110dB rejection at 50Hz or
60Hz

2%, or can be driven by an external oscillator for

a user defined rejection frequency in the range 1Hz to
120Hz. The internal oscillator requires no external fre-
quency setting components.

These converters accept an external reference voltage
from 0.1V to V

. With an extended input conversion

range of 12.5% V

REF

to 112.5% V

REF

= FS

SET

), the LTC2401/LTC2402 smoothly resolve the off-

set and overrange problems of preceding sensors or
signal conditioning circuits.

The LTC2401/LTC2402 communicate through a 2- or
3-wire digital interface that is compatible with SPI and
MICROWIRE

protocols.

24-Bit ADCs in Tiny MSOP-10 Packages

4ppm INL, No Missing Codes

4ppm Full-Scale Error

0.5ppm Offset

0.6ppm Noise

Single Conversion Settling Time for
Multiplexed Applications

1- or 2-Channel Inputs

Automatic Channel Selection (Ping-Pong) (LTC2402)

Zero Scale and Full Scale Set for Reference
and Ground Sensing

Internal Oscillator--No External Components Required

110dB Min, 50Hz/60Hz Notch Filter

Reference Input Voltage: 0.1V to V

Live Zero--Extended Input Range Accommodates
12.5% Overrange and Underrange

Single Supply 2.7V to 5.5V Operation

Low Supply Current (200

A) and Auto Shutdown

ANALOG INPUT RANGE

SET

0.12V

REF

SET

+ 0.12V

REF

= FS

SET

)

SET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

SET

+ 0.1V TO V

0V TO FS

SET

100mV

CH0

= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION

3-WIRE
SPI INTERFACE

2.7V TO 5.5V

LTC2402

24012 TA01

SET

SCK

CH0

SDO

CH1

GND

LTC2402

3-WIRE
SPI INTERFACE

INTERNAL OSCILLATOR
60Hz REJECTION

2.7V TO 5.5V

24012TA02

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

LTC2401/LTC2402

ORDER PART NUMBER

Consult factory for Military grade parts.

(Notes 1, 2)

Supply Voltage (V

) to GND ....................... 0.3V to 7V

Analog Input Voltage to GND ....... 0.3V to (V

+ 0.3V)

Reference Input Voltage to GND .. 0.3V to (V

+ 0.3V)

Digital Input Voltage to GND ........ 0.3V to (V

+ 0.3V)

Digital Output Voltage to GND ..... 0.3V to (V

+ 0.3V)

JMAX

= 125

= 130

C/W

LTC2401CMS
LTC2401IMS

ABSOLUTE

AXI

RATINGS

PACKAGE/ORDER I

FOR

ATIO

1
2
3
4
5

SET

CH1
CH0

SET

10
9
8
7
6

SCK
SDO
CS
GND

TOP VIEW

MS10 PACKAGE

10-LEAD PLASTIC MSOP

Operating Temperature Range

LTC2401/LTC2402C ................................ 0

C to 70

LTC2401/LTC2402I ............................ 40

C to 85

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

ORDER PART NUMBER

MS10 PART MARKING

LTC2402CMS
LTC2402IMS

LTMD

LTME

MS10 PART MARKING

LTMB
LTMC

JMAX

= 125

= 130

C/W

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Resolution

Bits

No Missing Codes Resolution

0.1V

SET

, ZS

SET

= 0V (Note 5)

Bits

Integral Nonlinearity

SET

= 2.5V, ZS

SET

= 0V (Note 6)

ppm of V

REF

SET

= 5V, ZS

SET

= 0V (Note 6)

ppm of V

REF

Offset Error

2.5V

SET

, ZS

SET

= 0V

0.5

ppm of V

REF

Offset Error Drift

2.5V

SET

, ZS

SET

= 0V

0.01

ppm of V

REF

Full-Scale Error

2.5V

SET

, ZS

SET

= 0V

ppm of V

REF

Full-Scale Error Drift

2.5V

SET

, ZS

SET

= 0V

0.04

ppm of V

REF

Total Unadjusted Error

SET

= 2.5V, ZS

SET

= 0V

ppm of V

REF

SET

= 5V, ZS

SET

= 0V

ppm of V

REF

Output Noise

= 0V (Note 13)

RMS

Normal Mode Rejection 60Hz

(Note 7)

110

130

Normal Mode Rejection 50Hz

(Note 8)

110

130

Power Supply Rejection, DC

SET

= 2.5V, ZS

SET

= 0V, V

= 0V

100

Power Supply Rejection, 60Hz

SET

= 2.5V, ZS

SET

= 0V, V

= 0V, (Notes 7, 15)

110

Power Supply Rejection, 50Hz

SET

= 2.5V, ZS

SET

= 0V, V

= 0V, (Notes 8, 15)

110

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

REF

= FS

SET

 ZS

SET

. (Notes 3, 4)

VERTER CHARACTERISTICS

1
2
3
4
5

SET

10
9
8
7
6

TOP VIEW

MS10 PACKAGE

10-LEAD PLASTIC MSOP

SCK
SDO
CS
GND

LTC2401/LTC2402

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

High Level Input Voltage

2.7V

5.5V

2.5

CS, F

2.7V

3.3V

2.0

Low Level Input Voltage

4.5V

5.5V

0.8

CS, F

2.7V

5.5V

0.6

High Level Input Voltage

2.7V

5.5V (Note 9)

2.5

SCK

2.7V

3.3V (Note 9)

2.0

Low Level Input Voltage

4.5V

5.5V (Note 9)

0.8

SCK

2.7V

5.5V (Note 9)

0.6

Digital Input Current

CS, F

Digital Input Current

(Note 9)

SCK

Digital Input Capacitance

CS, F

Digital Input Capacitance

(Note 9)

SCK

High Level Output Voltage

= 800

0.5

SDO

Low Level Output Voltage

= 1.6mA

0.4

SDO

High Level Output Voltage

= 800

A (Note 10)

0.5

SCK

Low Level Output Voltage

= 1.6mA (Note 10)

0.4

SCK

High-Z Output Leakage

SDO

DIGITAL I PUTS A D DIGITAL OUTPUTS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

2.7

5.5

Supply Current

Conversion Mode

CS = 0V (Note 12)

200

300

Sleep Mode

CS = V

(Note 12)

POWER REQUIRE E TS

The

denotes specifications which apply over the full

operating temperature range, otherwise specifications are at T

= 25

C. (Note 3)

The

denotes specifications which apply over the full operating temperature range,

otherwise specifications are at T

= 25

C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Voltage Range

(Note 14)

SET

0.12V

REF

SET

+ 0.12V

REF

SET

Full-Scale Set Range

0.1 + ZS

SET

Zero-Scale Set Range

SET

0.1

S(IN)

Input Sampling Capacitance

S(REF)

Reference Sampling Capacitance

IN(LEAK)

Input Leakage Current

CS = V

REF(LEAK)

Reference Leakage Current

REF

= 2.5V, CS = V

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

REF

= FS

SET

 ZS

SET

. (Note 3)

A ALOG I PUT A D REFERE CE

LTC2401/LTC2402

The

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T

= 25

C. (Note 3)

EOSC

External Oscillator Frequency Range

2.56

307.2

kHz

HEO

External Oscillator High Period

0.5

390

LEO

External Oscillator Low Period

0.5

390

CONV

Conversion Time

= 0V

130.86

133.53

136.20

= V

157.03

160.23

163.44

External Oscillator (Note 11)

20510/f

EOSC

(in kHz)

ISCK

Internal SCK Frequency

Internal Oscillator (Note 10)

19.2

kHz

External Oscillator (Notes 10, 11)

EOSC

kHz

ISCK

Internal SCK Duty Cycle

(Note 10)

ESCK

External SCK Frequency Range

(Note 9)

2000

kHz

LESCK

External SCK Low Period

(Note 9)

250

HESCK

External SCK High Period

(Note 9)

250

DOUT_ISCK

Internal SCK 32-Bit Data Output Time

Internal Oscillator (Notes 10, 12)

1.64

1.67

1.70

External Oscillator (Notes 10, 11)

256/f

EOSC

(in kHz)

DOUT_ESCK

External SCK 32-Bit Data Output Time

(Note 9)

32/f

ESCK

(in kHz)

to SDO Low Z

150

to SDO High Z

150

to SCK

(Note 10)

150

to SCK

(Note 9)

KQMAX

SCK

to SDO Valid

200

KQMIN

SDO Hold After SCK

(Note 5)

SCK Set-Up Before CS

SCK Hold After CS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 3: V

= 2.7 to 5.5V unless otherwise specified. Input source

resistance = 0

Note 4: Internal Conversion Clock source with the F

pin tied

to GND or to V

or to external conversion clock source with

EOSC

= 153600Hz unless otherwise specified.

Note 5: Guaranteed by design, not subject to test.

Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.

Note 7: F

= 0V (internal oscillator) or f

EOSC

= 153600Hz

(external oscillator).

Note 8: F

= V

(internal oscillator) or f

EOSC

= 128000Hz

(external oscillator).

Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f

ESCK

and is expressed in kHz.

Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation, the
SCK pin has a total equivalent load capacitance C

LOAD

= 20pF.

Note 11: The external oscillator is connected to the F

pin. The external

oscillator frequency, f

EOSC

, is expressed in kHz.

Note 12: The converter uses the internal oscillator.
F

= 0V or F

= V

Note 13: The output noise includes the contribution of the internal
calibration operations.

Note 14: V

REF

= FS

SET

. The minimum input voltage is limited

to 0.3V and the maximum to V

+ 0.3V.

Note 15: V

(DC) = 4.1V, V

(AC) = 2.8V

P-P

TI I G CHARACTERISTICS

LTC2401/LTC2402

TYPICAL PERFOR A CE CHARACTERISTICS

Total Unadjusted Error (3V Supply)

INPUT VOLTAGE (V)

ERROR (ppm)

2.0

24012 G01

0.5

1.0

1.5

2.5

= 3V

REF

= 2.5V

= 55

C, 45

C, 25

C, 90

125

INPUT VOLTAGE (V)

ERROR (ppm)

2.0

24012 G02

0.5

1.0

1.5

3.0

2.5

= 3V

REF

= 2.5V

= 55

C, 45

C, 25

C, 90

125

INPUT VOLTAGE (V)

0.3

ERROR (ppm)

0.25

0.2

0.15

0.1

24012 G03

0.05

= 25

= 45

= 55

= 90

= 125

= 3V

REF

= 2.5V

INL (3V Supply)

Negative Extended Input Range
Total Unadjusted Error (3V Supply)

Positive Extended Input Range
Total Unadjusted Error (3V Supply)

Total Unadjusted Error (5V Supply)

INPUT VOLTAGE (V)

2.5

ERROR (ppm)

2.55

2.6

2.65

2.7

24012 G04

2.75

2.8

= 3V

REF

= 2.5V

= 55

C, 45

C, 25

C, 90

C, 125

INPUT VOLTAGE (V)

ERROR (ppm)

24012 G05

= 5V

REF

= 5V

= 55

C, 45

C, 25

C, 90

C, 125

INL (5V Supply)

INPUT VOLTAGE (V)

ERROR (ppm)

24012 G06

2.5

0.5

1.5

4.5

3.5

= 5V

REF

= 5V

= 55

C, 45

C, 25

C, 90

C, 125

Negative Extended Input Range
Total Unadjusted Error (5V Supply)

Offset Error vs Reference Voltage

INPUT VOLTAGE (V)

0.3

ERROR (ppm)

0.25

0.2

0.15

0.1

24012 G07

0.05

= 25

= 45

= 55

= 5V

REF

= 5V

= 90

= 125

Positive Extended Input Range
Total Unadjusted Error (5V Supply)

INPUT VOLTAGE (V)

5.0

ERROR (ppm)

5.05

5.1

5.15

5.2

24012 G08

5.25

5.3

= 25

= 45

= 55

= 90

= 125

= 5V

REF

= 5V

REFERENCE VOLTAGE (V)

OFFSET ERROR (ppm)

24012 G09

= 5V

= 25

LTC2401/LTC2402

TYPICAL PERFOR A CE CHARACTERISTICS

RMS Noise vs Reference Voltage

Offset Error vs V

RMS Noise vs V

REFERENCE VOLTAGE (V)

RMS NOISE (ppm OF V

REF

)

24012 G10

= 5V

= 25

2.7

5.0

OFFSET ERROR (ppm)

2.5

5.0

3.2

3.7

4.2

4.7

24012 G11

5.2

REF

= 2.5V

= 25

2.7

RMS NOISE (ppm)

2.5

5.0

3.2

3.7

4.2

4.7

24012 G12

5.2

REF

= 2.5V

= 25

Noise Histogram

RMS Noise vs Code Out

Offset Error vs Temperature

OUTPUT CODE (ppm)

250

300

350

24012 G13

200

150

100

NUMBER OF READINGS

= 5V

REF

= 5V

= 0V

CODE OUT (HEX)

0.3

RMS NOISE (ppm)

0.50

0.75

5.3

24012 G14

0.25

2.5

1.00

= 5V

REF

= 5V

= 0.3V TO 5.3V

= 25

TEMPERATURE (

5.0

OFFSET ERROR (ppm)

2.5

5.0

24012 G15

120

= 5V

REF

= 5V

= 0V

Full-Scale Error vs Temperature

Full-Scale Error
vs Reference Voltage

Full-Scale Error vs V

TEMPERATURE (

5.0

FULL-SCALE ERROR (ppm)

2.5

5.0

24012 G16

120

= 5V

REF

= 5V

REFERENCE VOLTAGE (V)

FULL-SCALE ERROR (ppm)

24012 G17

= 5V

= V

REF

2.7

FULL-SCALE ERROR (ppm)

3.2

3.7

4.2

4.7

24012 G18

5.2

REF

= 2.5V

= 25

LTC2401/LTC2402

TYPICAL PERFOR A CE CHARACTERISTICS

Conversion Current
vs Temperature

Sleep Current vs Temperature

Rejection vs Frequency at V

TEMPERATURE (

SUPPLY CURRENT (

220

24012 G19

190

170

160

150

230

210

200

180

120

= 5.5V

= 4.1V

= 2.7V

TEMPERATURE (

SUPPLY CURRENT (

24012 G20

120

= 2.7V

= 5V

FREQUENCY AT V

(Hz)

120

REJECTION (dB)

105

100

10k

24012 G21

= 4.1V

= 0V

= 25

= 0

Rejection vs Frequency at V

FREQUENCY AT V

(Hz)

REJECTION (dB)

200

24012 G22

100

120

100

150

250

= 4.1V

= 0V

= 25

= 0

Rejection vs Frequency at V

FREQUENCY AT V

(Hz)

15200

120

REJECTION (dB)

105

15250 15300 15350 15400

24012 G23

15450 15500

= 4.1V

= 0V

= 25

= 0

FREQUENCY AT V

(Hz)

120

REJECTION (dB)

100

150

200

24012 G24

250

= 5V

REF

= 5V

= 2.5V

= 0

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

REJECTION (dB)

24012 G25

100

110

120

130

140

FREQUENCY AT V

(Hz)

15100

120

REJECTION (dB)

100

15200

15300

15400

15500

24012 G26

= 5V

REF

= 5V

= 2.5V

= 0

SAMPLE RATE = 15.36kHz

INPUT FREQUENCY

24012 G27

100

120

140

REJECTION (dB)

LTC2401/LTC2402

TYPICAL PERFOR A CE CHARACTERISTICS

CTIO

(Pin 1): Positive Supply Voltage. Bypass to GND

(Pin 6) with a 10

F tantalum capacitor in parallel with

0.1

F ceramic capacitor as close to the part as possible.

SET

(Pin 2): Full-Scale Set Input. This pin defines the

full-scale input value. When V

= FS

SET

, the ADC outputs

full scale (FFFFF

). The total reference voltage is

SET

CH0, CH1 (Pins 4, 3): Analog Input Channels. The input
voltage range is 0.125 · V

REF

to 1.125 · V

REF

. For

REF

> 2.5V, the input voltage range may be limited by the

absolute maximum rating of 0.3V to V

+ 0.3V. Conver-

sions are performed alternately between CH0
and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on
the LTC2401.

SET

(Pin 5): Zero-Scale Set Input. This pin defines the

zero-scale input value. When V

= ZS

SET

, the ADC

outputs zero scale (00000

GND (Pin 6): Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should

be connected directly to a ground plane through a mini-
mum length trace or it should be the single-point-ground
in a single-point grounding system.

CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.

SDO (Pin 8): Three-State Digital Output. During the data
output period, this pin is used for serial data output. When
the chip select CS is HIGH (CS = V

), the SDO pin is in a

high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status out-
put. The conversion status can be observed by pulling CS
LOW.

INL vs Output Rate

OUTPUT RATE (Hz)

INL (BITS)

24012 G28

100

= 5V

REF

= 5V

= EXTERNAL

= 55

= 25

= 90

Resolution vs Output Rate

OUTPUT RATE (Hz)

RESOLUTION (BITS)

24012 G29

100

= 5V

REF

= 5V

= EXTERNAL

= 55

= 25

= 90

LTC2401/LTC2402

CTIO

SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In the External Serial Clock Operation mode, SCK
is used as digital input for the external serial interface. An
internal pull-up current source is automatically activated
in Internal Serial Clock Operation mode. The Serial Clock
mode is determined by the level applied to SCK at power
up and the falling edge of CS.

(Pin 10): Frequency Control Pin. Digital input that

controls the ADC's notch frequencies and conversion
time. When the F

pin is connected to V

= V

), the

converter uses its internal oscillator and the digital filter's
first null is located at 50Hz. When the F

pin is connected

to GND (F

= 0V), the converter uses its internal oscillator

and the digital filter's first null is located at 60Hz. When F

is driven by an external clock signal with a frequency f

EOSC

the converter uses this signal as its clock and the digital
filter first null is located at a frequency f

EOSC

/2560.

CTIO

AL BLOCK DIAGRA

TEST CIRCUITS

3.4k

SDO

24012 TC01

Hi-Z TO V

TO V

TO Hi-Z

LOAD

= 20pF

3.4k

SDO

24012 TC02

Hi-Z TO V

TO V

TO Hi-Z

LOAD

= 20pF

AUTOCALIBRATION

AND CONTROL

DAC

DECIMATING FIR

INTERNAL

OSCILLATOR

SERIAL

INTERFACE

ADC

GND

SDO

SCK

REF

(INT/EXT)

24012 FD

LTC2401/LTC2402

APPLICATIO S I FOR ATIO

Converter Operation Cycle

The LTC2401/LTC2402 are low power, delta-sigma ana-
log-to-digital converters with an easy to use 3-wire serial
interface. Their operation is simple and made up of three
states. The converter operating cycle begins with the
conversion, followed by a low power sleep state and
concluded with the data output (see Figure 1). The 3-wire
interface consists of serial data output (SDO), a serial
clock (SCK) and a chip select (CS).

Initially, the LTC2401/LTC2402 perform a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, power consumption
is reduced by an order of magnitude. The part remains in
the sleep state as long as CS is logic HIGH. The conversion
result is held indefinitely in a static shift register while the
converter is in the sleep state.

Once CS is pulled low, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK, see Figure 3.
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion cycle and the
cycle repeats.

Through timing control of the CS and SCK pins, the
LTC2401/LTC2402 offer several flexible modes of opera-
tion (internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.

Conversion Clock

A major advantage delta-sigma converters offer over
conventional type converters is an on-chip digital filter
(commonly known as Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typi-
cally designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. In order to reject these frequencies
in excess of 110dB, a highly accurate conversion clock is
required. The LTC2401/LTC2402 incorporate an on-chip
highly accurate oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2401/
LTC2402 reject line frequencies (50Hz or 60Hz

2%) a

minimum of 110dB.

Ease of Use

The LTC2401/LTC2402 data output has no latency, filter
settling or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
an analog input voltage is easy.

The LTC2401/LTC2402 perform offset and full-scale cali-
brations every conversion cycle. This calibration is trans-
parent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage change and temperature
drift.

Power-Up Sequence

The LTC2401/LTC2402 automatically enter an internal
reset state when the power supply voltage V

drops

below approximately 2.2V. This feature guarantees the

CONVERT

SLEEP

DATA OUTPUT

24012 F01

1 CS AND

SCK

Figure 1. LTC2401/LTC2402 State Transition Diagram

LTC2401/LTC2402

integrity of the conversion result and of the serial interface
mode selection which is performed at the initial power-up.
(See the 2-wire I/O sections in the Serial Interface Timing
Modes section.)

When the V

voltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)
signal with duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2401/LTC2402 start a normal conversion
cycle and follows the normal succession of states de-
scribed above. The first conversion result following POR
is accurate within the specifications of the device.

Reference Voltage Range

The LTC2401/LTC2402 can accept a reference voltage
(V

REF

= FS

SET

) from 0V to V

. The converter

output noise is determined by the thermal noise of the
front-end circuits, and as such, its value in microvolts is
nearly constant with reference voltage. A decrease in
reference voltage will not significantly improve the
converter's effective resolution. On the other hand, a
reduced reference voltage will improve the overall con-
verter INL performance. The recommended range for the
LTC2401/LTC2402 voltage reference is 100mV to V

Input Voltage Range

The converter is able to accommodate system level
offset and gain errors as well as system level overrange
situations due to its extended input range, see Figure 2.
The LTC2401/LTC2402 convert input signals within the
extended input range of 0.125 · V

REF

to 1.125 · V

REF

= FS

SET

For large values of V

REF

= FS

SET

), this range

is limited by the absolute maximum voltage range of
0.3V to (V

+ 0.3V). Beyond this range, the input ESD

protection devices begin to turn on and the errors due to
the input leakage current increase rapidly.

Input signals applied to V

may extend below ground by

300mV and above V

by 300mV. In order to limit any

fault current, a resistor of up to 5k may be added in series
with the V

pin without affecting the performance of the

device. In the physical layout, it is important to maintain

APPLICATIO S I FOR ATIO

the parasitic capacitance of the connection between this
series resistance and the V

pin as low as possible;

therefore, the resistor should be located as close as
practical to the V

pin. The effect of the series resistance

on the converter accuracy can be evaluated from the
curves presented in the Analog Input/Reference Current
section. In addition, a series resistor will introduce a
temperature dependent offset error due to the input leak-
age current. A 1nA input leakage current will develop a
1ppm offset error on a 5k resistor if V

REF

= 5V. This error

has a very strong temperature dependency.

Output Data Format

The LTC2401/LTC2402 serial output data stream is 32 bits
long. The first 4 bits represent status information indicat-
ing the sign, selected channel, input range and conversion
state. The next 24 bits are the conversion result, MSB first.
The remaining 4 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.

Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW when
the conversion is complete.

Bit 30 (second output bit) for the LTC2402, this bit is LOW
if the last conversion was performed on CH0 and HIGH for
CH1. This bit is always low for the LTC2401.

24012 F02

+ 0.3V

SET

+ 0.12V

REF

SET

0.3V

REF

= FS

SET

)

SET

0.12V

REF

SET

NORMAL

INPUT

RANGE

EXTENDED

INPUT

RANGE

ABSOLUTE
MAXIMUM

INPUT

RANGE

Figure 2. LTC2401/LTC2402 Input Range

LTC2401/LTC2402

APPLICATIO S I FOR ATIO

Figure 3. Output Data Timing

Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V

is >0, this bit is HIGH. If V

is <0, this

bit is LOW. The sign bit changes state during the zero code.

Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0

REF

, this bit is LOW. If the input is outside the

normal input range, V

> V

REF

or V

< 0, this bit is HIGH.

The function of these bits is summarized in Table 1.

Table 1. LTC2401/LTC2402 Status Bits

Bit 31

Bit 30

Bit 29

Bit 28

Input Range

EOC

CH0/CH1

SIG

EXR

> V

REF

0/1

0 < V

REF

0/1

= 0

0/1

1/0

< 0

0/1

Bit 27 (fifth output bit) is the most significant bit (MSB).

Bits 27-4 are the 24-bit conversion result MSB first.

Bit 4 is the least significant bit (LSB).

Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.

Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.

In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from

HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.

As long as the voltage on the V

pin is maintained within

the 0.3V to (V

+ 0.3V) absolute maximum operating

range, a conversion result is generated for any input value
from 0.125 · V

REF

to 1.125 · V

REF

For input voltages

greater than 1.125 · V

REF

, the conversion result is clamped

to the value corresponding to 1.125 · V

REF

. For input

voltages below 0.125 · V

REF

, the conversion result is

clamped to the value corresponding to 0.125 · V

REF

Frequency Rejection Selection (F

Pin Connection)

The LTC2401/LTC2402 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz

2% or 60Hz

2%. For

60Hz rejection, F

(Pin 10) should be connected to GND

(Pin 6) while for 50Hz rejection the F

pin should be

connected to V

(Pin 1).

The selection of 50Hz or 60Hz rejection can also be made
by driving F

to an appropriate logic level. A selection

change during the sleep or data output states will not

MSB

EXT

SIG

CH0/CH1

BIT 0

BIT 27

BIT 4

LSB

BIT 28

BIT 29

BIT 30

SDO

SCK

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

24012 F03

Hi-Z

LTC2401/LTC2402

APPLICATIO S I FOR ATIO

Table 2. LTC2401/LTC2402 Output Data Format

Bit 31

Bit 30

Bit 29

Bit 28

Bit 27

Bit 26

Bit 25

Bit 24

Bit 23

...

Bit 4

Bit 3-0

Input Voltage

EOC

CH SELECT

SIG

EXR

MSB

LSB

SUB LSBs*

> 9/8 · V

REF

CH0/CH1

...

9/8 · V

REF

CH0/CH1

...

REF

+ 1LSB

CH0/CH1

...

REF

CH0/CH1

...

3/4V

REF

+ 1LSB

CH0/CH1

...

3/4V

REF

CH0/CH1

...

1/2V

REF

+ 1LSB

CH0/CH1

...

1/2V

REF

CH0/CH1

...

1/4V

REF

+ 1LSB

CH0/CH1

...

1/4V

REF

CH0/CH1

...

CH0/CH1

1/0**

...

1LSB

CH0/CH1

...

1/8 · V

REF

CH0/CH1

...

< 1/8 · V

REF

CH0/CH1

...

*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.

disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.

When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2401/
LTC2402 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the F

pin and turns off the internal

oscillator. The frequency f

EOSC

of the external signal must

be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods t

HEO

and t

LEO

are observed.

While operating with an external conversion clock of a
frequency f

EOSC

, the LTC2401/LTC2402 provide better

than 110dB normal mode rejection in a frequency range
f

EOSC

/2560

4% and its harmonics. The normal mode

rejection as a function of the input frequency deviation
from f

EOSC

/2560 is shown in Figure 4.

Whenever an external clock is not present at the F

pin, the

converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2401/
LTC2402 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state or
during the data output state while the converter uses an

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

REJECTION (dB)

24012 F04

100

110

120

130

140

Figure 4. LTC2401/LTC2402 Normal Mode Rejection When
Using an External Oscillator of Frequency f

EOSC

LTC2401/LTC2402

external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conver-
sions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.

Table 3 summarizes the duration of each state as a
function of F

SERIAL INTERFACE

The LTC2401/LTC2402 transmit the conversion results
and receives the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 9) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2401/LTC2402 create their own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as

input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or float-
ing at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 8), drives the serial
data during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.

When CS (Pin 7) is HIGH, the SDO driver is switched to a
high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = 0.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 7), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.

Table 3. LTC2401/LTC2402 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

= LOW

133ms

(60Hz Rejection)

= HIGH

160ms

(50Hz Rejection)

External Oscillator

= External Oscillator

20510/f

EOSC

with Frequency f

EOSC

kHz

EOSC

/2560 Rejection)

SLEEP

As Long As CS = HIGH Until CS = 0 and SCK

DATA OUTPUT

Internal Serial Clock

= LOW/HIGH

As Long As CS = LOW But Not Longer Than 1.67ms

(Internal Oscillator)

(32 SCK cycles)

= External Oscillator with

As Long As CS = LOW But Not Longer Than 256/f

EOSC

Frequency f

EOSC

kHz

(32 SCK cycles)

External Serial Clock with

As Long As CS = LOW But Not Longer Than 32/f

SCK

Frequency f

SCK

kHz

(32 SCK cycles)

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2401/LTC2402 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with CS = 0).

Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by F

. Tying a

capacitor to CS will reduce the output rate and power
dissipation by a factor proportional to the capacitor's
value, see Figures 12 to 14.

SERIAL INTERFACE TIMING MODES

The LTC2401/LTC2402's 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exter-
nal serial clock, 2- or 3-wire I/O, single cycle conversion
and autostart. The following sections describe each of
these serial interface timing modes in detail. In all these
cases, the converter can use the internal oscillator (F

LOW or F

= HIGH) or an external oscillator connected to

the F

pin. Refer to Table 4 for a summary.

External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.

The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin. EOC
= 1 while a conversion is in progress and EOC = 0 if the
device is in the sleep state. Independent of CS, the device
automatically enters the low power sleep state once the
conversion is complete.

When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift register.
The device remains in the sleep state until the first rising
edge of SCK is seen while CS is LOW. Data is shifted out
the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.

Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
32nd falling edge of SCK, see Figure 6. On the rising edge

Table 4. LTC2401/LTC2402 Interface Timing Modes

Conversion

Data

Connection

SCK

Cycle

Output

and

Configuration

Source

Control

Waveforms

External SCK, Single Cycle Conversion

External

CS and SCK

Figures 5, 6

External SCK, 2-Wire I/O

External

SCK

Figure 7

Internal SCK, Single Cycle Conversion

Internal

Figures 8, 9

Internal SCK, 2-Wire I/O, Continuous Conversion

Internal

Continuous

Internal

Figure 10

Internal SCK, Autostart Conversion

Internal

EXT

Internal

Figure 11

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

Figure 5. External Serial Clock, Single Cycle Operation

APPLICATIO S I FOR ATIO

EOC

BIT 31

SDO

SCK

(EXTERNAL)

TEST EOC

MSB

SUB LSB

EXR

CH0/CH1

BIT 0

LSB

BIT 4

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

24012 F05

CONVERSION

Hi-Z

TEST EOC

SET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

SET

+ 0.1V TO V

0V TO FS

SET

100mV

CH0

= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION

2.7V TO 5.5V

LTC2402

3-WIRE
SERIAL I/O

ANALOG INPUT RANGE

SET

0.12V

REF

SET

+ 0.12V

REF

= FS

SET

)

SDO

SCK

(EXTERNAL)

DATA OUTPUT

CONVERSION

SLEEP

TEST EOC

DATA OUTPUT

Hi-Z

CONVERSION

24012 F06

MSB

EXR

SIG

CH0/CH1

BIT 8

BIT 27

BIT 9

BIT 28

BIT 29

BIT 30

EOC

BIT 31

BIT 0

EOC

Hi-Z

TEST EOC

SET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

SET

+ 0.1V TO V

0V TO FS

SET

100mV

CH0

= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION

2.7V TO 5.5V

LTC2402

3-WIRE
SERIAL I/O

ANALOG INPUT RANGE

SET

0.12V

REF

SET

+ 0.12V

REF

= FS

SET

)

Figure 6. External Serial Clock, Reduced Data Output Length

LTC2401/LTC2402

of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for
systems not requiring all 32 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of a
conversion.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground (Pin 6), simplifying the
user interface or isolation barrier.

The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V

exceeds 2.2V. The level

applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. EOC may be used as an inter-
rupt to an external controller indicating the conversion
result is ready. EOC = 1 while the conversion is in

progress and EOC = 0 once the conversion enters the low
power sleep state. On the falling edge of EOC, the conver-
sion result is loaded into an internal static shift register.
The device remains in the sleep state until the first rising
edge of SCK. Data is shifted out the SDO pin on each
falling edge of SCK enabling external circuitry to latch
data on the rising edge of SCK. EOC can be latched on the
first rising edge of SCK. On the 32nd falling edge of SCK,
SDO goes HIGH (EOC = 1) indicating a new conversion
has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.

Figure 7. External Serial Clock, CS = 0 Operation

APPLICATIO S I FOR ATIO

EOC

BIT 31

SDO

SCK

(EXTERNAL)

MSB

EXR

SIG

CH0/CH1

BIT 0

LSB

BIT 4

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

24012 F07

CONVERSION

SET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

SET

+ 0.1V TO V

0V TO FS

SET

100mV

CH0

= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION

2-WIRE SERIAL I/O

2.7V TO 5.5V

LTC2402

ANALOG INPUT RANGE

SET

0.12V

REF

SET

+ 0.12V

REF

= FS

SET

)

LTC2401/LTC2402

The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.

When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t

EOCtest

after the falling edge of CS

(if EOC = 0) or t

EOCtest

after EOC goes LOW (if CS is LOW

during the falling edge of EOC). The value of t

EOCtest

is 23

if the device is using its internal oscillator (F

= logic LOW

or HIGH). If F

is driven by an external oscillator of

frequency f

EOSC

, then t

EOCtest

is 3.6/f

EOSC

. If CS is pulled

HIGH before time t

EOCtest

, the device remains in the sleep

state. The conversion result is held in the internal static
shift register.

If CS remains LOW longer than t

EOCtest

, the first rising

edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.

Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the

APPLICATIO S I FOR ATIO

SDO

SCK

(INTERNAL)

MSB

EXR

SIG

CH0/CH1

BIT 0

LSB

BIT 4

TEST EOC

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

2400 F08

EOCtest

10k

Hi-Z

TEST EOC

SET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

SET

+ 0.1V TO V

0V TO FS

SET

100mV

CH0

= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION

2.7V TO 5.5V

LTC2402

ANALOG INPUT RANGE

SET

0.12V

REF

SET

+ 0.12V

REF

= FS

SET

)

Figure 8. Internal Serial Clock, Single Cycle Operation

LTC2401/LTC2402

internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is
LOW.

Whenever SCK is LOW, the LTC2401/LTC2402's internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
mode. However, certain applications may require an ex-
ternal driver on SCK. If this driver goes Hi-Z after output-
ting a LOW signal, the LTC2401/LTC2402's internal pull-
up remains disabled. Hence, SCK remains LOW. On the
next falling edge of CS, the device is switched to the
external SCK timing mode. By adding an external 10k pull-
up resistor to SCK, this pin goes HIGH once the external
driver goes Hi-Z. On the next CS falling edge, the device
will remain in the internal SCK timing mode.

A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as t

EOCtest

), the internal pull-up is activated.

For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 2-Wire I/O,
Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground (Pin 6),
simplifying the user interface or isolation barrier.

SDO

SCK

(INTERNAL)

> t

EOCtest

MSB

EXR

SIG

BIT 8

TEST EOC

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

EOC

BIT 0

SLEEP

DATA OUTPUT

Hi-Z

DATA OUTPUT

CONVERSION

SLEEP

24012 F09

EOCtest

10k

TEST EOC

CH0/CH1

SET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

SET

+ 0.1V TO V

0V TO FS

SET

100mV

CH0

= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION

2.7V TO 5.5V

LTC2402

ANALOG INPUT RANGE

SET

0.12V

REF

SET

+ 0.12V

REF

= FS

SET

)

Figure 9. Internal Serial Clock, Reduced Data Output Length

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V

exceeds 2.2V. An internal

weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).

During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 32nd

rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.

Internal Serial Clock, Autostart Conversion

This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.

While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
capacitor tied to CS, see Figure 11. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 12 and 13. Once the
voltage at CS falls below an internal threshold (

1.4V), the

device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be

SDO

SCK

(INTERNAL)

LSB

MSB

EXR

SIG

BIT 4

BIT 0

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

24012 F10

CH0/CH1

SET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

SET

+ 0.1V TO V

0V TO FS

SET

100mV

CH0

= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION

2.7V TO 5.5V

LTC2402

10k

ANALOG INPUT RANGE

SET

0.12V

REF

SET

+ 0.12V

REF

= FS

SET

)

Figure 10. Internal Serial Clock, Continuous Operation

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

APPLICATIO S I FOR ATIO

SDO

Hi-Z

SCK

(INTERNAL)

GND

24012 F11

BIT 0

SIG

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

EOC

BIT 31

CH0/CH1

SET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

SET

+ 0.1V TO V

0V TO FS

SET

100mV

CH0

= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION

EXT

2.7V TO 5.5V

LTC2402

10k

ANALOG INPUT RANGE

SET

0.12V

REF

SET

+ 0.12V

REF

= FS

SET

)

Figure 11. Internal Serial Clock, Autostart Operation

CAPACITANCE ON CS (pF)

1000

10000

24012 F12

100

100000

SAMPLE

(SEC)

= 5V

= 3V

CAPACITANCE ON CS (pF)

SAMPLE RATE (Hz)

1000

100000

24012 F13

100

10000

= 5V

= 3V

Figure 12. CS Capacitance vs t

SAMPLE

Figure 13. CS Capacitance vs Output Rate

LTC2401/LTC2402

used to shift the conversion result into external circuitry.
After the 32nd rising edge, CS is pulled HIGH and a new
conversion is immediately started. This is useful in appli-
cations requiring periodic monitoring and ultralow power.
Figure 14 shows the average supply current as a function
of capacitance on CS.

It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the con-
verter power dissipation in the sleep state. In the autostart
mode the analog voltage on the CS pin cannot be observed
without disturbing the converter operation using a regular
oscilloscope probe. When using this configuration, it is
important to minimize the external leakage current at the
CS pin by using a low leakage external capacitor and
properly cleaning the PCB surface.

The internal serial clock mode is selected every time the
voltage on the CS pin crosses an internal threshold volt-
age. An internal weak pull-up at the SCK pin is active while
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.

as 100

s. However, some considerations are required to

take advantage of exceptional accuracy and low supply
current.

The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.

In order to preserve the LTC2401/LTC2402's accuracy, it
is very important to minimize the ground path impedance
which may appear in series with the input and/or reference
signal and to reduce the current which may flow through
this path. The GND pin should be connected to a low
resistance ground plane through a minimum length trace.
The use of multiple via holes is recommended to further
reduce the connection resistance.

In an alternative configuration, the GND pin of the converter
can be the single-point-ground in a single point grounding
system. The input signal ground, the reference signal
ground, the digital drivers ground (usually the digital
ground) and the power supply ground (the analog ground)
should be connected in a star configuration with the com-
mon point located as close to the GND pin as possible.

The power supply current during the conversion state
should be kept to a minimum. This is achieved by restrict-
ing the number of digital signal transitions occurring
during this period.

While a digital input signal is in the range 0.5V to
(V

0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,
when any one of the digital input signals (F

, CS and SCK

in External SCK mode of operation) is within this range, the
LTC2401/LTC2402 power supply current may increase
even if the signal in question is at a valid logic level. For
micropower operation and in order to minimize the poten-
tial errors due to additional ground pin current, it is
recommended to drive all digital input signals to full CMOS
levels [V

< 0.4V and V

> (V

0.4V)].

Severe ground pin current disturbances can also occur
due to the undershoot of fast digital input signals. Under-
shoot and overshoot can occur because of the impedance
mismatch at the converter pin when the transition time of
an external control signal is less than twice the propaga-
tion delay from the driver to LTC2401/LTC2402. For

APPLICATIO S I FOR ATIO

CAPACITANCE ON CS (pF)

SUPPLY CURRENT (

RMS

)

100

150

200

250

300

100

1000

10000

24012 F14

100000

= 5V

= 3V

Figure 14. CS Capacitance vs Supply Current

DIGITAL SIGNAL LEVELS

The LTC2401/LTC2402's digital interface is easy to use.
Its digital inputs (F

, CS and SCK in External SCK mode of

operation) accept standard TTL/CMOS logic levels and the
internal hysteresis receivers can tolerate edge rates as slow

LTC2401/LTC2402

reference, on a regular FR-4 board, signal propagation
velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver gener-
ating a control signal with a minimum transition time of
1ns must be connected to the converter pin through a
trace shorter than 2.5 inches. This problem becomes
particularly difficult when shared control lines are used
and multiple reflections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.

Parallel termination near the LTC2401/LTC2402 pin will
eliminate this problem but will increase the driver power
dissipation. A series resistor between 27

and 56

placed near the driver or near the LTC2401/LTC2402 pin
will also eliminate this problem without additional power
dissipation. The actual resistor value depends upon the
trace impedance and connection topology.

Driving the Input and Reference

The analog input and reference of the typical delta-sigma
analog-to-digital converter are applied to a switched ca-
pacitor network. This network consists of capacitors
switching between the analog input (V

), ZS

SET

(Pin 5)

and FS

SET

(Pin 2). The result is small current spikes seen

at both V

and V

REF

. A simplified input equivalent circuit

is shown in Figure 15.

The key to understanding the effects of this dynamic
input current is based on a simple first order RC time
constant model. Using the internal oscillator, the

LTC2401/LTC2402's internal switched capacitor network
is clocked at 153,600Hz corresponding to a 6.5

s sam-

pling period. Fourteen time constants are required each
time a capacitor is switched in order to achieve 1ppm
settling accuracy.

Therefore, the equivalent time constant at V

and V

REF

should be less than 6.5

s/14 = 460ns in order to achieve

1ppm accuracy.

Input Current (V

)

If complete settling occurs on the input, conversion results
will be uneffected by the dynamic input current. If the
settling is incomplete, it does not degrade the linearity
performance of the device. It simply results in an offset/
full-scale shift, see Figure 16. To simplify the analysis of
input dynamic current, two separate cases are assumed:
large capacitance at V

> 0.01

F) and small capaci-

tance at V

< 0.01

F).

APPLICATIO S I FOR ATIO

SET

CH0/CH1

AVERAGE INPUT CURRENT:

= 0.25(V

0.5 · V

REF

)fC

REF(LEAK)

2.5pF (TYP)

IN(LEAK)

24012 F15

IN(LEAK)

SWITCHING FREQUENCY
f = 153.6kHz FOR INTERNAL OSCILLATOR (f

= LOGIC LOW OR HIGH)

f = f

EOSC

FOR EXTERNAL OSCILLATORS

SET

Figure 15. LTC2401/LTC2402 Equivalent Analog Input Circuit

SET

TUE

24012 F16

SET

Figure 16. Offset/Full-Scale Shift

If the total capacitance at V

(see Figure 17) is small

(< 0.01

F), relatively large external source resistances (up

to 20k for 20pF parasitic capacitance) can be tolerated
without any offset/full-scale error. Figures 18 and 19 show
a family of offset and full-scale error curves for various
small valued input capacitors (C

< 0.01

F) as a function

of input source resistance.

For large input capacitor values (C

> 0.01

F), the input

spikes are averaged by the capacitor into a DC current. The
gain shift becomes a linear function of input source

LTC2401/LTC2402

resistance independent of input capacitance, see Figures
20 and 21. The equivalent input impedance is 6.25M

This results in

400

A of input dynamic current at the

extreme values of V

= 0V and V

= V

REF

, when

REF

= 5V). This corresponds to a 0.8ppm shift in offset

and full-scale readings for every 10

of input source

resistance.

24012 F17

INTPUT

SIGNAL

SOURCE

LTC2401/

LTC2402

PAR

20pF

APPLICATIO S I FOR ATIO

Figure 17. An RC Network at V

Figure 18. Offset vs R

SOURCE

(Small C)

Figure 19. Offset vs R

SOURCE

(Large C)

In addition to the input current spikes, the input ESD
protection diodes have a temperature dependent leakage
current. This leakage current, nominally 1nA (

10nA

max), results in a fixed offset shift of 10

V for a 10k source

resistance.

The effect of input leakage current is evident for C

= 0 in

Figures 18 and 21. A leakage current of 3nA results in a
150

V (30ppm) error for a 50k source resistance. As

SOURCE

gets larger, the switched capacitor input current

begins to dominate.

Reference Current (V

REF

)

Similar to the analog input, the reference input has a
dynamic input current. This current has negligible effect

Figure 20. Full-Scale Error vs R

SOURCE

(Large C)

Figure 21. Full-Scale Error vs R

SOURCE

(Small C)

SOURCE

(

)

OFFSET ERROR (ppm)

100

10k

24012 F18

100k

= 5V

REF

= 5V

= 0V

= 25

= 100pF

= 0.01

= 1000pF

= NO CAP

SOURCE

(

)

OFFSET ERROR (ppm)

800

24012 F19

200

400

600

1000

= 22

= 10

= 1

= 0.1

= 0.01

= 0.001

= 5V

REF

= 5V

= 0V

= 25

SOURCE

(

)

FULL-SCALE ERROR (ppm)

400

800

1000

24012 F20

200

600

= 22

= 10

= 1

= 0.1

= 0.01

= 0.001

= 5V

REF

= 5V

= 25

SOURCE

(

)

FULL-SCALE (ppm)

10k

24012 F21

100

100k

= 5V

REF

= 5V

= 25

= NO CAP

= 0.01

= 1000pF

= 100pF

LTC2401/LTC2402

on the offset. However, the reference current at V

= V

REF

is similar to the input current at full-scale. For large values
of reference capacitance (C

VREF

> 0.01

F), the full-scale

error shift is 0.08ppm/

of external reference resistance

independent of the capacitance at V

REF

, see Figure 22. If

the capacitance tied to V

REF

is small (C

VREF

< 0.01

F), an

input resistance of up to 20k (20pF parasitic capacitance
at V

REF

) may be tolerated, see Figure 23.

Unlike the analog input, the integral nonlinearity of the
device can be degraded with excessive external RC time
constants tied to the reference input. If the capacitance

APPLICATIO S I FOR ATIO

Figure 22. Full-Scale Error vs R

VREF

(Large C)

Figure 23. Full-Scale Error vs R

VFEF

(Small C)

Figure 24. INL Error vs R

VREF

(Small C)

Figure 25. INL Error vs R

VREF

(Large C)

at node V

REF

is small (C

VREF

< 0.01

F), the reference input

can tolerate large external resistances without reduction
in INL, see Figure 24. If the external capacitance is large
(C

VREF

> 0.01

F), the linearity will be degraded by

0.04ppm/

independent of capacitance at V

REF

, see

Figure 25.

In addition to the dynamic reference current, the V

REF

ESD

protection diodes have a temperature dependent leakage
current. This leakage current, nominally 1nA (

10nA max),

results in a fixed full-scale shift of 10

V for a 10k source

resistance.

RESISTANCE AT V

REF

(

)

FULL-SCALE ERROR (ppm)

120

800

24012 F22

200

400

600

1000

160

= 5V

REF

= 5V

= 25

= 10

= 0.1

= 0.01

= 1

RESISTANCE AT V

REF

(

)

100

FULL-SCALE ERROR (ppm)

= 10

10k

24012 F23

100k

= 5V

REF

= 5V

= 25

= 20pF

= 1000pF

= 100pF

RESISTANCE AT V

REF

(

)

100

INL ERROR (ppm)

= 0.01

= 20pF

= 1000pF

= 100pF

= 5V

REF

= 5V

= 25

10k

24012 F24

100k

RESISTANCE AT V

REF

(

)

INL ERROR (ppm)

800

24012 F25

200

400

600

1000

= 5V

REF

= 5V

= 25

VREF

= 10

VREF

= 0.1

VREF

= 1

VREF

= 0.01

LTC2401/LTC2402

APPLICATIO S I FOR ATIO

ANTIALIASING

One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2401/LTC2402 signifi-
cantly simplify antialiasing filter requirements.

The digital filter provides very high rejection except at
integer multiples of the modulator sampling frequency
(f

), see Figure 26. The modulator sampling frequency is

256 · F

, where F

is the notch frequency (typically 50Hz

or 60Hz). The bandwidth of signals not rejected by the
digital filter is narrow (

0.2%) compared to the bandwidth

of the frequencies rejected.

As a result of the oversampling ratio (256) and the digital
filter, minimal (if any) antialias filtering is required in front
of the LTC2401/LTC2402. If passive RC components are
placed in front of the LTC2401/LTC2402, the input dy-
namic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of input dynamic current.

The modulator contained within the LTC2401/LTC2402
can handle large-signal level perturbations without satu-
rating. Signal levels up to 40% of V

REF

do not saturate the

analog modulator. These signals are limited by the input
ESD protection to 300mV below ground and 300mV above
V

Single Ended Half-Bridge Digitizer
with Reference and Ground Sensing

Sensors convert real world phenomena (temperature,
pressure, gas levels, etc.) into a voltage. Typically, this
voltage is generated by passing an excitation current
through the sensor. The wires connecting the sensor to
the ADC form parasitic resistors R

and R

. The excita-

tion current also flows through parasitic resistors R

and

, as shown in Figure 27. The voltage drop across these

parasitic resistors leads to systematic offset and full-scale
errors.

In order to eliminate the errors associated with these
parasitic resistors, the LTC2401/LTC2402 include a full-
scale set input (FS

SET

) and a zero-scale set input

(ZS

SET

). As shown in Figure 28, the FS

SET

pin acts as a zero

current full-scale sense input. Errors due to parasitic
resistance R

in series with the half-bridge sensor are

removed by the FS

SET

input to the ADC. The absolute full-

scale output of the ADC (data out = FFFFFF

HEX

) will occur

INPUT FREQUENCY

24012 F26

100

120

140

REJECTION (dB)

Figure 26. Sinc

Filter Rejection

FULL-SCALE ERROR

SENSOR

SENSOR OUTPUT

EXCITATION

OFFSET ERROR

24012 F27

LTC2401

SET

GND

SCK

SDO

SET

3-WIRE
SPI INTERFACE

24012 F03

= 0

EXCITATION

= 0

Figure 28. Half-Bridge Digitizer with
Zero-Scale and Full-Scale Sense

Figure 27. Errors Due to Excitation Currents

LTC2401/LTC2402

APPLICATIO S I FOR ATIO

at V

= V

= FS

SET

, see Figure 29. Similarly, the offset

errors due to R

are removed by the ground sense input

SET

. The absolute zero output of the ADC (data out =

000000

HEX

) occurs at V

= V

= ZS

SET

. Parasitic resistors

to R

have negligible errors due to the 1nA (typ)

leakage current at pins FS

SET

, ZS

SET

and V

. The wide

dynamic input range ( 300mV to 5.3V) and low noise
(0.6ppm RMS) enable the LTC2401 or the LTC2402 to
directly digitize the output of the bridge sensor.

The LTC2402 is ideal for applications requiring continu-
ous monitoring of two input sensors. As shown in
Figure 30, the LTC2402 can monitor both a thermocouple

temperature probe and a cold junction temperature sen-
sor. Absolute temperature measurements can be
performed with a variety of thermocouples using digital
cold junction compensation.

The selection between CH0 and CH1 is automatic. Initially,
after power-up, a conversion is performed on CH0. For
each subsequent conversion, the input channel selection
is alternated. Embedded within the serial data output is a
status bit indicating which channel corresponds to the
conversion result. If the conversion was performed on
CH0, this bit (Bit 30) is LOW and is HIGH if the conversion
was performed on CH1 (see Figure 31).

Figure 29. Transfer Curve with Zero-Scale and Full-Scale Set

Figure 30. Isolated Temperature Measurement

00000

12.5%
UNDER
RANGE

ADC DATA OUT

FFFFF

SET

24012 F29

12.5%
EXTENDED
RANGE

SET

SCK

CH1

SDO

GND

THERMOCOUPLE

COLD JUNCTION

ISOLATION

BARRIER

PROCESSOR

CH0

12k

THERMISTOR

100

2.7V TO 5.5V

LTC2402

24012 F30

LTC2401/LTC2402

There are no extra control or status pins required to
perform the alternating 2-channel measurements. The
LTC2402 only requires two digital signals (SCK and SDO).
This simplification is ideal for isolated temperature mea-
surements or systems where minimal control signals are
available.

Pseudo Differential Applications

Generally, designers choose fully differential topologies
for several reasons. First, the interface to a 4- or 6-wire
bridge is simple (it is a differential output). Second, they
require good rejection of line frequency noise. Third, they
typically look at a small differential signal sitting on a
large common mode voltage; they need accurate
measurements of the differential signal independent of

Figure 31. Embedded Selected Channel Indicator

Figure 32. Pseudo Differential Strain Guage Application

APPLICATIO S I FOR ATIO

the common mode input voltage. Many applications
currently using fully differential analog-to-digital con-
verters for any of the above reasons may migrate to a
pseudo differential conversion using the LTC2402.

Direct Connection to a Full Bridge

The LTC2402 interfaces directly to a 4- or 6-wire bridge, as
shown in Figure 32. The LTC2402 includes a FS

SET

and a

SET

for sensing the excitation voltage directly across the

bridge. This eliminates errors due to excitation currents
flowing through parasitic resistors. The LTC2402 also
includes two single ended input channels which can tie
directly to the differential output of the bridge. The two
conversion results may be digitally subtracted yielding the
differential result.

24012 F31

SCK

SDO

CH1

· · ·

CH1 DATA OUT

CH0 DATA OUT

EOC

CH0

EOC

LTC2402

SET

SCK

CH1

SDO

CH0

GND

3-WIRE
SPI INTERFACE

24012 F32

350

= 0

EXCITATION

= 0

LTC2401/LTC2402

The LTC2402's single ended rejection of line frequencies
(

2%) and harmonics is better than 110dB. Since the

device performs two independent single ended conver-
sions each with > 110dB rejection, the overall common
mode and differential rejection is much better than the
80dB rejection typically found in other differential input
delta-sigma converters.

In addition to excellent rejection of line frequency noise,
the LTC2402 also exhibits excellent single ended noise
rejection over a wide range of frequencies due to its 4

order sinc filter. Each single ended conversion indepen-
dently rejects high frequency noise (> 60Hz). Care must be
taken to insure noise at frequencies below 15Hz and at
multiples of the ADC sample rate (15,360Hz) are not
present. For this application, it is recommended the
LTC2402 is placed in close proximity to the bridge sensor
in order to reduce the noise injected into the ADC input. By
performing three successive conversions (CH0-CH1-CH0),
the drift and low frequency noise can be measured and
compensated for digitally.

The absolute accuracy (less than 10 ppm total error) of the
LTC2402 enables extremely accurate measurement of
small signals sitting on large voltages. Each of the two
pseudo differential measurements performed by the
LTC2402 is absolutely accurate independent of the com-
mon mode voltage output from the bridge. The pseudo
differential result obtained from digitally subtracting the
two single ended conversion results is accurate to within

the noise level of the device (3

RMS

) times the square

root of 2, independent of the common mode input voltage.

Typically, a bridge sensor outputs 2mV/V full scale. With
a 5V excitation, this translates to a full-scale output of
10mV. Divided by the RMS noise of 4.2

V(= 3

V · 1.414),

this circuit yields 2,300 counts with no averaging or
amplification. If more counts are required, several conver-
sions may be averaged (the number of effective counts is
increased by a factor of square root of 2 for each doubling
of averages).

An RTD Temperature Digitizer

RTDs used in remote temperature measurements often
have long lead lengths between the ADC and RTD sensor.
These long lead lengths lead to voltage drops due to
excitation current in the interconnect to the RTD. This
voltage drop can be measured and digitally removed using
the LTC2402 (see Figure 33).

The excitation current (typically 200

A) flows from the

ADC through a long lead length to the remote temperature
sensor (RTD). This current is applied to the RTD, whose
resistance changes as a function of temperature (100

400

for 0

C to 800

C). The same excitation current flows

back to the ADC ground and generates another voltage
drop across the return leads. In order to get an accurate
measurement of the temperature, these voltage drops
must be measured and removed from the conversion
result. Assuming the resistance is approximately the same

Figure 33. RTD Remote Temperature Measurement

APPLICATIO S I FOR ATIO

LTC2402

SET

SCK

CH0

SDO

CH1

GND

3-WIRE
SPI INTERFACE

24012 F33

RTD

100

= 0

EXCITATION

= 200

EXCITATION

= 200

1000pF

0.1

LTC2401/LTC2402

for the forward and return paths (R1 = R2), the auxiliary
channel on the LTC2402 can measure this drop. These
errors are then removed with simple digital correction.

The result of the first conversion on CH0 corresponds to
an input voltage of V

RTD

+ R1 · I

EXCITATION.

The result of the

second conversion (CH1) is R1 · I

EXCITATION.

Note, the

LTC2402's input range is not limited to the supply rails, it
has underrange capabilities. The device's input range is
300mV to V

REF

+ 300mV. Adding the two conversion

results together, the voltage drop across the RTD's leads
are cancelled and the final result is V

RTD

An Isolated, 24-Bit Data Acquisition System

The LTC1535 is useful for signal isolation. Figure 34
shows a fully isolated, 24-bit differential input A/D con-
verter implemented with the LTC1535 and LTC2402. Power
on the isolated side is regulated by an LT1761-5.0 low
noise, low dropout micropower regulator. Its output is
suitable for driving bridge circuits and for ratiometric
applications.

Figure 34. Complete, Isolated 24-Bit Data Acquisition System

APPLICATIO S I FOR ATIO

During power-up, the LTC2402 becomes active at V

2.3V, while the isolated side of the LTC1535 must wait for
V

CC2

to reach its undervoltage lockout threshold of 4.2V.

Below 4.2V, the LTC1535's driver outputs Y and Z are in a
high impedance state, allowing the 1k

pull-down to

define the logic state at SCK. When the LTC2402 first
becomes active, it samples SCK; a logic "0" provided by
the 1k

pull-down invokes the external serial clock mode.

In this mode, the LTC2402 is controlled by a single clock
line from the nonisolated side of the barrier, through the
LTC1535's driver output Y. The entire power-up sequence,
from the time power is applied to V

CC1

until the LT1761's

output has reached 5V, is approximately 1ms.

Data returns to the nonisolated side through the LTC1535's
receiver at RO. An internal divider on receiver input B sets
a logic threshold of approximately 3.4V at input A, facili-
tating communications with the LTC2402's SDO output
without the need for any external components.

SCK
SDO
CS
GND

SET

CH1
CH0

SET

LTC2402

24012 F09

LT1761-5

GND

10V
TANT

16V
TANT

10V

TANT

1/2 BAT54C

ISOLATION

BARRIER

= LOGIC COMMON

= FLOATING COMMON

T1 = COILTRONICS CTX02-14659

OR SIEMENS B78304-A1477-A3

CERAMIC

A
B
Y

RO
RE
DE
DI

CC2

ST2

CC1

ST1

"SDO"

"SCK"

LOGIC 5V

OUT

SHDN

BYP

LTC1535

LTC2401/LTC2402

PACKAGE I FOR ATIO

Dimensions in inches (millimeters) unless otherwise noted.

MS10 Package

10-Lead Plastic MSOP

(LTC DWG # 05-08-1661)

* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

0.021

0.006

(0.53

0.015)

TYP

SEATING

PLANE

0.007

(0.18)

0.040

0.006

(1.02

0.15)

0.009

(0.228)

REF

0.006

0.004

(0.15

0.102)

0.034

0.004

(0.86

0.102)

0.0197

(0.50)

BSC

MSOP (MS10) 1098

1 2 3 4 5

0.193

0.006

(4.90

0.15)

7 6

0.118

0.004*

(3.00

0.102)

0.118

0.004**

(3.00

0.102)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2401/LTC2402

24012f LT/LCG 1000 4K · PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 2000

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1019

Precision Bandgap Reference, 2.5V, 5V

3ppm/

C Drift, 0.05% Max

LTC1050

Precision Chopper Stabilized Op Amp

No External Components 5

V Offset, 1.6

P-P

Noise

LT1236A-5

Precision Bandgap Reference, 5V

0.05% Max, 5ppm/

C Drift

LTC1391

8-Channel Multiplexer

Low R

: 45

, Low Charge Injection Serial Interface

LT1460

Micropower Series Reference

0.075% Max, 10ppm/

C Max Drift, 2.5V, 5V and 10V Versions

LT1461-2.5

Precision Micropower Voltage Reference

A Supply Current, 3ppm/

C Drift

LTC1535

Isolated RS485 Transceiver

2500V

RMS

Isolation

LTC2400

24-Bit, No Latency

ADC in SO-8

4ppm INL, 10ppm Total Unadjusted Error, 200

LTC2404/LTC2408

4-/8-Channel, 24-Bit, No Latency

ADC

4ppm INL, 10ppm Total Unadjusted Error, 200

LTC2410

24-Bit, Fully Differential, No Latency

ADC in SSOP-16

0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200

LTC2411

24-Bit, Fully Differential, No Latency

ADC in MS10

0.29ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200

LTC2413

24-Bit, No Latency

ADC

Simultaneous 50Hz and 60Hz Rejection, 0.16ppm Noise

LTC2420

20-Bit, No Latency

ADC in SO-8

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400

LTC2424/LTC2428

4-/8-Channel, 20-Bit, No Latency

ADC

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

TYPICAL APPLICATIO

Figure 35 shows the block diagram of a demo circuit
(contact LTC for a demonstration) of a multichannel
isolated temperature measurement system. This circuit
decodes an address to select which LTC2402 receives a
32-bit burst of SCK signal. All devices independently

convert either the thermal couple output or the thermistor
cold juntion output. After each conversion, the devices
enter their sleep state and wait for the SCK signal before
clocking out data and beginning the next conversion.

SET

CH1

SDO

SCK

CH0

SET

LTC2402

LTC1535

SET

CH1

SDO

SCK

CH0

2500V

SET

LTC2402

LTC1535

SET

CH1

SDO

SCK

24012 F35

CH0

SET

LTC2402

HC138

HC595

ADDRESS

LATCH

LTC1535

SEE FIGURE 34 FOR
THE COMPLETE CIRCUIT

HC138

SCK

SD0

(ADDRESS

OR COUNTER)

Figure 35. Mulitchannel Isolated Temperature Measurement System

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