1
LTC2482
2482f
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency
and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patent pending.
R
SOURCE
(
)
1
+FS ERROR (ppm)
20
0
20
1k
100k
2482 TA02
40
60
80
10
100
10k
40
60
80
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
F
O
= GND
T
A
= 25
C
C
IN
= 1
F
LTC2482
V
REF
V
CC
V
CC
GND
F
O
1
F
SDO
3-WIRE
SPI INTERFACE
1
F
10k
I
DIFF
= 0
10k
SCK
2482 TA01
CS
SENSE
V
IN
+
V
IN
Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Strain Gauge Transducers
Instrumentation
Industrial Process Control
DVMs and Meters
Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
600nV RMS Noise, Independent of V
REF
Operates with a Reference as Low as 100mV with
16-Bit Resolution
GND to V
CC
Input/Reference Common Mode Range
Simultaneous 50Hz/60Hz Rejection Mode
2ppm INL, No Missing Codes
1ppm Offset and 15ppm Total Unadjusted Error
No Latency: Digital Filter Settles in a Single Cycle
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
Available in a Tiny (3mm
3mm) 10-Lead
DFN Package
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
The LTC
2482 combines a 16-bit plus sign No Latency
TM analog-to-digital converter with patented Easy DriveTM
technology. The patented sampling scheme eliminates
dynamic input current errors and the shortcomings of on-
chip buffering through automatic cancellation of differen-
tial input current. This allows large external source
impedances and input signals with rail-to-rail input range
to be directly digitized while maintaining exceptional DC
accuracy.
The LTC2482 allows a wide common mode input range
(0V to V
CC
) independent of the reference voltage. The
reference can be as low as 100mV or can be tied directly
to V
CC
. The noise level is 600nV RMS independent of V
REF
.
This allows direct digitization of low level signals with 16-
bit accuracy. The LTC2482 includes an on-chip trimmed
oscillator, eliminating the need for external crystals or
oscillators and provides 87dB rejection of 50Hz and 60Hz
line frequency noise. Absolute accuracy and low drift are
automatically maintained through continuous, transpar-
ent, offset and full-scale calibration.
+FS Error vs R
SOURCE
at IN
+
and IN
16-Bit
ADC with
Easy Drive Input Current
Cancellation
2
LTC2482
2482f
(Notes 1, 2)
Supply Voltage (V
CC
) to GND ...................... 0.3V to 6V
Analog Input Voltage to GND ....... 0.3V to (V
CC
+ 0.3V)
Reference Input Voltage to GND .. 0.3V to (V
CC
+ 0.3V)
Digital Input Voltage to GND ........ 0.3V to (V
CC
+ 0.3V)
Digital Output Voltage to GND ..... 0.3V to (V
CC
+ 0.3V)
Operating Temperature Range
LTC2482C ................................................... 0
C to 70C
LTC2482I ................................................ 40
C to 85C
Storage Temperature Range ................ 65
C to 125C
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
LTC2482CDD
LTC2482IDD
ORDER PART
NUMBER
DD PART MARKING**
LBSQ
T
JMAX
= 125
C,
JA
= 43
C/ W
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
*PIN 1 MAY BE DRIVEN WITH A DIGITAL
SIGNAL IN ORDER TO REMAIN PIN
COMPATIBLE WITH THE LTC2480/LTC2484
TOP VIEW
11
DD PACKAGE
10-LEAD (3mm
3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1
F
O
SCK
GND
SDO
CS
*GND
V
CC
V
REF
IN
+
IN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1
V
REF
V
CC
, FS
V
IN
+FS (Note 5)
16
Bits
Integral Nonlinearity
5V
V
CC
5.5V, V
REF
= 5V, V
IN(CM)
= 2.5V (Note 6)
2
20
ppm of V
REF
2.7V
V
CC
5.5V, V
REF
= 2.5V, V
IN(CM)
= 1.25V (Note 6)
1
ppm of V
REF
Offset Error
2.5V
V
REF
V
CC
, GND
IN
+
= IN
V
CC
(Note 14)
0.5
5
V
Offset Error Drift
2.5V
V
REF
V
CC
, GND
IN
+
= IN
V
CC
10
nV/
C
Positive Full-Scale Error
2.5V
V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
32
ppm of V
REF
Positive Full-Scale Error Drift
2.5V
V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
0.1
ppm of
V
REF
/
C
Negative Full-Scale Error
2.5V
V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
32
ppm of V
REF
Negative Full-Scale Error Drift
2.5V
V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
0.1
ppm of
V
REF
/
C
Total Unadjusted Error
5V
V
CC
5.5V, V
REF
= 2.5V, V
IN(CM)
= 1.25V
15
ppm of V
REF
5V
V
CC
5.5V, V
REF
= 5V, V
IN(CM)
= 2.5V
ppm of V
REF
2.7V
V
CC
5.5V, V
REF
= 2.5V, V
IN(CM)
= 1.25V
ppm of V
REF
Output Noise
5V
V
CC
5.5V, V
REF
= 5V, GND
IN
= IN
+
V
CC
(Note 13)
0.6
V
RMS
The
denotes specifications which apply
over the full operating temperature range, otherwise specifications are T
A
= 25
C. (Notes 3, 4)
ELECTRICAL CHARACTERISTICS ( OR AL SPEED)
U
W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
**The temperature grade is indicated by a label on the shipping container.
3
LTC2482
2482f
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Common Mode Rejection DC
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Note 5)
140
dB
Input Common Mode Rejection
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Note 5)
140
dB
50Hz
2%
Input Common Mode Rejection
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Note 5)
140
dB
60Hz
2%
Input Normal Mode Rejection
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Notes 5, 7)
110
120
dB
50Hz
2%
Input Normal Mode Rejection
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Notes 5, 8)
110
120
dB
60Hz
2%
Input Normal Mode Rejection
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Notes 5, 9)
87
dB
50Hz/60Hz
2%
Reference Common Mode
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Note 5)
120
140
dB
Rejection DC
Power Supply Rejection DC
V
REF
= 2.5V, IN
= IN
+
= GND
120
dB
Power Supply Rejection, 50Hz
2%
V
REF
= 2.5V, IN
= IN
+
= GND (Note 7)
120
dB
Power Supply Rejection, 60Hz
2%
V
REF
= 2.5V, IN
= IN
+
= GND (Note 8)
120
dB
The
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Notes 3, 4)
CO VERTER CHARACTERISTICS
U
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN
+
Absolute/Common Mode IN
+
Voltage
GND 0.3V
V
CC
+ 0.3V
V
IN
Absolute/Common Mode IN
Voltage
GND 0.3V
V
CC
+ 0.3V
V
FS
Full Scale of the Differential Input (IN
+
IN
)
0.5V
REF
V
LSB
Least Significant Bit of the Output Code
FS/2
16
V
IN
Input Differential Voltage Range (IN
+
IN
)
FS
+FS
V
V
REF
Reference Voltage Range
0.1
V
CC
V
C
S
(IN
+
)
IN
+
Sampling Capacitance
11
pF
C
S
(IN
)
IN
Sampling Capacitance
11
pF
C
S
(V
REF
)
V
REF
Sampling Capacitance
11
pF
I
DC_LEAK
(IN
+
)
IN
+
DC Leakage Current
Sleep Mode, IN
+
= GND
10
1
10
nA
I
DC_LEAK
(IN
)
IN
DC Leakage Current
Sleep Mode, IN
= GND
10
1
10
nA
I
DC_LEAK
(V
REF
)
V
REF
Leakage Current
Sleep Mode, V
REF
= V
CC
100
1
100
nA
The
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Note 3)
A ALOG I PUT A
U
D REFERE CE
U
U
U
4
LTC2482
2482f
The
denotes specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25
C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
2.7V
V
CC
5.5V
V
CC
0.5
V
CS, F
O
V
IL
Low Level Input Voltage
2.7V
V
CC
5.5V
0.5
V
CS, F
O
V
IH
High Level Input Voltage
2.7V
V
CC
5.5V (Note 10)
V
CC
0.5
V
SCK
V
IL
Low Level Input Voltage
2.7V
V
CC
5.5V (Note 10)
0.5
V
SCK
I
IN
Digital Input Current
0V
V
IN
V
CC
10
10
A
CS, F
O
I
IN
Digital Input Current
0V
V
IN
V
CC
(Note 10)
10
10
A
SCK
C
IN
Digital Input Capacitance
10
pF
CS, F
O
C
IN
Digital Input Capacitance
10
pF
SCK
V
OH
High Level Output Voltage
I
O
= 800
A
V
CC
0.5
V
SDO
V
OL
Low Level Output Voltage
I
O
= 1.6mA
0.4
V
SDO
V
OH
High Level Output Voltage
I
O
= 800
A
V
CC
0.5
V
SCK
V
OL
Low Level Output Voltage
I
O
= 1.6mA
0.4
V
SCK
I
OZ
Hi-Z Output Leakage
10
10
A
SDO
DIGITAL I PUTS A D DIGITAL OUTPUTS
U
U
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply Voltage
2.7
5.5
V
I
CC
Supply Current
Conversion Mode (Note 12)
160
250
A
Sleep Mode (Note 12)
1
2
A
The
denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. (Note 3)
POWER REQUIRE E TS
W
U
5
LTC2482
2482f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
EOSC
External Oscillator Frequency Range
(Note 15)
10
4000
kHz
t
HEO
External Oscillator High Period
0.125
100
s
t
LEO
External Oscillator Low Period
0.125
100
s
t
CONV_1
Conversion Time
Simultaneous 50Hz/60Hz
144.1
146.9
149.9
ms
External Oscillator
41036/f
EOSC
(in kHz)
ms
f
ISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
38.4
kHz
External Oscillator (Notes 10, 11)
f
EOSC
/8
kHz
D
ISCK
Internal SCK Duty Cycle
(Note 10)
45
55
%
f
ESCK
External SCK Frequency Range
(Note 10)
4000
kHz
t
LESCK
External SCK Low Period
(Note 10)
125
ns
t
HESCK
External SCK High Period
(Note 10)
125
ns
t
DOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
0.61
0.625
0.64
ms
External Oscillator (Notes 10, 11)
192/f
EOSC
(in kHz)
ms
t
DOUT_ESCK
External SCK 24-Bit Data Output Time
(Note 10)
24/f
ESCK
(in kHz)
ms
t
1
CS
to SDO Low
0
200
ns
t2
CS
to SDO High Z
0
200
ns
t3
CS
to SCK
(Note 10)
0
200
ns
t4
CS
to SCK
(Note 10)
50
ns
t
KQMAX
SCK
to SDO Valid
200
ns
t
KQMIN
SDO Hold After SCK
(Note 5)
15
ns
t
5
SCK Set-Up Before CS
50
ns
t
6
SCK Hold After CS
50
ns
The
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. (Note 3)
TI I G CHARACTERISTICS
W
U
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: V
CC
= 2.7V to 5.5V unless otherwise specified.
V
REFCM
= V
REF
/2, FS = 0.5V
REF
V
IN
= IN
+
IN
, V
IN(CM)
= (IN
+
+ IN
)/2
Note 4: Use internal conversion clock or external conversion clock source
with f
EOSC
= 307.2kHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: f
EOSC
= 256kHz
2% (external oscillator).
Note 8: f
EOSC
= 307.2kHz
2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz rejection (internal oscillator) or
f
EOSC
= 280kHz
2% (external oscillator).
Note 10: The SCK can be configured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as digital input and the
driving clock is f
ESCK
. In internal SCK mode, the SCK pin is used as digital
output and the output clock signal during the data output is f
ISCK
.
Note 11: The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: Refer to Applications Information section for performance vs
data rate graphs.
6
LTC2482
2482f
V
IN(CM)
(V)
1
OFFSET ERROR (ppm OF V
REF
)
0.1
0.2
0.3
2
4
2482 G07
0
0.1
0
1
3
5
6
0.2
0.3
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
T
A
= 25
C
Offset Error vs V
IN(CM)
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Total Unadjusted Error
(V
CC
= 5V, V
REF
= 5V)
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
1.5
0.5
0.5
1.5
2482 G01
2.5
2
2.5
1
0
1
2
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
F
O
= GND
85
C
45
C
25
C
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
0.75
0.25
0.25
0.75
2482 G02
1.25
1.25
V
CC
= 5V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
F
O
= GND
45
C, 25C, 90C
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
0.75
0.25
0.25
0.75
2482 G03
1.25
1.25
V
CC
= 2.7V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
F
O
= GND
45
C, 25C, 90C
Total Unadjusted Error
(V
CC
= 5V, V
REF
= 2.5V)
Total Unadjusted Error
(V
CC
= 2.7V, V
REF
= 2.5V)
Integral Nonlinearity
(V
CC
= 5V, V
REF
= 5V)
Integral Nonlinearity
(V
CC
= 5V, V
REF
= 2.5V)
Integral Nonlinearity
(V
CC
= 2.7V, V
REF
= 2.5V)
INPUT VOLTAGE (V)
12
TUE (ppm OF V
REF
)
4
4
12
8
0
8
1.5
0.5
0.5
1.5
2482 G04
2.5
2
2.5
1
0
1
2
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
F
O
= GND
85
C
25
C
45
C
INPUT VOLTAGE (V)
12
TUE (ppm OF V
REF
)
4
4
12
8
0
8
0.75
0.25
0.25
0.75
2482 G05
1.25
1.25
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 1.25V
F
O
= GND
85
C
25
C
45
C
INPUT VOLTAGE (V)
12
TUE (ppm OF V
REF
)
4
4
12
8
0
8
0.75
0.25
0.25
0.75
2482 G06
1.25
1.25
V
CC
= 2.7V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
F
O
= GND
85
C
25
C
45
C
TEMPERATURE (
C)
45
0.3
OFFSET ERROR (ppm OF V
REF
)
0.2
0
0.1
0.2
15
15
30
90
2482 G08
0.1
30
0
45
60
75
0.3
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
V
IN(CM)
= GND
F
O
= GND
Offset Error vs Temperature
7
LTC2482
2482f
FREQUENCY AT V
CC
(Hz)
0
0
20
40
60
80
100
120
140
1k
100k
2482 G13
10
100
10k
1M
REJECTION (dB)
V
CC
= 4.1V DC
V
REF
= 2.5V
IN
+
= GND
IN
= GND
F
O
= GND
T
A
= 25
C
V
CC
(V)
2.5
300
FREQUENCY (kHz)
302
304
306
308
310
3.0
3.5
4.0
4.5
2482 G12
5.0
5.5
V
REF
= 2.5V
V
IN
= 0V
V
IN(CM)
= GND
F
O
= GND
TEMPERATURE (
C)
45 30
300
FREQUENCY (kHz)
304
310
15
30
45
2482 G11
302
308
306
15
0
60
75
90
V
CC
= 4.1V
V
REF
= 2.5V
V
IN
= 0V
V
IN(CM)
= GND
F
O
= GND
On-Chip Oscillator Frequency
vs Temperature
On-Chip Oscillator Frequency
vs V
CC
PSRR vs Frequency at V
CC
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
V
REF
(V)
0
0.3
OFFSET ERROR (ppm OF V
REF
)
0.2
0.1
0
0.1
0.2
0.3
1
2
3
4
2482 G10
5
V
CC
= 5V
REF
= GND
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25
C
Offset Error vs V
REF
FREQUENCY AT V
CC
(Hz)
0
140
REJECTION (dB)
120
80
60
40
0
20
100
140
2482 G14
100
20
80
180
220
200
40 60
120
160
V
CC
= 4.1V DC
1.4V
V
REF
= 2.5V
IN
+
= GND
IN
= GND
F
O
= GND
T
A
= 25
C
PSRR vs Frequency at V
CC
V
CC
(V)
2.7
OFFSET ERROR (ppm OF V
REF
)
0.1
0.2
0.3
3.9
4.7
2482 G09
0
0.1
3.1
3.5
4.3
5.1
5.5
0.2
0.3
REF
+
= 2.5V
REF
= GND
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25
C
Offset Error vs V
CC
8
LTC2482
2482f
OUTPUT DATA RATE (READINGS/SEC)
0
SUPPLY CURRENT (
A)
500
450
400
350
300
250
200
150
100
80
2482 G18
20
40
60
100
70
10
30
50
90
V
CC
= 5V
V
CC
= 3V
V
REF
= V
CC
IN
+
= GND
IN
= GND
SCK = NC
SDO = NC
CS = GND
F
O
= EXT OSC
T
A
= 25
C
TEMPERATURE (
C)
45
0
SLEEP MODE CURRENT (
A)
0.2
0.6
0.8
1.0
2.0
1.4
15
15
30
90
2482 G17
0.4
1.6
1.8
1.2
30
0
45
60
75
V
CC
= 5V
V
CC
= 2.7V
F
O
= GND
CS = V
CC
SCK = NC
SDO = NC
TYPICAL PERFOR A CE CHARACTERISTICS
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Sleep Mode Current
vs Temperature
Conversion Current
vs Data Output Rate
FREQUENCY AT V
CC
(Hz)
30600
60
40
0
30750
2482 G15
80
100
30650
30700
30800
120
140
20
REJECTION (dB)
V
CC
= 4.1V DC
0.7V
V
REF
= 2.5V
IN
+
= GND
IN
= GND
F
O
= GND
T
A
= 25
C
PSRR vs Frequency at V
CC
TEMPERATURE (
C)
45
100
CONVERSION CURRENT (
A)
120
160
180
200
15
15
30
90
2482 G16
140
30
0
45
60
75
V
CC
= 5V
V
CC
= 2.7V
F
O
= GND
CS = GND
SCK = NC
SDO = NC
Conversion Current
vs Temperature
9
LTC2482
2482f
GND (Pin 8): Ground. Shared pin for analog ground,
digital ground and reference ground. Should be connected
directly to a ground plane through a minimum impedance.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as the digital input for the external serial inter-
face clock during the Data Output period. A weak internal
pull-up is automatically activated in Internal Serial Clock
Operation mode. The Serial Clock Operation mode is de-
termined by the logic level applied to the SCK pin at power
up or during the most recent falling edge of CS.
F
O
(Pin 10): Frequency Control Pin. Digital input that
controls the conversion clock. When F
O
is connected to
GND the converter uses its internal oscillator running at
307.2kHz. The conversion clock may also be overridden
by driving the F
O
pin with an external clock in order to
change the output rate or the digital filter rejection null.
Exposed Pad (Pin 11): This pin is ground and should be
soldered to the PCB, GND plane. For prototyping purposes
this pin may remain floating.
GND (Pin 1): Ground. This pin should be tied to ground;
however, in order to remain pin compatible with the
LTC2480/LTC2484, this pin may be driven HIGH or LOW.
V
CC
(Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 8) with a 1
F tantalum capacitor in parallel with 0.1F
ceramic capacitor as close to the part as possible.
V
REF
(Pin 3): Positive Reference Input. The voltage on this
pin can have any value between 0.1V and V
CC
. The negative
reference input is GND (Pin 8).
IN
+
(Pin 4), IN
(Pin 5): Differential Analog Inputs.
The voltage on these pins can have any value between GND
0.3V and V
CC
+ 0.3V. Within these limits the converter
bipolar input range (V
IN
= IN
+
IN
) extends from
0.5 V
REF
to 0.5 V
REF
. Outside this input range the
converter produces unique overrange and underrange
output codes.
CS (Pin 6): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as long
as CS is HIGH. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
SDO (Pin 7): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = V
CC
), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
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10
LTC2482
2482f
9
4
5
7
6
10
IN
+
3
2
V
REF
V
CC
F
O
8
GND
1
GND
IN
SERIAL
INTERFACE
CS
2482 FD
SCK
SD0
AUTOCALIBRATION
AND CONTROL
INTERNAL
OSCILLATOR
3RD ORDER
ADC
REF
+
IN
+
IN
REF
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FU CTIO AL BLOCK DIAGRA
TEST CIRCUITS
1.69k
SDO
2482 TC01
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
C
LOAD
= 20pF
1.69k
SDO
2482 TC02
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
11
LTC2482
2482f
SDO
SCK
t
1
t
5
t
6
t
4
SLEEP
t
KQMAX
CONVERSION
DATA OUT
t
KQMIN
t
2
2482 TD2
CS
SDO
SCK
t
1
t
3
SLEEP
t
KQMAX
CONVERSION
DATA OUT
t
KQMIN
t
2
2482 TD1
CS
TI I G DIAGRA S
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Timing Diagram Using Internal SCK
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Timing Diagram Using External SCK
CONVERTER OPERATION
Converter Operation Cycle
The LTC2482 is a low power, delta-sigma analog-to-
digital converter with an easy to use 3-wire serial interface
and automatic differential input current cancellation. Its
operation is made up of three states. The converter oper-
ating cycle begins with the conversion, followed by the low
power sleep state and ends with the data output (see
Figure 1). The 3-wire interface consists of serial data
output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2482 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
CONVERT
SLEEP
DATA OUTPUT
2482 F01
TRUE
FALSE CS = LOW
AND
SCK
Figure 1. LTC2482 State Transition Diagram
12
LTC2482
2482f
CS
SDO
Hi-Z
SIG
BIT 21
BIT 20
BIT 19
BIT 18
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 22
BIT 23
DMY
MSB
B16
CONVERSION RESULT
LSB
SCK
SLEEP
DATA OUTPUT
EOC
CONVERSION
2482 F02
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While in this sleep state, power consumption is reduced by
two orders of magnitude. The part remains in the sleep
state as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new
conversion. The conversion result is shifted out of the
device through the serial data output pin (SDO) on the
falling edge of the serial clock (SCK) (see Figure 2).
Through timing control of the CS and SCK pins, the
LTC2482 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Easy Drive Input Current Cancellation
The LTC2482 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
network transparently removes the differential input cur-
rent. This enables external RC networks and high imped-
ance sensors to directly interface to the LTC2482 without
external amplifiers. The remaining common mode input
current is eliminated by either balancing the differential
input impedances or setting the common mode input
equal to the common mode reference (see Automatic
Input Current Cancellation section). This unique architec-
ture does not require on-chip buffers enabling input sig-
nals to swing all the way to ground and up to V
CC
.
Furthermore, the cancellation does not interfere with the
transparent offset and full-scale autocalibration and the
absolute accuracy (full scale + offset + linearity) is main-
tained with external RC networks.
Output Data Format
The LTC2482 serial output data stream is 24 bits long. The
first 3 bits represent status information indicating the sign
and conversion state. The next 17 bits are the conversion
result, MSB first. The remaining 4 bits are always zero.
Bit 21 and Bit 20 together are also used to indicate an
underrange condition (the differential input voltage is
below FS) or an overrange condition (the differential
input voltage is above +FS).
In applications where a processor generates 32 clock cycles,
or to remain compatible with higher resolution converters,
the LTC2482's digital interface will ignore extra clock edges
seen during the next conversion period after the 24th and
output "1" for the extra clock cycles. Furthermore, CS may
be pulled high prior to outputting all 24 bits, aborting the
data out transfer and initiating a new conversion.
Figure 2. Output Data Timing
13
LTC2482
2482f
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Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW.
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also
provides the underrange or overrange indication. If both
Bit 21 and Bit 20 are HIGH, the differential input voltage is
above +FS. If both Bit 21 and Bit 20 are LOW, the
differential input voltage is below FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2482 Status Bits
BIT 23 BIT 22 BIT 21 BIT 20
INPUT RANGE
EOC
DMY
SIG
MSB
V
IN
0.5 V
REF
0
0
1
1
0V
V
IN
< 0.5 V
REF
0
0
1
0
0.5 V
REF
V
IN
< 0V
0
0
0
1
V
IN
< 0.5 V
REF
0
0
0
0
Bits 20-4 are the 16-bit plus sign conversion result MSB
first.
Bits 3-0 are always low and are included to maintain
software compatibility with the LTC2480.
Data is shifted out of the SDO pin under control of the serial
clock (SCK) (see Figure 2). Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes in real time
from HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
rising edge of SCK. Bit 22 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 23rd SCK and may be latched
on the rising edge of the 24th SCK pulse. On the falling
edge of the 24th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
pins is
maintained within the 0.3V to (V
CC
+ 0.3V) absolute
maximum operating range, a conversion result is
generated for any differential input voltage
V
IN
from
FS = 0.5 V
REF
to +FS = 0.5 V
REF
. For differential input
voltages greater than +FS, the conversion result is clamped
to the value corresponding to the +FS + 1LSB. For
differential input voltages below FS, the conversion re-
sult is clamped to the value corresponding to FS 1LSB.
Table 2. LTC2482 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
BIT 23
BIT 22
BIT 21
BIT 20
BIT 19
BIT 18
BIT 17
...
BIT 4
V
IN
*
EOC
DMY
SIG
MSB
V
IN
*
FS**
0
0
1
1
0
0
0
...
0
0
FS** 1LSB
0
0
1
0
1
1
1
...
1
0
0.5 FS**
0
0
1
0
1
0
0
...
0
0
0.5 FS** 1LSB
0
0
1
0
0
1
1
...
1
0
0
0
0
1
0
0
0
0
...
0
0
1LSB
0
0
0
1
1
1
1
...
1
0
0.5 FS**
0
0
0
1
1
0
0
...
0
0
0.5 FS** 1LSB
0
0
0
1
0
1
1
...
1
0
FS**
0
0
0
1
0
0
0
...
0
0
V
IN
* < FS**
0
0
0
0
1
1
1
...
1
0
*The differential input voltage V
IN
= IN
+
IN
. **The full-scale voltage FS = 0.5 V
REF
.
BITS 3-0
14
LTC2482
2482f
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a SINC or Comb filter). For high
resolution, low frequency applications, this filter is typically
designed to reject line frequencies of 50Hz or 60Hz plus their
harmonics. The filter rejection performance is directly
related to the accuracy of the converter system clock.
The LTC2482 incorporates a highly accurate on-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
Frequency Rejection Selection (F
O
)
The LTC2482 internal oscillator provides better than 87dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for the frequency range 48Hz
to 62.4Hz.
When a fundamental rejection frequency different from 50Hz/
60Hz is required, when more than 87dB rejection is needed
for 50Hz/60Hz, or when the converter must be synchronized
with an outside source, the LTC2482 can operate with an
external conversion clock. The converter automatically de-
tects the presence of an external clock signal at the F
O
pin and
turns off the internal oscillator. The frequency f
EOSC
of the
external signal must be at least 10kHz to be detected. The
external clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and low
periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2482 provides better than 110dB
normal mode rejection in a frequency range of f
EOSC
/5120
4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/5120
is shown in Figure 3.
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Figure 3. LTC2482 Normal Mode Rejection When Using
an External Oscillator
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
EOSC
/5120(%)
12
8
4
0
4
8
12
NORMAL MODE REJECTION (dB)
2480 F03
80
85
90
95
100
105
110
115
120
125
130
135
140
Whenever an external clock is not present at the F
O
pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2482
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of F
O
.
Table 3. LTC2482 State Duration
STATE
OPERATING MODE
DURATION
CONVERT
Internal Oscillator
50Hz/60Hz Rejection
147ms, Output Data Rate
6.8 Readings/s
External Oscillator
F
O
= External Oscillator
41036/f
EOSC
s, Output Data Rate
f
EOSC
/41036 Readings/s
with Frequency f
EOSC
kHz
(f
EOSC
/5120 Rejection)
SLEEP
As Long As CS = HIGH, After a Conversion is Complete
DATA OUTPUT
Internal Serial Clock
F
O
= LOW/HIGH
As Long As CS = LOW But Not Longer Than 0.62ms
(Internal Oscillator)
(24 SCK Cycles)
F
O
= External Oscillator with
As Long As CS = LOW But Not Longer Than 192/f
EOSC
ms
Frequency f
EOSC
kHz
(24 SCK Cycles)
External Serial Clock with
As Long As CS = LOW But Not Longer Than 24/f
SCK
ms
Frequency f
SCK
kHz
(24 SCK Cycles)
15
LTC2482
2482f
Ease of Use
The LTC2482 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2482 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to time,
supply voltage change and temperature drift.
Power-Up Sequence
The LTC2482 automatically enters an internal reset
state when the power supply voltage V
CC
drops below
approximately 2V. This feature guarantees the integrity of
the conversion result and of the serial interface mode
selection. (See the 2-wire I/O sections in the Serial Inter-
face Timing Modes section.)
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2482 starts a normal conversion cycle and
follows the succession of states described in Figure 1. The
first conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
The LTC2482 external reference voltage range is 0.1V to
V
CC
. The converter output noise is determined by the
thermal noise of the front-end circuits, and as such, its
value in nanovolts is nearly constant with reference volt-
age. Since the transition noise (600nV) is much less than
the quantization noise (V
REF
/2
17
), a decrease in the refer-
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ence voltage will increase the converter resolution. A
reduced reference voltage will improve the converter
performance when operated with an external conversion
clock (external F
O
signal) at substantially higher output
data rates (see the Output Data Rate section).
The negative reference input to the converter is internally
tied to GND. GND (Pin 8) should be connected to a ground
plane through as short a trace as possible to minimize
voltage drop. The LTC2482 has an average operational
current of 160
A and for 1 parasitic resistance, the
voltage drop of 160
V causes a gain error of 2LSB for
V
REF
= 5V.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN
+
and IN
input pins
extending from GND 0.3V to V
CC
+ 0.3V. Outside these
limits, the ESD protection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2482 converts bipolar differential
input signal, V
IN
= IN
+
IN
, from FS to +FS where
FS = 0.5 V
REF
. Outside this range, the converter
indicates the overrange or the underrange condition using
distinct output codes. Since the differential input current
cancellation does not rely on an on-chip buffer,
current cancellation as well as DC performance is
maintained rail-to-rail.
Input signals applied to IN
+
and IN
pins may extend by
300mV below ground and above V
CC
. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN
+
and IN
pins without affecting the perfor-
mance of the devices. The effect of the series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sec-
tions. In addition, series resistors will introduce a tem-
perature dependent offset error due to the input leakage
current. A 1nA input leakage current will develop a 1ppm
offset error on a 5k resistor if V
REF
= 5V. This error has a
very strong temperature dependency.
16
LTC2482
2482f
SERIAL INTERFACE TIMING MODES
The LTC2482's 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle or continuous conversion.
The following sections describe each of these serial inter-
face timing modes in detail. In all these cases, the con-
verter can use the internal oscillator (F
O
= LOW or F
O
=
HIGH) or an external oscillator connected to the F
O
pin.
Refer to Table 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 4.
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK
is seen while CS is LOW. The output data is shifted out of
the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 24th rising edge of SCK. On the 24th falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress. In
applications where the processor generates 32 clock
cycles, or to remain compatible with higher resolution
converters, the LTC2482's digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and outputs "1" for the extra clock cycles.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 24th
falling edge of SCK (see Figure 5). On the rising edge of CS,
the device aborts the data output state and immediately
initiates a new conversion. This is useful for systems not
requiring all 24 bits of output data, aborting an invalid con-
version cycle or synchronizing the start of a conversion.
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Table 4. LTC2482 Interface Timing Modes
CONVERSION
DATA
CONNECTION
SCK
CYCLE
OUTPUT
and
CONFIGURATION
SOURCE
CONTROL
CONTROL
WAVEFORMS
External SCK, Single Cycle Conversion
External
CS and SCK
CS and SCK
Figures 4, 5
External SCK, 2-Wire I/O
External
SCK
SCK
Figure 6
Internal SCK, Single Cycle Conversion
Internal
CS
CS
Figures 7, 8
Internal SCK, 2-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 9
17
LTC2482
2482f
Figure 4. External Serial Clock, Single Cycle Operation
Figure 5. External Serial Clock, Reduced Data Output Length
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EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
TEST EOC
MSB
SIG
BIT 0
LSB
BIT 4
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
SLEEP
SLEEP
DATA OUTPUT
CONVERSION
2482 F04
CONVERSION
Hi-Z
Hi-Z
Hi-Z
TEST EOC
V
CC
F
O
V
REF
IN
+
IN
SCK
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
7
8,1
6
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1
F
2.7V TO 5.5V
LTC2482
3-WIRE
SPI INTERFACE
TEST EOC
(OPTIONAL)
SDO
SCK
(EXTERNAL)
CS
DATA
OUTPUT
CONVERSION
SLEEP
SLEEP
SLEEP
TEST EOC
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
CONVERSION
2482 F05
MSB
SIG
BIT 8
BIT 19
BIT 18
BIT 17
BIT 16
BIT 9
BIT 20
BIT 21
BIT 22
EOC
BIT 23
BIT 0
EOC
Hi-Z
TEST EOC
TEST EOC
(OPTIONAL)
V
CC
F
O
V
REF
IN
+
IN
SCK
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
7
8,1
6
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1
F
2.7V TO 5.5V
LTC2482
3-WIRE
SPI INTERFACE
18
LTC2482
2482f
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal (see Figure 6). CS
may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 4ms after V
CC
exceeds approximately 2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The output data is shifted out of the SDO pin
on each falling edge of SCK. EOC can be latched on the
first rising edge of SCK. On the 24th falling edge of SCK,
SDO goes HIGH (EOC = 1) indicating a new conversion
has begun. In applications where the processor generates
32 clock cycles, or to remain compatible with higher
resolution converters, the LTC2482's digital interface will
ignore extra clock edges seen during the next conversion
period after the 24th and outputs "1" for the extra clock
cycles.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle (see Figure 7).
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
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Figure 6. External Serial Clock, CS = 0 Operation
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
MSB
SIG
LSB
BIT 4
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
DATA OUTPUT
CONVERSION
2482 F06
CONVERSION
V
CC
F
O
V
REF
IN
+
IN
SCK
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
7
8,1
6
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1
F
2.7V TO 5.5V
LTC2482
2-WIRE
SPI INTERFACE
19
LTC2482
2482f
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time t
EOCtest
after the falling edge of CS (if EOC = 0) or t
EOCtest
after EOC
goes LOW (if CS is LOW during the falling edge of EOC).
The value of t
EOCtest
is 12
s if the device is using its internal
oscillator. If F
O
is driven by an external oscillator of
frequency f
EOSC
, then t
EOCtest
is 3.6/f
EOSC
in seconds. If CS
is pulled HIGH before time t
EOCtest
, the device returns to
the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 24th rising edge. The output data is shifted out of
the SDO pin on each falling edge of SCK. The internally
generated serial clock is output to the SCK pin. This signal
may be used to shift the conversion result into external
circuitry. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result on the 24th rising
edge of SCK. After the 24th rising edge, SDO goes HIGH
(EOC = 1), SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 24th rising edge of
SCK (see Figure 8). On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2482's internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2482's internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH once
the external driver goes Hi-Z. On the next CS falling edge,
the device will remain in the internal SCK timing mode.
APPLICATIO S I FOR ATIO
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Figure 7. Internal Serial Clock, Single Cycle Operation
SDO
SCK
(INTERNAL)
CS
MSB
SIG
BIT 0
LSB
BIT 4
TEST EOC
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
EOC
BIT 23
SLEEP
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
2482 F07
<t
EOCtest
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TEST EOC
V
CC
F
O
V
REF
IN
+
IN
SCK
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
10k
V
CC
7
8,1
6
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1
F
2.7V TO 5.5V
LTC2482
3-WIRE
SPI INTERFACE
20
LTC2482
2482f
APPLICATIO S I FOR ATIO
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A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t
EOCtest
), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire (output only) interface. The
conversion result is shifted out of the device by an inter-
nally generated serial clock (SCK) signal (see Figure 9).
CS may be permanently tied to ground, simplifying the
user interface or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
CC
exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data input/
output cycle begins on the first rising edge of SCK and
ends after the 24th rising edge. The output data is shifted
out of the SDO pin on each falling edge of SCK. The
internally generated serial clock is output to the SCK pin.
This signal may be used to shift the conversion result into
external circuitry. EOC can be latched on the first rising
edge of SCK and the last bit of the conversion result can
be latched on the 24th rising edge of SCK. After the 24th
rising edge, SDO goes HIGH (EOC = 1) indicating a new
conversion is in progress. SCK remains HIGH during the
conversion.
Figure 8. Internal Serial Clock, Reduce Data Output Length
SDO
SCK
(INTERNAL)
CS
> t
EOCtest
MSB
SIG
BIT 8
TEST EOC
(OPTIONAL)
TEST EOC
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
EOC
BIT 23
EOC
BIT 0
SLEEP
SLEEP
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DATA
OUTPUT
CONVERSION
CONVERSION
SLEEP
2482 F08
<t
EOCtest
TEST EOC
V
CC
F
O
V
REF
IN
+
IN
SCK
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
10k
V
CC
7
8,1
6
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1
F
2.7V TO 5.5V
LTC2482
3-WIRE
SPI INTERFACE
21
LTC2482
2482f
APPLICATIO S I FOR ATIO
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PRESERVING THE CONVERTER ACCURACY
The LTC2482 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
extreme accuracy capability of this part, some simple
precautions are required.
Digital Signal Levels
The LTC2482's digital interface is easy to use. Its digital
inputs (F
O
, CS and SCK in External SCK mode of operation)
accept standard CMOS logic levels and the internal hyster-
esis receivers can tolerate edge transition times as slow as
100
s. However, some considerations are required to take
advantage of the exceptional accuracy and low supply
current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(V
CC
0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (F
O
, CS and
SCK in External SCK mode of operation) is within
this range, the power supply current may increase even
if the signal in question is at a valid logic level.
For micropower operation, it is recommended to
drive all digital input signals to full CMOS levels
[V
IL
< 0.4V and V
OH
> (V
CC
0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins can
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the imped-
ance mismatch of the circuit board trace at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver to
the LTC2482. For reference, on a regular FR-4 board,
signal propagation velocity is approximately 183ps/inch
for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.
Parallel termination near the LTC2482 pin will eliminate
this problem but will increase the driver power dissipa-
tion. A series resistor between 27
and 56 placed near
the driver output pin will also eliminate this problem
without additional power dissipation. The actual resistor
value depends upon the trace impedance and connection
topology.
Figure 9. Internal Serial Clock, CS = 0 Continuous Operation
SDO
SCK
(INTERNAL)
CS
LSB
MSB
SIG
BIT 4
BIT 0
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
EOC
BIT 23
DATA OUTPUT
CONVERSION
CONVERSION
2482 F09
V
CC
F
O
V
REF
IN
+
IN
SCK
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
7
8,1
6
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1
F
2.7V TO 5.5V
LTC2482
2-WIRE
SPI INTERFACE
10k
V
CC
22
LTC2482
2482f
APPLICATIO S I FOR ATIO
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An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input architec-
ture reduces the converter's sensitivity to ground
currents.
Particular attention must be given to the connection of the
F
O
signal when the LTC2482 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such
perturbations can occur due to asymmetric capacitive
coupling between the F
O
signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F
O
signal trace and the input/reference sig-
nals. When the F
O
signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the F
O
connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F
O
signal as well as the loop area for
the differential input and reference connections. Even
when F
0
is not driven, other nearby signals pose similar
EMI threats which will be minimized by following good
layout practices.
Driving the Input and Reference
The input and reference pins of the LTC2482 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca-
pacitors are switching between these four pins transfer-
ring small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 10.
For a simple approximation, the source impedance R
S
driving an analog input pin (IN
+
, IN
, V
REF
+
or GND) can be
considered to form, together with R
SW
and C
EQ
(see
Figure 10), a first order passive network with a time
constant
= (R
S
+ R
SW
) C
EQ
. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant
. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
Figure 10. LTC2482 Equivalent Analog Input Circuit
V
REF
+
V
IN
+
V
CC
R
SW
(TYP)
10k
I
LEAK
I
LEAK
V
CC
I
LEAK
I
LEAK
V
CC
R
SW
(TYP)
10k
C
EQ
12pF
(TYP)
R
SW
(TYP)
10k
I
LEAK
I
IN
+
V
IN
I
IN
I
REF
+
I
REF
2482 F10
I
LEAK
V
CC
I
LEAK
I
LEAK
SWITCHING FREQUENCY
f
SW
= 123kHz INTERNAL OSCILLATOR
f
SW
= 0.4 f
EOSC
EXTERNAL OSCILLATOR
GND
R
SW
(TYP)
10k
I IN
I IN
V
V
R
I REF
V
V
V
R
V
R
V
D
R
V
V
V
R
V
V
R
where
AVG
AVG
IN CM
REF CM
EQ
AVG
REF
INCM
REFCM
EQ
REF
EQ
REF
T
EQ
REF
REF CM
IN CM
EQ
IN
REF
EQ
+
+
( )
=
( )
=
-
( )
=
-
+
-
-
+
(
)
(
)
(
)
(
)
(
)
.
.
.
.
.
.
0 5
1 5
0 5
0 5
1 5
0 5
2
:
:
V
V
IN
IN
V
IN
IN
REFCM
IN
INCM
=
=
-
=
+
=
=
(
)
+
-
+
-
2
R
2.98M
INTERNAL OSCILLATOR
R
0.915 10
/ f
EXTERNAL OSCILLATOR
D IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
EQ
EQ
12
EOSC
T
WHERE REF
IS INTERNALLY TIED TO GND
V
IN
2
V
REF
+
2
23
LTC2482
2482f
APPLICATIO S I FOR ATIO
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When using the internal oscillator, the LTC2482's front-
end switched-capacitor network is clocked at 123kHz
corresponding to an 8.1
s sampling period. Thus, for
settling errors of less than 1ppm, the driving source
impedance should be chosen such that
8.1s/14 =
580ns. When an external oscillator of frequency f
EOSC
is
used, the sampling period is 2.5/f
EOSC
and, for a settling
error of less than 1ppm,
0.178/f
EOSC
.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is low
(up to 10k
with no external bypass capacitor or up to
500
with 0.001F bypass), complete settling of the input
occurs. In this case, no errors are introduced and direct
digitization of the sensor is possible.
For many applications, the sensor output impedance com-
bined with external bypass capacitors produces RC time
constants much greater than the 580ns required for 1ppm
accuracy. For example, a 10k
bridge driving a 0.1F
bypass capacitor has a time constant an order of magni-
tude greater than the required maximum. Historically,
settling issues were solved using buffers. These buffers led
to increased noise, reduced DC performance (Offset/Drift),
limited input/output swing (cannot digitize signals near
ground or V
CC
), added system cost and increased power.
The LTC2482 uses a proprietary switching algorithm that
forces the average differential input current to zero inde-
pendent of external settling errors. This allows accurate
direct digitization of high impedance sensors without the
need for buffers. Additional errors resulting from mis-
matched leakage currents must also be taken into account.
The switching algorithm forces the average input current
on the positive input (I
IN
+
) to be equal to the average input
current on the negative input (I
IN
). Over the complete
conversion cycle, the average differential input current
(I
IN
+
I
IN
) is zero. While the differential input current is
zero, the common mode input current (I
IN
+
+ I
IN
)/2 is
proportional to the difference between the common mode
input voltage (V
INCM
) and the common mode reference
voltage (V
REFCM
).
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balance bridge type application, both the differ-
ential and common mode input current are zero. The
accuracy of the converter is unaffected by settling errors.
Mismatches in source impedances between IN
+
and IN
also do not affect the accuracy.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between V
INCM
and V
REFCM
. For a reference
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
0.74
A. This common mode input current has no effect on
the accuracy if the external source impedances tied to IN
+
and IN
are matched. Mismatches in these source imped-
ances lead to a fixed offset error but do not affect the
linearity or full-scale reading. A 1% mismatch in 1k
source resistances leads to a 1LSB shift (74
V) in offset
voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
the common mode input current effects are rejected by the
large CMRR of the LTC2482 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errors proportional to the difference between the common
mode input voltage and the common mode reference
voltage. 1% mismatches in 1k
source resistances lead
to gain worst-case gain errors on the order of 1LSB (for 1V
differences in reference and input common mode volt-
age). Table 5 summarizes the effects of mismatched
source impedance and differences in reference/input com-
mon mode voltages.
Table 5. Suggested Input Configuration for LTC2482
BALANCED INPUT
UNBALANCED INPUT
RESISTANCES
RESISTANCES
Constant
C
IN
> 1nF at Both
C
IN
> 1nF at Both IN
+
V
IN(CM)
V
REF(CM)
IN
+
and IN
. Can Take
and IN
. Can Take Large
Large Source Resistance
Source Resistance.
with Negligible Error
Unbalanced Resistance
Results in an Offset
Which Can be Calibrated
Varying
C
IN
> 1nF at Both IN
+
Minimize IN
+
and IN
V
IN(CM)
V
REF(CM)
and IN
. Can Take Large
Capacitors and Avoid
Source Resistance with
Large Source Impedance
Negligible Error
(< 5k Recommended)
24
LTC2482
2482f
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
C) are
used for the external source impedance seen by IN
+
and
IN
, the expected drift of the dynamic current and offset
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
10nA max), results
in a small offset shift. A 1k source resistance will create a
1
V typical and 10V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2482 samples the differential
reference pins V
REF
+
and GND transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in two distinct situations.
For relatively small values of the external reference capaci-
tors (C
REF
< 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
REF
will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
REF
> 1nF) may be
required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator (50Hz/60Hz rejection), the differential refer-
APPLICATIO S I FOR ATIO
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Figure 11. An RC Network at IN
+
and IN
Figure 12. +FS Error vs R
SOURCE
at IN
+
or IN
Figure 13. FS Error vs R
SOURCE
at IN
+
or IN
C
IN
2482 F11
V
INCM
+ 0.5V
IN
R
SOURCE
IN
+
LTC2482
C
PAR
20pF
C
IN
V
INCM
0.5V
IN
R
SOURCE
IN
C
PAR
20pF
R
SOURCE
(
)
1
+FS ERROR (ppm)
20
0
20
1k
100k
2482 F12
40
60
80
10
100
10k
40
60
80
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
F
O
= GND
T
A
= 25
C
C
IN
= 0pF
C
IN
= 100pF
C
IN
= 1nF, 0.1
F, 1F
R
SOURCE
(
)
1
FS ERROR (ppm) 20
0
20
1k
100k
2482 F13
40
60
80
10
100
10k
40
60
80
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 1.25V
V
IN
= 3.75V
F
O
= GND
T
A
= 25
C
C
IN
= 0pF
C
IN
= 100pF
C
IN
= 1nF, 0.1
F, 1F
25
LTC2482
2482f
ence resistance is 1.1M
and the resulting full-scale
error is 0.46ppm for each ohm of source resistance
driving the V
REF
pin. When F
O
is driven by an external
oscillator with a frequency f
EOSC
(external conversion
clock operation), the typical differential reference resis-
tance is 0.33 10
12
/f
EOSC
and each ohm of source
resistance driving the V
REF
pin will result in 1.53 10
6
f
EOSC
ppm gain error. The typical +FS and FS errors for
various combinations of source resistance seen by the
V
REF
pin and external capacitance connected to that pin
are shown in Figures 14-17.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
APPLICATIO S I FOR ATIO
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Figure 14. +FS Error vs R
SOURCE
at V
REF
(Small C
REF
)
R
SOURCE
(
)
0
+FS ERROR (ppm)
50
70
90
10k
2482 F14
30
10
40
60
80
20
0
10
10
100
1k
100k
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
F
O
= GND
T
A
= 25
C
C
REF
= 0.01
F
C
REF
= 0.001
F
C
REF
= 100pF
C
REF
= 0pF
Figure 15. FS Error vs R
SOURCE
at V
REF
(Small C
REF
)
Figure 16. +FS Error vs R
SOURCE
at V
REF
(Large C
REF
)
R
SOURCE
(
)
0
FS ERROR (ppm)
30
10
10
10k
2482 F15
50
70
40
20
0
60
80
90
10
100
1k
100k
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 1.25V
V
IN
= 3.75V
F
O
= GND
T
A
= 25
C
C
REF
= 0.01
F
C
REF
= 0.001
F
C
REF
= 100pF
C
REF
= 0pF
R
SOURCE
(
)
0
+FS ERROR (ppm)
300
400
500
800
2482 F16
200
100
0
200
400
600
1000
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
F
O
= GND
T
A
= 25
C
C
REF
= 1
F, 10F
C
REF
= 0.1
F
C
REF
= 0.01
F
Figure 17. FS Error vs R
SOURCE
at V
REF
(Large C
REF
)
R
SOURCE
(
)
0
FS ERROR (ppm)
200
100
0
800
2482 F17
300
400
500
200
400
600
1000
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 1.25V
V
IN
= 3.75V
F
O
= GND
T
A
= 25
C
C
REF
= 1
F, 10F
C
REF
= 0.1
F
C
REF
= 0.01
F
The INL is caused by the input dependent terms V
IN
2
/
(V
REF
R
EQ
) (0.5 V
REF
D
T
)/R
EQ
in the reference pin
current as expressed in Figure 10. When using internal
oscillator with 50Hz/60Hz rejection, every 100
of refer-
ence source resistance translates into about 0.61ppm
additional INL error. When F
O
is driven by an external
oscillator with a frequency f
EOSC
, every 100
of source
resistance driving V
REF
translates into about 1.99 10
6
f
EOSC
ppm additional INL error. Figure 18 shows the
typical INL error due to the source resistance driving the
V
REF
pin when large C
REF
values are used. The user is
advised to minimize the source impedance driving the
V
REF
pin.
26
LTC2482
2482f
APPLICATIO S I FOR ATIO
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Output Data Rate
When using its internal oscillator, the LTC2482 produces
6.8ps with a notch frequency of 55Hz, for simultaneous
50Hz/60Hz rejection. The actual output data rate will
depend upon the length of the sleep and data output
phases which are controlled by the user and which can be
made insignificantly short. When operated with an exter-
nal conversion clock (F
O
connected to an external oscilla-
tor), the LTC2482 output data rate can be increased as
desired. The duration of the conversion phase is 41036/
f
EOSC
.
An increase in f
EOSC
over the nominal 307.2kHz will
translate into a proportional increase in the maximum
output data rate. The increase in output rate is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in f
EOSC
will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power
line frequency. In many applications, the subsequent
performance degradation can be substantially reduced by
relying upon the LTC2482's exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and
should maintain a very high degree of matching and
symmetry in the circuits driving the IN
+
and IN
pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (C
IN
, C
REF
) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of f
EOSC
. If small external input and/or
reference capacitors (C
IN
, C
REF
) are used, the effect of the
external source resistance upon the LTC2482 typical
performance can be inferred from Figures 12, 13, 14 and
15 in which the horizontal axis is scaled by 307200/f
EOSC
.
Third, an increase in the frequency of the external oscilla-
tor above 1MHz (a more than 3
increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (V
REFCM
V
INCM
) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (V
REFCM
V
INCM
)/(V
REF
R
EQ
) full-scale gain error
which is 0.067ppm when using the internal oscillator
(50Hz/60Hz rejection). If an external clock is used, the
corresponding extra gain error is 0.22 10
6
f
EOSC
ppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typically better
than 0.5%. Such a specification can also be easily achieved
by an external clock. When relatively stable resistors
(50ppm/
C) are used for the external source impedance
seen by V
REF
+
and GND, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(
10nA max), results in a small gain error. A 100 source
resistance will create a 0.05
V typical and 0.5V maxi-
mum full-scale error.
Figure 18. INL vs Differential Input Voltage and
Reference Source Resistance for C
REF
> 1
F
V
IN
/V
REF
(V)
0.5
INL (ppm OF V
REF
)
2
6
10
0.3
2482 F18
2
6
0
4
8
4
8
10
0.3
0.1
0.1
0.5
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25
C
C
REF
= 10
F
R = 1k
R = 100
R = 500
27
LTC2482
2482f
Figure 24. Resolution (INL
MAX
1LSB) vs
Output Data Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
22
10
50
70
2482 F24
14
20
40
90 100
20 30
60
80
V
CC
= 5V, V
REF
= 2.5V
V
CC
= V
REF
= 5V
V
IN(CM)
= V
REF(CM)
V
IN
= 0V
REF
= GND
F
O
= EXT CLOCK
T
A
= 25
C
RES = LOG 2 (V
REF
/INL
MAX
)
Figure 19. Offset Error vs Output Data Rate and Temperature
Figure 20. +FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
10
OFFSET ERROR (ppm OF V
REF
)
10
30
50
0
20
40
20
40
60
80
2482 F19
100
10
0
30
50
70
90
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
V
IN
= 0V
F
O
= EXT CLOCK
T
A
= 85
C
T
A
= 25
C
OUTPUT DATA RATE (READINGS/SEC)
0
0
+FS ERROR (ppm OF V
REF
)
500
1500
2000
2500
3500
10
50
70
2482 F20
1000
3000
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
F
O
= EXT CLOCK
T
A
= 85
C
T
A
= 25
C
Figure 22. Resolution (INL
MAX
1LSB)
vs Output Data Rate and Temperature
Figure 23. Offset Error vs Output
Data Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
22
10
50
70
2482 F22
14
20
40
90 100
20 30
60
80
T
A
= 25
C
T
A
= 85
C
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
F
O
= EXT CLOCK
RES = LOG 2 (V
REF
/INL
MAX
)
OUTPUT DATA RATE (READINGS/SEC)
0
10
OFFSET ERROR (ppm OF V
REF
)
5
5
10
20
10
50
70
2482 F23
0
15
40
90 100
20 30
60
80
V
CC
= 5V, V
REF
= 2.5V
V
CC
= V
REF
= 5V
V
IN(CM)
= V
REF(CM)
V
IN
= 0V
F
O
= EXT CLOCK
T
A
= 25
C
APPLICATIO S I FOR ATIO
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Figure 21. FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
3500
FS ERROR (ppm OF V
REF
)
3000
2000
1500
1000
0
10
50
70
2482 F21
2500
500
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
F
O
= EXT CLOCK
T
A
= 85
C
T
A
= 25
C
28
LTC2482
2482f
The conversion noise (600nV
RMS
typical for V
REF
= 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is 47nV
Hz
for an infinite bandwidth source and 64nV
Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in order
to reduce the output referred noise and relatively high
bandwidth (at least 500kHz) necessary to drive the input
switched-capacitor network. A possible solution is a high
gain, low bandwidth amplifier stage followed by a high
bandwidth unity-gain buffer.
When external amplifiers are driving the LTC2482, the
ADC input referred system noise calculation can be sim-
plified by Figure 26. The noise of an amplifier driving the
LTC2482 input pin can be modeled as a band limited white
noise source. Its bandwidth can be approximated by the
bandwidth of a single pole lowpass filter with a corner
frequency f
i
. The amplifier noise spectral density is n
i
.
From Figure 26, using f
i
as the x-axis selector, we can find
on the y-axis the noise equivalent bandwidth freq
i
of the
input driving amplifier. This bandwidth includes the band
limiting effects of the ADC internal calibration and filter-
ing. The noise of the driving amplifier referred to the
converter input and including all these effects can be
calculated as N = n
i
freq
i
. The total system noise
Figure 26. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
INPUT SIGNAL ATTENUATION (dB)
3
2
1
0
4
2482 F25
4
5
6
1
2
3
5
Figure 25. Input Signal Bandwidth Using the Internal Oscillator
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
10
0.1
1
10
100
1k
10k
100k
1M
2482 F26
0.1
100
APPLICATIO S I FOR ATIO
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degradation in the converter accuracy and linearity. Typi-
cal measured performance curves for output data rates up
to 100 readings per second are shown in Figures 19 to 24.
In order to obtain the highest possible level of accuracy from
this converter at output data rates above 20 readings per
second, the user is advised to maximize the power supply
voltage used and to limit the maximum ambient operating
temperature. In certain circumstances, a reduction of the
differential reference voltage may be beneficial.
Input Bandwidth
The combined effect of the internal SINC
4
digital filter and
of the analog and digital autocalibration circuits deter-
mines the LTC2482 input bandwidth. When the internal
oscillator is used the 3dB input bandwidth is 3.3Hz. If an
external conversion clock generator of frequency f
EOSC
is
connected to the F
O
pin, the 3dB input bandwidth is
10.7 10
6
f
EOSC
.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2482 input bandwidth is shown in
Figure 25. When an external oscillator of frequency f
EOSC
is used, the shape of the LTC2482 input bandwidth can be
derived from Figure 25 in which the horizontal axis is
scaled by f
EOSC
/307200.
29
LTC2482
2482f
f
OUTMAX
where f
N
is the notch frequency and f
OUTMAX
is
the maximum output data rate. In the internal oscillator
mode with 50Hz/60Hz rejection, f
S
= 13960Hz. In the
external oscillator mode, f
S
= f
EOSC
/20.
The regions of low rejection occurring at integer multiples
of f
S
have a very narrow bandwidth. Magnified details of
the normal mode rejection curves are shown in Figure 27
(rejection near DC) and Figure 28 (rejection at f
S
= 256f
N
)
where f
N
represents the notch frequency. These curves
have been derived for the external oscillator mode but they
can be used in all operating modes by appropriately
selecting the f
N
value.
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by
Figure 29. Typical measured values of the normal mode
rejection of the LTC2482 operating with an internal
oscillator (50Hz/60Hz rejection) is shown in Figure 29.
As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2482. If passive RC components are placed in
front of the LTC2482, the input dynamic current should be
considered (see Input Current section). In this case, the
differential input current cancellation feature of the
LTC2482 allows external RC networks without significant
degradation in DC performance.
Traditional high order delta-sigma modulators, while pro-
viding very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The
(referred to the LTC2482 input) can now be obtained by
summing as square root of sum of squares the three ADC
input referred noise sources: the LTC2482 internal noise,
the noise of the IN
+
driving amplifier and the noise of the
IN
driving amplifier.
If the F
O
pin is driven by an external oscillator of frequency
f
EOSC
, Figure 26 can still be used for noise calculation if the
x-axis is scaled by f
EOSC
/307200. For large values of the
ratio f
EOSC
/307200, the Figure 26 plot accuracy begins to
decrease, but at the same time the LTC2482 noise floor
rises and the noise contribution of the driving amplifiers
lose significance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2482 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature of the LTC2482
allows external lowpass filtering without degrading the DC
performance of the device.
The SINC
4
digital filter provides greater than 120dB nor-
mal mode rejection at all frequencies except DC and
integer multiples of the modulator sampling frequency
(f
S
). The LTC2482's autocalibration circuits further sim-
plify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, f
S
= 256 f
N
= 2048
APPLICATIO S I FOR ATIO
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Figure 27. Input Normal Mode Rejection at DC
Figure 28. Input Normal Mode Rejection at f
S
= 256f
N
INPUT SIGNAL FREQUENCY (Hz)
INPUT NORMAL MODE REJECTION (dB)
2482 F27
0
10
20
30
40
50
60
70
80
90
100
110
120
f
N
0
2f
N
3f
N
4f
N
5f
N
6f
N
7f
N
8f
N
f
N
= f
EOSC
/5120
INPUT SIGNAL FREQUENCY (Hz)
250f
N
252f
N
254f
N
256f
N
258f
N
260f
N
262f
N
INPUT NORMAL MODE REJECTION (dB)
2482 F28
0
10
20
30
40
50
60
70
80
90
100
110
120
30
LTC2482
2482f
proprietary architecture used for the LTC2482 third order
modulator resolves this problem and guarantees a predict-
able stable behavior at input signal levels of up to 150% of
full scale. In many industrial applications, it is not uncom-
mon to have to measure microvolt level signals superim-
posed over volt level perturbations and the LTC2482 is
eminently suited for such tasks. When the perturbation is
differential, the specification of interest is the normal mode
rejection for large input signal levels. With a reference
voltage V
REF
= 5V, the LTC2482 has a full-scale differential
input range of 5V peak-to-peak.
Remote Sensing with Easy Drive Input Current
Cancellation
One problem faced by designers of high performance data
acquisition systems is achieving data sheet specified per-
formance in a real world environment. One advantage delta
sigma type ADCs offer over the alternatives is on-chip digi-
tal filtering (noise suppression). The disadvantage (solved
by Easy Drive technology) is the drive requirements inher-
ent in delta sigma ADC architectures. In order to demon-
strate the full potential of the Easy Drive technology, a
practical test case was characterized (see Figure 30).
Precise measurements of offset, noise and linearity were
measured under extreme test conditions. A remote sensor
was digitized through 100 meters of cable applied to an RC
network with low accuracy 1% resistors. A remote sensor
voltage was swept from 0 to 2.5 with less than 1LSB
linearity error (see Figure 31). Noise levels of 650nV RMS
and offsets below 5
V were measured (see Figure 32).
APPLICATIO S I FOR ATIO
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Figure 29. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale
INPUT FREQUENCY (Hz)
0
20
40
60
80
100
120
140
160
180
200
220
NORMAL MODE REJECTION (dB)
2482 F29
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
V
IN(P-P)
= 5V
T
A
= 25
C
MEASURED DATA
CALCULATED DATA
Fundamentally, an oversampled data converter (
ADC)
directly connected to a long cable and a low precision RC
network leads to many problems greatly limiting the
accuracy of the system. These include transmission line
effects, noise and DC settling errors.
The sampling network of
ADCs injects high frequency
current spikes into the cable. The resulting voltage spikes
are reflected through the long wire and result in excessive
noise and reduced accuracy. This problem is solved by
placing a bypass capacitor across the input to the ADC.
This capacitor serves as a charge reservoir for the ADC's
sampling network and reduces the voltage spikes by the
ratio of internal sampling capacitor to external bypass
capacitor. A 1
F bypass capacitor reduces the voltage
spikes generated by the sampling network by a factor of
50,000 (1V spikes are reduced to 18
V) and is sufficient
to achieve data sheet specified noise and accuracy.
The addition the large external bypass capacitor results in
input settling errors. Typical 24-bit high resolution delta
sigma ADCs sample at time intervals on the order of 10
s.
In order to fully settle with a 1
F bypass capacitor, the
source impedance must be lower than 1
. Source imped-
ances greater than 1
result in offset and full-scale errors
due to the accumulation of charge settling errors over the
complete conversion cycle. Easy Drive technology auto-
matically removes the differential component of this
error. The remaining common mode error is reduced to a
fixed offset as a function of the external resistor matching
seen at the plus and minus input of the ADC. In this
extreme case, 1k external resistors with 1% matching
result in a 3.5
V offset while the linearity and noise are
unaffected.
The signal path contains a 100 meter wire connected to
a low voltage source in a very noisy environment. Line
frequency noise is rejected by the on chip digital filter
and guaranteed by the high accuracy on chip oscillator.
High frequency noise is rejected by the external lowpass
filter formed by the input bypass capacitor and external
resistors.
31
LTC2482
2482f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm
3mm)
(Reference LTC DWG # 05-08-1698)
3.00
0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38
0.10
BOTTOM VIEW--EXPOSED PAD
1.65
0.10
(2 SIDES)
0.75
0.05
R = 0.115
TYP
2.38
0.10
(2 SIDES)
1
5
10
6
PIN 1
TOP MARK
(SEE NOTE 5)
0.200 REF
0.00 0.05
(DD10) DFN 0403
0.25
0.05
2.38
0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65
0.05
(2 SIDES)
2.15
0.05
0.50
BSC
0.675
0.05
3.50
0.05
PACKAGE
OUTLINE
0.25
0.05
0.50 BSC
32
LTC2482
2482f
100
METERS
CS
SCK
SDO
F
O
V
CC
5V
LTC2482
REF
GND
C7
0.1
F
C8
1
F
1k
1%
2482 F30
GND
1k
1%
REMOTE
SENSOR
V
IN
+
V
IN
1
F
LINEAR TECHNOLOGY CORPORATION 2005
LT/TP 0405 500 PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
PART NUMBER
DESCRIPTION
COMMENTS
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5
V Offset, 1.6V
P-P
Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/
C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/
C Max Drift
LTC2400
24-Bit, No Latency
ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200
A
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency
ADCs in MSOP
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200
A
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency
ADCs
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200
A
with Differential Inputs
LTC2410
24-Bit, No Latency
ADC with Differential Inputs
0.8
V
RMS
Noise, 2ppm INL
LTC2411/LTC2411-1 24-Bit, No Latency
ADCs with Differential Inputs in MSOP
1.45
V
RMS
Noise, 4ppm INL,
Simultaneous 50Hz/60Hz Rejection (LTC2411-1)
LTC2413
24-Bit, No Latency
ADC with Differential Inputs
Simultaneous 50Hz/60Hz Rejection, 800nV
RMS
Noise
LTC2415/
24-Bit, No Latency
ADCs with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2415-1
LTC2414/LTC2418
8-/16-Channel 24-Bit, No Latency
ADCs
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200
A
LTC2420
20-Bit, No Latency
ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2430/LTC2431
20-Bit, No Latency
ADCs with Differential Inputs
2.8
V Noise, SSOP-16/MSOP Package
LTC2435/LTC2435-1 20-Bit, No Latency
ADCs with 15Hz Output Rate
3ppm INL, Simultaneous 50Hz/60Hz Rejection
LTC2440
High Speed, Low Noise 24-Bit
ADC
3.5kHz Output Rate, 200mV Noise, 24.6 ENOBs
LTC2480
16-Bit, No Latency
ADC with PGA and Temperature Sensor
Pin Compatible with LTC2482
LTC2484
16-Bit, No Latency
ADC with Temperature Sensor
Pin Compatible with LTC2482
RELATED PARTS
TYPICAL APPLICATIO
U
Figure 30. Differential Input Current Cancellation Enables Direct Digitization of Remote Sensors
Figure 31. Input Current Cancellation Enables Precise DC
Measurements Under Extreme Conditions
Figure 32. Input Current Cancellation Enables Low Noise/
Low Offset Measurements under Extreme Conditions
INPUT VOLTAGE (V)
0
INL (LSB)
5
4
3
2
1
0
1
2
3
4
5
2
2482 F31
0.5
1
1.5
2.5
INTEGRAL NONLINEARITY
THROUGH 100 METERS OF
WIRE AND A 1k
, 1F RC
NETWORK
OUTPUT READING (
V)
5.25
NUMBER OF READINGS (%)
8
10
12
3.45
2.25
2482 F32
6
4
4.65 4.05
2.85
1.65
2
0
RMS NOISE = 630nV
AVERAGE = 3.5
V
2500 CONSECUTIVE
READINGS
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