LTC3414
1
sn 3414 3414is
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Final Electrical Specifications
s
Point-of-Load Regulation
s
Notebook Computers
s
Portable Instruments
s
Distributed Power Systems
s
High Efficiency: Up to 95%
s
4A Output Current
s
Low Quiescent Current: 64
A
s
Low R
DS(ON)
Internal Switch: 67m
s
Programmable Frequency: 300KHz to 4MHz
s
2.25V to 5.5V Input Voltage Range
s
2% Output Voltage Accuracy
s
0.8V Reference Allows Low Output Voltage
s
Selectable Forced Continuous/Burst Mode
operation
with Adjustable Burst Clamp
s
Synchronizable Switching Frequency
s
Low Dropout Operation: 100% Duty Cycle
s
Power Good Output Voltage Monitor
s
Overtemperature Protected
s
Available in 20-Lead Exposed TSSOP Package
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
4A, 4MHz, Monolithic
Synchronous Step-Down Regulator
May 2003
The LTC
3414 is a high efficiency monolithic synchro-
nous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.25V to 5.5V and provides a
regulated output voltage from 0.8V to 5V while delivering
up to 4A of output current. The internal synchronous
power switch with 67m
on-resistance increases effi-
ciency and eliminates the need for an external Schottky
diode. Switching frequency is set by an external resistor or
can be synchronized to an external clock. 100% duty cycle
provides low dropout operation extending battery life in
portable systems. OPTI-LOOP
compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
The LTC3414 can be configured for either Burst Mode
operation or forced continuous operation. Forced continu-
ous operation reduces noise and RF interference while
Burst Mode operation provides high efficiency by reduc-
ing gate charge losses at light loads. In Burst Mode
operation, external control of the burst clamp level allows
the output voltage ripple to be adjusted according to the
requirements of the application.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
3414 F01a
SYNC/MODE
V
FB
PGOOD
SW
PGND
SGND
RT
RUN/SS
I
TH
SV
IN
PV
IN
LTC3414
294k
22
F
C
OUT
*
0.47
H
V
OUT
2.5V AT 4A
V
IN
2.7V TO 5.5V
1000pF
2.2M
470pF
R
ITH
*
75k
110k
392k
*BURST MODE OPERATION: C
OUT
= 470
F SANYO POSCAP 4TPB470M, R
ITH
= 20k
FORCED CONTINUOUS: C
OUT
= (2) 100
F TDKC4532X5ROJ107M, R
ITH
= 12.1k
LTC3414 Efficiency Curve
Figure 1. 2.5V/4A Step-Down Regulator
LOAD CURRENT (A)
EFFICIENCY (%)
100
95
90
85
80
75
70
65
60
55
50
0.001
0.100
1.000
10.000
3414 G12
0.010
BURST MODE OPERATION
FORCED
CONTINUOUS
LTC3414
2
sn 3414 3414is
Input Supply Voltage ................................... 0.3V to 6V
I
TH
, RUN/SS, V
FB
,
SYNC/MODE Voltages .................................. 0.3 to V
IN
SW Voltages ................................. 0.3V to (V
IN
+ 0.3V)
Peak SW Sink and Source Current ......................... 8.9A
Operating Ambient Temperature Range
(Note 2) .............................................. 40
C to 85
C
Junction Temperature (Notes 5, 6) ....................... 125
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
ORDER PART
NUMBER
(EXPOSED PAD MUST BE SODERED TO PCB)
T
JMAX
= 125
C,
JA
= 38
C/W,
JC
= 10
C/W
LTC3414EFE
ABSOLUTE AXI U
RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
(Note 1)
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3414E is guaranteed to meet performance specifications
from 0
C to 70
C. Specifications over the 40
C to 85
C operating
ambient temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 3: The LTC3414 is tested in a feedback loop that adjusts V
FB
to
achieve a specified error amplifier output voltage (I
TH
).
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
IN
= 3.3V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Input Voltage Range
2.25
5.5
V
I
FB
Feedback Pin Input Current
(Note 3)
0.1
A
V
FB
Regulated Feedback Voltage
(Note 3)
q
0.784
0.800
0.816
V
V
FB
Reference Voltage Line Regulation
V
IN
= 2.7V to 5.5V (Note 3)
q
0.04
0.2
%V
V
LOADREG
Output Voltage Load Regulation
Measured in Servo Loop, V
ITH
= 0.36V
q
0.02
0.2
%
Mesured in Servo Loop, V
ITH
= 0.84V
q
0.02
0.2
%
V
PGOOD
Power Good Range
7.5
9
%
R
PGOOD
Power Good Resistance
120
200
I
Q
Input DC Bias Current
(Note 4)
Active Current
V
FB
= 0.75V, V
ITH
= 1.2V
250
330
A
Sleep
V
FB
= 1V, V
ITH
= 0V, V
SYNC/MODE
= 0V
64
80
A
Shutdown
V
RUN
= 0V
0.02
1
A
f
OSC
Switching Frequency
R
OSC
= 294k
0.88
1.00
1.12
MHz
Switching Frequency Range
0.3
4
MHz
f
SYNC
SYNC Capture Range
0.3
4
MHz
R
PFET
R
DS(ON)
of P-Channel FET
I
SW
= 300mA
67
100
m
R
NFET
R
DS(ON)
of N-Channel FET
I
SW
= 300mA
50
100
m
I
LIMIT
Peak Current Limit
6.4
8
A
V
UVLO
Undervoltage Lockout Threshold
1.75
2.00
2.25
V
I
LSW
SW Leakage Current
V
RUN
= 0V, V
IN
= 5.5V
0.1
1.0
A
V
RUN
RUN Threshold
0.5
0.65
0.8
V
Consult LTC Marketing for parts specified with wider operating temperature ranges.
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
PGND
RT
SYNC/MODE
RUN/SS
SGND
NC
PV
IN
SW
SW
PGND
PGND
V
FB
I
TH
PGOOD
SV
IN
NC
PV
IN
SW
SW
PGND
FE PACKAGE
20-LEAD PLASTIC TSSOP
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
as follows: T
J
=T
A
+ (P
D
)(37.6
C/W)
Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125
C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliabiability.
LTC3414
3
sn 3414 3414is
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
V
REF
vs Temperature, V
IN
= 3.3V
Switch On-Resistance vs
Input Voltage
Switch On-Resistance vs
Temperature, V
IN
= 3.3V
TEMPERATURE (
C)
40
0.795
V
REF
(V)
0.796
0.798
0.799
0.800
0
40
60
140
3414 G01
0.797
20
20
80 100 120
INPUT VOLTAGE (V)
2.25 2.75 3.25
3.75
4.25 4.75
5.25
5.75
ON-RESISTANCE (m
)
90
80
70
60
50
40
30
20
10
0
3414 G02
PFET
NFET
T
A
= 25
C
TEMPERATURE (
C)
40
ON-RESISTANCE (m
)
120
100
80
60
40
20
0
25
3414 G03
10 5 20 35 50 65 80 95 110 125
PFET
NFET
INPUT VOLTAGE (V)
2.25
SWITCH LEAKAGE CURRENT (nA)
20
18
16
14
12
10
8
6
4
2
0
3.25
4.25
4.75
3414 G04
2.75
3.75
5.25
INPUT VOLTAGE (V)
2.25
3.25
4.25
4.75
2.75
3.75
5.25
PFET
NFET
R
OSC
(k)
25
FREQUENCY (kHz)
7000
6000
5000
4000
3000
2000
1000
0
3414 G05
225
925
825
725
625
525
125
325 425
1040
1020
1000
980
960
940
920
900
3414 G06
FREQUENCY (kHz)
TEMPERATURE (
C)
40
60
1090
1070
1050
1030
1010
990
970
950
930
910
3414 G07
20
120
0
20
40
80
100
INPUT VOLTAGE (V)
2.25
350
300
250
200
150
100
50
0
3.75
4.75
3414 G08
2.75
3.25
4.25
5.25
QUIESCENT CURRENT (
A)
BURST CLAMP VOLTAGE (V)
0
MINIMUM PEAK INDUCTOR CURRENT (A)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.2
0.4
0.5
3414 G09
0.1
0.3
0.6
0.7
0.8
FREQUENCY (kHz)
ACTIVE
SLEEP
V
IN
= 3.3V
T
A
= 25
C
V
IN
= 3.3V
T
A
= 25
C
V
IN
= 3.3V
R
OSC
= 294k
R
OSC
= 294k
T
A
= 25
C
T
A
= 25
C
T
A
= 25
C
Frequency vs Temperature
DC Supply Current vs Input
Voltage
Minimum Peak Inductor Current
vs Burst Clamp Voltage
Switch Leakage vs Input Voltage
Frequency vs R
OSC
Frequency vs Input Voltage
LTC3414
4
sn 3414 3414is
LOAD CURRENT (A)
EFFICIENCY (%)
100
95
90
85
80
75
70
65
60
55
50
0.001
0.1
1
10
3414 G10
0.01
LOAD CURRENT (A)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0
0.001
0.1
1
10
0.01
3414 G11
INPUT VOLTAGE (V)
2.5
EFFICIENCY (%)
3.0
3.5
4.0
4.5
3414 G13
5.0
98
96
94
92
90
88
86
84
82
80
78
5.5
LOAD CURRENT (A)
V
OUT
/V
OUT
(%)
3414 G15
0
0.05
0.10
0.15
0.20
0.25
0.30
0
1.0
2.0
2.5
0.5
1.5
3.0
3.5
4.0
FREQUENCY (kHz)
EFFICIENCY (%)
3414 G14
100
95
90
85
80
75
70
300
1300
2300 2800
800
1800
3300 3800
3414 G16
3414 G18
3414 G17
V
IN
= 3.3V
V
IN
= 5V
V
IN
= 3.3V
V
IN
= 5V
I
OUT
= 1A
I
OUT
= 4A
L = 0.47
H
L = 0.2
H
L = 1
H
V
IN
= 3.3V, V
OUT
= 2.5V
LOAD = 250mA
OUTPUT
VOLTAGE
20mV/DIV
INDUCTOR
CURRENT
500mA/DIV
V
IN
= 3.3V, V
OUT
= 2.5V
LOAD STEP = 0A TO 4A
OUTPUT
VOLTAGE
100mV/DIV
INDUCTOR
CURRENT
2A/DIV
V
IN
= 3.3V, V
OUT
= 2.5V
LOAD STEP = 250mA TO 4A
OUTPUT
VOLTAGE
100mV/DIV
INDUCTOR
CURRENT
2A/DIV
LOAD CURRENT (A)
EFFICIENCY (%)
100
95
90
85
80
75
70
65
60
55
50
0.001
0.1
1
10
3414 G12
0.01
Burst Mode OPERATION
FORCED
CONTINUOUS
10
s/DIV
20
s/DIV
20
s/DIV
V
IN
= 3.3V
V
OUT
= 2.5V
V
OUT
= 2.5V
T
A
= 25
C
V
OUT
= 2.5V
T
A
= 25
C
V
IN
= 3.3V
V
OUT
= 2.5V
T
A
= 25
C
V
IN
= 3.3V
V
OUT
= 2.5V
T
A
= 25
C
T
A
= 25
C
T
A
= 25
C
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Efficiency vs Load Current, Burst
Mode Operation
Efficiency vs Input Voltage
Efficiency vs Frequency
Efficiency vs Load Current,
Forced Continuous
Load Regulation
Burst Mode Operation
Load Step Transient Forced
Continuous
Load Step Transient Burst Mode
Operation
Efficiency vs Load Current
LTC3414
5
sn 3414 3414is
PGND (Pins 1, 10, 11, 20): Power Ground. Connect this
pin closely to the () terminal of C
IN
and C
OUT
.
RT (Pin 2): Oscillator Resistor Input. Connecting a resistor
to ground from this pin sets the switching frequency.
SYNC/MODE (Pin 3): Mode Select and External Clock
Synchronization Input. To select Forced Continuous, tie to
SV
IN
. Connecting this pin to a voltage between 0V and 1V
selects Burst Mode operation with the burst clamp set to
the pin voltage.
RUN/SS (Pin 4): Run Control and Soft-Start Input. Forcing
this pin below 0.5V shuts down the LTC3414. In shutdown
all functions are disabled. Less than 1
A of supply current
is consumed. A capacitor to ground from this pin sets the
ramp time to full output current.
SGND (Pin 5):Signal Ground. All small signal components
and compensation components should connect to this
ground, which in turn connects to PGND at one point.
NC (Pin 6): Open. No internal connection.
PV
IN
(Pins 7, 14): Power Input Supply. Decouple this pin
to PGND with a capacitor.
SW (Pins 8, 9, 12, 13): Switch Node Connection to
Inductor. This pin connects to the drains of the internal
main and synchronous power MOSFET switches.
NC (Pin 15): Open. No internal connection.
SV
IN
(Pin 16): Signal Input Supply. Decouple this pin to
SGND with a capacitor.
PGOOD (Pin 17): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within
7.5% of regulation point.
I
TH
(Pin 18): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.2V to
1.4V with 0.4V corresponding to the zero-sense voltage
(zero current).
V
FB
(Pin 19): Feedback Pin. Receives the feedback voltage
from a resistive divider connected across the output.
U
U
U
PI FU CTIO S
Start-Up Transient
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
3414 G19
V
IN
= 3.3V, V
OUT
= 2.5V
LOAD = 4A
OUTPUT
VOLTAGE
INDUCTOR
CURRENT
2A/DIV
V
RUN
1ms/DIV
LTC3414
6
sn 3414 3414is
Main Control Loop
The LTC3414 is a monolithic, constant-frequency, cur-
rent-mode step-down DC/DC converter. During normal
operation, the internal top power switch (P-channel
MOSFET) is turned on at the beginning of each clock cycle.
Current in the inductor increases until the current com-
parator trips and turns off the top power MOSFET. The
peak inductor current at which the current comparator
shuts off the top power switch is controlled by the voltage
on the I
TH
pin. The error amplifier adjusts the voltage on
the I
TH
pin by comparing the feedback signal from a
resistor divider on the V
FB
pin with an internal 0.8V
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the I
TH
voltage until the average
inductor current matches the new load current. When the
top power MOSFET shuts off, the synchronous power
switch (N-channel MOSFET) turns on until either the
bottom current limit is reached or the beginning of the next
clock cycle. The bottom current limit is set at 5A for
forced continuous mode and 0A for Burst Mode operation.
The operating frequency is externally set by an external
resistor connected between the RT pin and ground. The
practical switching frequency can range from 300kHz to
4MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by
7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET's current limit is reached.
Forced Continuous Mode
Connecting the SYNC/MODE pin to SV
IN
will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation, but may be desirable
in some applications where it is necessary to keep switch-
OPERATIO
U
BLOCK DIAGRA
W
+
+
+
+
+
+
+
16
19
17
4
2
5
18
7
14
SLOPE
COMPENSATION
RECOVERY
SLOPE
COMPENSATION
VOLTAGE
REFERENCE
OSCILLATOR
LOGIC
3
0.74V
0.86V
RUN
13
12
9
8
SV
IN
SGND
I
TH
PV
IN
PV
IN
PMOS CURRENT
COMPARATOR
BCLAMP
V
FB
RUN/SS
PGOOD
RT
SYNC/MODE
PGND
PGND
PGND
PGND
CURRENT
REVERSAL
COMPARTOR
NMOS CURRENT
COMPARATOR
BURST
COMPARATOR
ERROR
AMPLIFIER
SW
SW
SW
SW
10
11
20
1
3414 BD
SYNC/MODE
+
V
0.8V
LTC3414
7
sn 3414 3414is
ing harmonics out of a signal band. The output voltage
ripple is minimized in this mode.
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage in the range
of 0V to 1V enables Burst Mode operation. In Burst Mode
operation, the internal power MOSFETs operate intermit-
tently at light loads. This increases efficiency by minimiz-
ing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
voltage on the SYNC/MODE pin and the voltage on the I
TH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the I
TH
pin drops. As the I
TH
voltage falls
below 150mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top power MOSFET is
held off and the I
TH
pin is disconnected from the output of
the error amplifier. The majority of the internal circuitry is
also turned off to reduce the quiescent current to 64
A
while the load current is solely supplied by the output
capacitor. When the output voltage drops, the I
TH
pin is
reconnected to the output of the error amplifier and the top
power MOSFET along with all the internal circuitry is
switched back on. This process repeats at a rate that is
dependent on the load demand.
Pulse Skipping operation is implemented by connecting
the SYNC/MODE pin to ground. This forces the burst
clamp level to be at 0V. As the load current decreases, the
peak inductor current will be determined by the voltage on
the I
TH
pin until the I
TH
voltage drops below 400mV. At this
point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Frequency Synchronization
The internal oscillator of the LTC3414 can be synchronized
to an external clock connected to the SYNC/MODE pin. The
frequency of the external clock can be in the range of
300kHz to 4MHz. For this application, the oscillator timing
resistor should be chosen to correspond to a frequency
that is 25% lower than the synchronization frequency.
During synchronization, the burst clamp is set to 0V, and
each switching cycle begins at the falling edge of the clock
signal.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle eventually reaching 100% duty cycle. The output
voltage will then be determined by the input voltage minus
the voltage drop across the internal P-channel MOSFET
and the inductor.
Low Supply Operation
The LTC3414 is designed to operate down to an input
supply voltage of 2.25V. One important consideration
at low input supply voltages is that the R
DS(ON)
of the
P-channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3414 is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3414, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Short-Circuit Protection
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. To
prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases larger than 7.8A, the top
power MOSFET will be held off and switching cycles will be
skipped until the inductor current is reduced.
OPERATIO
U
LTC3414
8
sn 3414 3414is
The basic LTC3414 application circuit is shown in Figure 1.
External component selection is determined by the maxi-
mum load current and begins with the selection of the
operating frequency and inductor value followed by C
IN
and C
OUT
.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3414 is determined by
an external resistor that is connected between pin R
T
and
ground. The value of the resistor sets the ramp current that
is used to charge and discharge an internal timing capaci-
tor within the oscillator and can be calculated by using the
following equation:
R
f
k
OSC
=
( )
3 08 10
10
11
.
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3414 imposes a minimum
limit on the operating duty cycle. The minimum on-time is
typically 110ns; therefore, the minimum duty cycle is
equal to 100 110ns f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current
I
L
increases with higher V
IN
or V
OUT
and
decreases with higher inductance.
=
I
V
f
V
V
L
OUT
L
OUT
IN
1
Having a lower ripple current reduces the core losses in
the inductor, the ESR losses in the output capacitors, and
the output voltage ripple. Highest efficiency operation is
achieved at low frequency with small ripple current. This,
however, requires a large inductor.
A reasonable starting point for selecting the ripple current
is
I
L
= 0.4(I
MAX
). The largest ripple current occurs at the
highest V
IN
. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
L
V
f I
V
V
OUT
L MAX
OUT
IN MAX
=
(
)
(
)
1
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by
the burst clamp. Lower inductor values result in higher
ripple current which causes this to occur at lower load
currents. This causes a dip in efficiency in the upper range
of low current operation. In Burst Mode operation, lower
inductance values will cause the burst frequency to in-
crease.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates "hard," which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don't radiate much energy, but gener-
ally cost more than powdered iron core inductors with
similar characteristics. The choice of which style inductor
to use mainly depends on the price verus size require-
ments and any radiated field/EMI requirements. New
designs for surface mount inductors are available from
Coiltronics, Coilcraft, Toko, and Sumida.
APPLICATIO S I FOR ATIO
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LTC3414
9
sn 3414 3414is
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the trapezoi-
dal wave current at the source of the top MOSFET. To
prevent large voltage transients from occurring, a low ESR
input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
I
I
V
V
V
V
RMS
OUT MAX
OUT
IN
IN
OUT
=
(
)
1
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT/2
. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design. For low input voltage applications, sufficient
bulk input capacitance is needed to minimize transient
effects during output load changes.
The selection of C
OUT
is determined by the effective series
resistance (ESR) that is required to minimize voltage
ripple and load step transients as well as the amount of
bulk capacitance that is necessary to ensure that the
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple,
V
OUT
, is determined by:
+
V
I ESR
fC
OUT
L
OUT
1
8
The output ripple is highest at maximum input voltage
since
I
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and RMS
current handling requirements. Dry tantalum, special poly-
mer, aluminum electrolytic, and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capaci-
tors have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
V
IN
. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at V
IN
large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
V
V
R
R
OUT
=
+
0 8
1
2
1
.
The resistive divider allows pin V
FB
to sense a fraction of
the output voltage as shown in Figure 2.
APPLICATIO S I FOR ATIO
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LTC3414
V
FB
SGND
V
OUT
R2
R1
Figure 2. Setting the Output Voltage
LTC3414
10
sn 3414 3414is
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than V
IN
by 1V,
Burst Mode operation is enabled. During Burst Mode
Operation, the voltage on the SYNC/MODE pin determines
the burst clamp level, which sets the minimum peak
inductor current, I
BURST
, for each switching cycle accord-
ing to the following equation:
I
A
V
V
V
BURST
BURST
=
(
)
6 9
0 6
0 383
.
.
.
V
BURST
is the voltage on the SYNC/MODE pin. I
BURST
can
only be programmed in the range of 0A to 7A. For values
of V
BURST
greater than 1V, I
BURST
is set at 7A. For values
of V
BURST
less than 0.4V, I
BURST
is set at 0A. As the output
load current drops, the peak inductor currents decrease to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than I
BURST
, the burst clamp will force the peak inductor
current to remain equal to I
BURST
regardless of further
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
on the I
TH
pin will decrease. When the I
TH
voltage drops
to 150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
I
BURST
is determined by the desired amount of output
voltage ripple. As the value of I
BURST
increases, the sleep
period between pulses and the output voltage ripple in-
crease. The burst clamp voltage, V
BURST
, can be set by a
resistor divider from the V
FB
pin to the SGND pin as shown
in Figure 1.
Pulse skipping, which is a compromise between low
output voltage ripple and efficiency, can be implemented
by connecting pin SYNC/MODEto ground. This sets I
BURST
to 0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator. The
lowest output voltage ripple is achieved while still operat-
ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3414's internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set
by the external resistor. Because slope compensation is
generated by the oscillator's RC circuit, the external
frequency should be set 25% higher than the frequency
set by the external resistor to ensure that adequate slope
compensation is present.
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3414 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3414 in a low
quiescent current shutdown state (I
Q
< 1
A).
The LTC3414 contains an internal soft-start clamp that
gradually raises the clamp on I
TH
after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on I
TH
after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on I
TH
can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
t
R
C
V
V
V
SECONDS
SS
SS
SS
IN
IN
=
ln
.
(
)
1 8
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
IN
quiescent current and I
2
R losses.
APPLICATIO S I FOR ATIO
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LTC3414
11
sn 3414 3414is
The V
IN
quiescent current loss dominates the efficiency
loss at very low load currents whereas the I
2
R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current out
of V
IN
that is typically larger than the DC bias current. In
continuous mode, I
GATECHG
= f(QT + QB) where QT and QB
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V
IN
; thus, their effects will be more pro-
nounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In con-
tinuous mode the average output current flowing through
inductor L is "chopped" between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)
TOP)(DC) + (R
DS(ON)
BOT)(1 DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. To obtain I
2
R losses, simply add R
SW
to R
L
and
multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3414 does not dissipate
much heat due to its high efficiency.
However, in applications where the LTC3414 is running at
high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
150
C, both power switches will be turned off and the SW
node will become high impedance.
To avoid the LTC3414 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
t
r
= (P
D
)(
JA
)
where P
D
is the power dissipated by the regulator and
JA
is the thermal resistance from the junction of the die to the
ambient temperature. For the 20-lead exposed TSSOP
package, the
JA
is 38
C/W.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ t
r
where T
A
is the ambient temperature.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
To maximize the thermal performance of the LTC3414, the
exposed pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current.
When a load step occurs, V
OUT
immediately shifts by an
amount equal to
I
LOAD(ESR)
, where ESR is the effective
series resistance of C
OUT
.
I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components and output capaci-
tor shown in Figure 1 will provide adequate compensation
for most applications.
APPLICATIO S I FOR ATIO
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Design Example
As a design example, consider using the LTC3414 in an
application with the following specifications:
V
IN
= 2.7V to 4.2V, V
OUT
= 2.5V, I
OUT(MAX)
= 4A,
I
OUT(MIN)
= 100mA, f = 1MHz.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
R
k
k
OSC
=
=
3 08 10
1 10
10
298
11
6
.
Use a standard value of 294k. Next, calculate the inductor
value for about 40% ripple current at maximum V
IN
:
L
V
MHz
A
V
V
H
=
=
2 5
1
1 6
1
2 5
4 2
0 63
.
(
)( .
)
.
.
.
Using a 0.47
H inductor results in a maximum ripple
current of:
=
=
I
V
MHz
H
V
V
A
L
2 5
1
0 47
1
2 5
4 2
2 15
.
(
)( .
)
.
.
.
C
OUT
will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
22
F ceramic capacitor and a 470
F tantalum capacitor
will be used.
C
IN
should be sized for a maximum current rating of:
I
A
V
V
V
V
A
RMS
RMS
=
=
(
)
.
.
.
.
.
4
2 5
4 2
4 2
2 5
1 1 96
Decoupling the PV
IN
and SV
IN
pins with two 22
F capaci-
tors and a 330
F tantalum capacitor is adequate for most
applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2, and R3. The
voltage on pin MODE will be set to 0.49V by the resistor
divider consisting of R2 and R3. A burst clamp voltage of
0.49V will set the minimum inductor current, I
BURST
, as
follows:
I
V
V
A
V
A
BURST
BURST
=
(
)
=
.
.
.
.
0 383
6 9
0 6
1 23
If we set the sum of R2 and R3 to 200k, then the following
equations can be solved:
R
R
k
R
R
V
V
2
3
200
1
2
3
0 8
0 49
+
=
+
=
.
.
The two equations shown above result in the following
values for R2 and R3: R2 = 78.7k , R3 = 124k. The value
of R1 can now be determined by solving the following
equation.
1
1
202 7
2 5
0 8
1 432
+
=
=
R
k
V
V
R
k
.
.
.
A value of 432k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3414. Check the following in your layout:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3414.
2. Connect the (+) terminal of the input capacitor(s), C
IN
,
as close as possible to the PV
IN
pin. This capacitor
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small signal nodes.
4. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. You can connect the copper areas to
any DC net (PV
IN
, SV
IN
, V
OUT
, PGND, SGND, or any other
DC rail in your system).
5. Connect the V
FB
pin directly to the feedback resistors.
The resistor divider must be connected between V
OUT
and SGND.
APPLICATIO S I FOR ATIO
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LTC3414
13
sn 3414 3414is
3413 F04
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
C
ITH
470pF
X7R
C
SS
1000pF
X7R
R
SS
2.2M
R
OSC
294k
R
ITH
20k
RPG
100k
C1
10pF
X7R
R3
124k
R2
78.7k
PGND
RT
SYNC/MODE
RUN/SS
SGND
NC
PV
IN
SW
SW
PGND
PGND
V
FB
I
TH
PGOOD
SV
IN
NC
PV
IN
SW
SW
PGND
LTC3414
C
OUT1
**
470
F
C
OUT2
22
F
X5R
L1*
0.47
H
C
IN1
22
F
X5R
2X
C
IN2
***
330
F
R1
432k
V
OUT
2.5V
4A
V
IN
2.7V TO 5V
PGOOD
*
**
***
VISHAY DALE IHLP-2525CZ-01
SANYO POSCAP 4TPD470M
SANYO POSCAP 6TPB330M
+
+
Figure 4. 2.5V, 4A Regulator at 1MHz, Burst Mode Operation
APPLICATIO S I FOR ATIO
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Figure 3. LTC3414 Layout Diagram
Top
Bottom
LTC3414
14
sn 3414 3414is
3413 F06
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
C
ITH
470pF
X7R
C
SS
1000pF
X7R
R
SS
2.2M
R
OSC
294k
R
ITH
12.1k
RPG
100k
C
C
100pF
X7R
R2
200k
PGND
RT
SYNC/MODE
RUN/SS
SGND
NC
PV
IN
SW
SW
PGND
PGND
V
FB
I
TH
PGOOD
SV
IN
NC
PV
IN
SW
SW
PGND
LTC3414
C
OUT
**
100
F
2x
L1*
0.47
H
C
IN1
**
100
F
2x
C
IN2
***
220
F
C1
22pF
X7R
R1
422k
V
OUT
2.5V
4A
V
IN
3.3V
PGOOD
*
**
***
VISHAY DALE IHLP-2525CZ-01
TDK C4532X5ROJ107M
SANYO POSCAP 4TPB220M
1.25MHz
CLOCK
+
Figure 5. 3.3V, 2.5A Step-Down Regulator at 1MHz, Forced Continuous
3413 F05
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
C
ITH
470pF
X7R
C
SS
1000pF
X7R
R
SS
2.2M
R
OSC
294k
R
ITH
12.1k
RPG
100k
C
C
100pF
X7R
R2
200k
PGND
RT
SYNC/MODE
RUN/SS
SGND
NC
PV
IN
SW
SW
PGND
PGND
V
FB
I
TH
PGOOD
SV
IN
NC
PV
IN
SW
SW
PGND
LTC3414
C
OUT
**
100
F
2x
L1*
0.68
H
C
IN1
22
F
X5R
2x
C
IN2
***
150
F
C1
22pF
X7R
R1
634k
V
OUT
3.3V
4A
V
IN
5V
PGOOD
*
**
***
MURATA LQH66SNR68M03L
TDK C4532X5ROJ107M
SANYO POSCAP 6TPE150M
+
APPLICATIO S I FOR ATIO
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Figure 6. 2.5V, 2.5A Step-Down Regulator at 1.25MHz, Synchronized to External Clock
LTC3414
15
sn 3414 3414is
PACKAGE DESCRIPTIO
U
FE20 (CA) TSSOP 0203
0.09 0.20
(.0036 .0079)
0
8
RECOMMENDED SOLDER PAD LAYOUT
0.45 0.75
(.018 .030)
4.30 4.50*
(.169 .177)
6.40
BSC
1
3
4
5
6 7 8
9 10
11
12
14 13
6.40 6.60*
(.252 .260)
4.95
(.195)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 0.15
(.002 .006)
0.65
(.0256)
BSC
0.195 0.30
(.0077 .0118)
2
2.74
(.108)
0.45
0.05
0.65 BSC
4.50
0.10
6.60
0.10
1.05
0.10
4.95
(.195)
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
LTC3414
16
sn 3414 3414is
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
LT/TP 0503 1.5K PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATIO
U
3413 TA01
1
2
3
4
5
20
19
18
17
16
C
ITH
470pF
X7R
C
SS
1000pF, X7R
R
SS
2.2M
R
OSC
294k
R
ITH
15k
RPG
100k
C
C
100pF
X7R
R2
200k
PGND
RT
SYNC/MODE
RUN/SS
SGND
PGND
V
FB
I
TH
PGOOD
SV
IN
LTC3414
C
OUT1
**
470
F
C
OUT2
22
F
X5R
L1*
0.44
H
C
IN1
22
F
X5R
2x
C
IN2
**
470
F
C1
39pF
X7R
R1
178k
V
OUT
1.5V
4A
V
IN
2.5V
PGOOD
*
**
PULSE P1166.68IT
SANYO POSCAP 4TPD470M
6
7
8
9
10
NC
PV
IN
SW
SW
PGND
15
14
13
12
11
NC
PV
IN
SW
SW
PGND
+
+
PART NUMBER
DESCRIPTION
COMMENTS
LT1616
500mA (I
OUT
), 1.4MHz, High Efficiency Step-Down
90% Efficiency, V
IN
= 3.6V to 25V, V
OUT
= 1.25V,
DC/DC Converter
I
Q
= 1.9mA, I
SD
= <1
A, ThinSOT Package
LT1676
450mA (I
OUT
), 100kHz, High Efficiency Step-Down
90% Efficiency, V
IN
= 7.4V to 60V, V
OUT
= 1.24V,
DC/DC Converter
I
Q
= 3.2mA, I
SD
= 2.5
A, S8 Package
LT1765
25V, 2.75A (I
OUT
), 1.25MHz, High Efficiency Step-Down
90% Efficiency, V
IN
= 3V to 25V, V
OUT
= 1.2V,
DC/DC Converter
I
Q
= 1mA, I
SD
= 15
A, S8, TSSOP16E Packages
LT1776
500mA (I
OUT
), 200kHz, High Efficiency Step-Down
90% Efficiency, V
IN
= 7.4V to 40V, V
OUT
= 1.24V,
DC/DC Converter
I
Q
= 3.2mA, I
SD
= 30
A, N8, S8 Packages
LTC1879
1.20A (I
OUT
), 550kHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.7V to 10V, V
OUT
= 0.8V,
DC/DC Converter
I
Q
= 15
A, I
SD
= <1
A, TSSOP16 Package
LTC3405/LTC3405A
300mA (I
OUT
), 1.5MHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.75V to 6V, V
OUT
= 0.8V,
DC/DC Converter
I
Q
= 20
A, I
SD
= <1
A, ThinSOT Package
LTC3406/LTC3406B
600mA (I
OUT
), 1.5MHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.5V to 5.5V, V
OUT
= 0.6V,
DC/DC Converter
I
Q
= 20
A, I
SD
= <1
A, ThinSOT Package
LTC3411
1.25A (I
OUT
), 4MHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.5V to 5.5V, V
OUT
= 0.8V,
DC/DC Converter
I
Q
= 60
A, I
SD
= <1
A, MS Package
LTC3412
2.5A (I
OUT
), 4MHz, Synchronous Step-Down
95% Efficiency, V
IN
= 2.5V to 5.5V, V
OUT
= 0.8V
DC/DC Converter
I
Q
= 60
A, I
SD
= <1
A, TSSOP16E Package
LTC3413
3A (I
OUT
Sink/source), 2MHz, Monolithic Synchronous
90% Efficiency, V
IN
= 2.25V to 5.5V, V
OUT
= V
REF
/2,
Regulator for DDR/QDR Memory Termination
I
Q
= 280
A, I
SD
= <1
A, TSSOP16E Package
LTC3430
60V, 2.75A (I
OUT
), 200kHz, High Efficiency Step-Down
90% Efficiency, V
IN
= 5.5V to 60V, V
OUT
= 1.2V,
DC/DC Converter
I
Q
= 2.5mA, I
SD
= 25
A, TSSOP16E Package
LTC3440
600mA (I
OUT
), 2MHz, Synchronous Buck-Boost
95% Efficiency, V
IN
= 2.5V to 5.5V, V
OUT
= 2.5V,
DC/DC Converter
I
Q
= 25
A, I
SD
= <1
A, MS Package
1.5V, 4A Step-Down Regulator at 1MHz, Burst Mode
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