LTC4006

4006i

4A, High Efficiency,

Standalone Li-Ion Battery Charger

May 2003

Complete Charger Controller for 2-, 3- or 4-Cell
Lithium-Ion Batteries

High Conversion Efficiency: Up to 96%

Output Currents Exceeding 4A

0.8% Accurate Preset Voltages: 8.4V, 12.6V, 16.8V

Built-In Charge Termination with Automatic Restart

AC Adapter Current Limiting Maximizes Charge Rate*

Automatic Conditioning of Deeply Discharged
Batteries

Thermistor Input for Temperature Qualified Charging

Wide Input Voltage Range: 6V to 28V

0.5V Dropout Voltage; Maximum Duty Cycle: 98%

Programmable Charge Current:

5% Accuracy

Indicator Outputs for Charging, C/10 Current
Detection and AC Adapter Present

Charging Current Monitor Output

16-Pin Narrow SSOP Package

Notebook Computers

Portable Instruments

Battery-Backup Systems

Standalone Li-Ion Chargers

, LTC and LT are registered trademarks of Linear Technology Corporation.

APPLICATIO S

Final Electrical Specifications

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

4A Li-Ion Battery Charger

The LTC

4006 is a complete constant-current/constant-

voltage charger controller for 2-, 3- or 4-cell lithium bat-
teries in a small package using few external components.
The PWM controller is a synchronous, quasi-constant fre-
quency, constant off-time architecture that will not gener-
ate audible noise even when using ceramic capacitors.

The LTC4006 is available in 8.4V, 12.6V and 16.8V versions
with

0.8% accuracy. Charging current is programmable

with a single sense resistor to

4% typical accuracy. Charg-

ing current can be monitored as a representative voltage at
the I

MON

pin. A timer, programmed by an external resistor,

sets the total charge time or is reset to 25% of total charge
time after C/10 charging current is reached. Charging au-
tomatically resumes when cell voltage falls below 3.9V/cell.

Fully discharged cells are automatically trickle charged at
10% of the programmed current until the cell voltage ex-
ceeds 2.5V/cell. Charging terminates if the low-battery
condition persists for more than 25% of the total charge
time.

LTC4006 includes a thermistor sensor input that sus-
pends charging if an unsafe temperature condition is
detected and automatically resumes charging when bat-
tery temperature returns to within safe limits.

DCIN

CHG

ACP/SHDN

MON

NTC

GND

CHG

ACP

INFET

CLP

CLN

TGATE

BGATE

PGND

CSP

BAT

LTC4006

0.12

THERMISTOR

10k

NTC

309k

TIMING

RESISTOR

(~2 HOURS)

0.0047

0.47

32.4k

CHARGING

CURRENT MONITOR

100k

LOGIC

DCIN

0V TO 28V

INPUT SWITCH

0.1

15nF

0.025

0.033

BATTERY

4006 TA01

FEATURES

DESCRIPTIO

TYPICAL APPLICATIO

*U.S. Patent No. 5,723,970

LTC4006

4006i

(Note 1)

Voltage from DCIN, CLP, CLN, TGATE, INFET,
ACP/SHDN, CHG to GND ........................... + 32V/ 0.3V
CSP, BAT to GND ....................................... +28V/ 0.3V
R

to GND ..................................................... +7V/ 0.3V

NTC ............................................................ +10V/ 0.3V
Operating Ambient Temperature Range

(Note 4) ............................................. 40

C to 85

Operating Junction Temperature ......... 40

C to 125

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

ABSOLUTE

AXI

RATINGS

PACKAGE/ORDER I

FOR

ATIO

ORDER PART

NUMBER

LTC4006EGN-2
LTC4006EGN-4
LTC4006EGN-6

JMAX

= 125

= 110

C/W

The

denotes specifications which apply over the full operating

temperature range (Note 4), otherwise specifications are at T

= 25

C. V

DCIN

= 20V, V

BAT

= 12V unless otherwise noted.

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

GN PART MARKING

GN PACKAGE

16-LEAD PLASTIC SSOP

TOP VIEW

DCIN

CHG

ACP/SHDN

GND

NTC

MON

INFET

BGATE

PGND

TGATE

CLN

CLP

BAT

CSP

40062
40064
40066

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DCIN Operating Range

DCIN

DCIN Operating Current

Sum of Current from CLP, CLN, DCIN

TOL

Voltage Accuracy

(Note 2)
LTC4006-6

8.333

8.4

8.467

LTC4006-6

8.316

8.4

8.484

LTC4006-2

12.499

12.6

12.700

LTC4006-2

12.474

12.6

12.726

LTC4006-4

16.665

16.8

16.935

LTC4006-4

16.632

16.8

16.968

TOL

Current Accuracy (Note 3)

CSP

BAT

Target = 100mV

BAT

= 11.5V (LTC4006-2)

BAT

= 7.6V (LTC4006-6)

BAT

= 12V (LTC4006-4)

BAT

< 6V, V

CSP

BAT

Target = 10mV

BAT

LOBAT

CSP

BAT

Target = 10mV

TOL

Termination Timer Accuracy

= 270k

Shutdown

Battery Leakage Current

DCIN = 0V

DCIN = 20V, V

SHDN

= 0V

UVLO

Undervoltage Lockout Threshold

DCIN Rising, V

BAT

= 0V

4.2

4.7

5.5

Shutdown Threshold at ACP/SHDN

2.5

DCIN Current in Shutdown

SHDN

= 0V, Sum of Current from CLP,

CLN, DCIN

Current Sense Amplifier, CA1

Input Bias Current Into BAT Pin

11.67

CMSL

CA1/I

Input Common Mode Low

CMSH

CA1/I

Input Common Mode High

CLN

0.2

LTC4006

4006i

The

denotes specifications which apply over the full operating

temperature range (Note 4), otherwise specifications are at T

= 25

C. V

DCIN

= 20V, V

BAT

= 12V unless otherwise noted.

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Current Comparators I

CMP

and I

REV

TMAX

Maximum Current Sense Threshold (V

CSP

BAT

)

ITH

= 2.4V

140

165

200

TREV

Reverse Current Threshold (V

CSP

BAT

)

Current Sense Amplifier, CA2

Transconductance

mmho

Source Current

Measured at I

, V

ITH

= 1.4V

Sink Current

Measured at I

, V

ITH

= 1.4V

Current Limit Amplifier

Transconductance

1.5

mmho

CLP

Current Limit Threshold

100

107

CLP

CLP Input Bias Current

100

Voltage Error Amplifier, EA

Transconductance

mmho

Sink Current

Measured at I

, V

ITH

= 1.4V

OVSD

Overvoltage Shutdown Threshold as a Percent

102

107

110

of Programmed Charger Voltage

Input P-Channel FET Driver (INFET)

DCIN Detection Threshold (V

DCIN

CLN

)

DCIN Voltage Ramping Up

0.17

0.25

from V

CLN

0.1V

Forward Regulation Voltage (V

DCIN

CLN

)

Reverse Voltage Turn-Off Voltage (V

DCIN

CLN

)

DCIN Voltage Ramping Down

INFET "On" Clamping Voltage (V

DCIN

INFET

)

INFET

= 1

5.8

6.5

INFET "Off" Clamping Voltage (V

DCIN

INFET

)

INFET

= 25

0.25

Thermistor

NTCVR

Reference Voltage During Sample Time

4.5

High Threshold

NTC

Rising

NTCVR

· 0.48

· 0.5

· 0.52

Low Threshold

NTC

Falling

NTCVR

· 0.115

· 0.125

· 0.135

Thermistor Disable Current

NTC

10V

Indicator Outputs (ACP/SHDN, CHG)

C10TOL

C/10 Indicator Accuracy

Voltage Falling at PROG

0.375

0.400

0.425

LBTOL

LOBAT Threshold Accuracy

LTC4006-6

4.70

4.93

5.10

LTC4006-2

7.27

7.5

7.71

LTC4006-4

9.70

10.28

RESTART Threshold Accuracy

LTC4006-6

7.5

7.7

7.9

LTC4006-2

11.35

11.7

11.94

LTC4006-4

15.15

15.6

15.92

Low Logic Level of ACP/SHDN, CHG

= 100

0.5

High Logic Level of ACP/SHDN

= 1

2.7

Pull-Up Current on ACP/SHDN

V = 0V

IC10

C/10 Indicator Sink Current from CHG

= 3V

OFF

Off State Leakage Current of CHG

= 3V

Timer Defeat Threshold at CHG

LTC4006

4006i

The

denotes specifications which apply over the full operating

temperature range (Note 4), otherwise specifications are at T

= 25

C. V

DCIN

= 20V, V

BAT

= 12V unless otherwise noted.

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: See Test Circuit

Note 3: Does not include tolerance of current sense resistor.

Note 4: The LTC4006E is guaranteed to meet performance specifications
from 0

C to 70

C. Specifications over the 40

C to 85

C operating

temperature range are assured by design, characterization and correlation
with statistical process controls.

ELECTRICAL CHARACTERISTICS

PI FU CTIO S

DCIN (Pin 1): External DC Power Source Input. Bypass
this pin with at least 0.01

F. See Applications Information

section.

CHG (Pin 2): Open-Drain Charge Status Output. When the
battery is being charged, the CHG pin is pulled low by an
internal N-channel MOSFET. When the charge current
drops below 10% of programmed current, the N-channel
MOSFET turns off and a 25

A current source is connected

from the CHG pin to GND. When the timer runs out or the
input supply is removed, the current source will be discon-
nected and the CHG pin is forced into a high impedance
state. A pull-up resistor is required. The timer function is
defeated by forcing this pin below 1V (or connecting it to
GND).

ACP/SHDN (Pin 3): Open-Drain Output Used to Indicate if
the AC Adapter Voltage is Adequate for Charging. Active
high digital output. Internal 10

A pull-up to 3.5V. The

charger can also be inhibited by pulling this pin below 1V.
Reset the charger by pulsing the pin low for a minimum of
0.1

(Pin 4): Timer Resistor. The timer period is set by

placing a resistor, R

, to GND.

The timer period is t

TIMER

= (1hour · R

/154k)

If this resistor is not present, the charger will not start.

GND (Pin 5): Ground for Low Power Circuitry.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Oscillator

OSC

Regulator Switching Frequency

255

300

345

kHz

MIN

Regulator Switching Frequency in Drop Out

Duty Cycle

98%

kHz

MAX

Regulator Maximum Duty Cycle

CSP

= V

BAT

Gate Drivers (TGATE, BGATE)

TGATE

High (V

CLN

TGATE

)

TGATE

= 1mA

BGATE

High

LOAD

= 3000pF

4.5

5.6

TGATE

Low (V

CLN

TGATE

)

LOAD

= 3000pF

4.5

5.6

BGATE

Low

BGATE

= 1mA

TGATE Transition Time

TGTR

TGATE Rise Time

LOAD

= 3000pF, 10% to 90%

110

TGTF

TGATE Fall Time

LOAD

= 3000pF, 10% to 90%

100

BGATE Transition Time

BGTR

BGATE Rise Time

LOAD

= 3000pF, 10% to 90%

BGTF

BGATE Fall Time

LOAD

= 3000pF, 10% to 90%

TGATE

at Shutdown (V

CLN

TGATE

)

TGATE

= 1

A, DCIN = 0V, CLN = 12V

100

BGATE

at Shutdown

BGATE

= 1

A, DCIN = 0V, CLN = 12V

100

LTC4006

4006i

PI FU CTIO S

NTC (Pin 6): A thermistor network is connected from NTC
to GND. This pin determines if the battery temperature is
safe for charging. The charger and timer are suspended if
the thermistor indicates a temperature that is unsafe for
charging. The thermistor function may be disabled with a
300k to 500k resistor from DCIN to NTC.

(Pin 7): Control Signal of the Inner Loop of the Current

Mode PWM. Higher I

voltage corresponds to higher

charging current in normal operation. A 6.04k resistor, in
series with a capacitor of at least 0.1

F to GND, provides

loop compensation. Typical full-scale output current is
40

A. Nominal voltage range for this pin is 0V to 3V.

MON

(Pin 8): Current Monitoring Output. The voltage at

this pin provides a linear indication of charging current.
Peak current is equivalent to 1.19V. Zero current is ap-
proximately 0.309V. A capacitor from I

MON

to ground is

required to filter higher frequency components. If V

BAT

2.5V/cell, then I

MON

= 1.19V when conditioning a depleted

battery.

CSP (Pin 9): Current Amplifier CA1 Input. This pin and the
BAT pin measure the voltage across the sense resistor,
R

SENSE

, to provide the instantaneous current signals re-

quired for both peak and average current mode operation.

BAT (Pin 10): Battery Sense Input and the Negative
Reference for the Current Sense Resistor. A precision
internal resistor divider sets the final float potential on this
pin. The resistor divider is disconnected during shutdown.

CLP (Pin 11): Positive Input to the Supply Current Limiting
Amplifier, CL1. The threshold is set at 100mV above the
voltage at the CLN pin. When used to limit supply current,
a filter is needed to filter out the switching noise. If no
current limit function is desired, connect this pin to CLN.

CLN (Pin 12): Negative Reference for the Input Current
Limit Amplifier, CL1. This pin also serves as the power
supply for the IC. A 10

F to 22

F bypass capacitor should

be connected as close as possible to this pin.

TGATE (Pin 13): Drives the top external P-channel MOSFET
of the battery charger buck converter.

PGND (Pin 14): High Current Ground Return for the BGATE
Driver.

BGATE (Pin 15): Drives the bottom external N-channel
MOSFET of the battery charger buck converter.

INFET (Pin 16): Drives the Gate of the External Input PFET.

TEST CIRCUIT

LT1055

LTC4006

REF

11.67

BAT

0.6V

4006 TC

35mV

LTC4006

4006i

BLOCK DIAGRA

1.19V

11.67

35mV

C/10

BAD

= 1m

1.19V

GND

TGATE

BGATE

CLP

100mV

15nF

5.1k

CLN

PGND

397mV

CHG

LOGIC

NTC

0.47

10k
NTC

CL1

= 1.5m

TIMER/CONTROLLER

THERMISTOR

OSCILLATOR

BAT

SENSE

CSP

32.4k

100k

WATCH DOG

DETECT t

OFF

DCIN

OSCILLATOR

1.28V

PWM

LOGIC

CHARGE

REV

CMP

BUFFERED I

0.01

MON

4006 BD

4.7nF

IMON1

26.44k

IMON2

52.87k

17mV

ACP/SHDN 3

INFET

DCIN

5.8V

CLN

6.04k

0.12

CA2

CA1

RESTART

LOBAT

1.105V

708mV

OPERATIO

Overview

The LTC4006 is a synchronous current mode PWM step-
down (buck) switcher battery charger controller. The charge
current is programmed by the sense resistor (R

SENSE

)

between the CSP and BAT pins. The final float voltage is
internally programmed to 8.4V (LTC4006-6), 12.6V

(LTC4006-2) or 16.8V (LTC4006-4) with better than

0.8%

accuracy. Charging begins when the potential at the DCIN
pin rises above the voltage at CLN (and the UVLO voltage)
and the ACP/SHDN pin is allowed to go high; the CHG pin
is set low. At the beginning of the charge cycle, if the cell
voltage is below 2.5V, the charger will trickle charge the
battery with 10% of the maximum programmed current.

LTC4006

4006i

OPERATIO

If the cell voltage stays below 2.5V for 25% of the total
charge time, the charge sequence will be terminated im-
mediately and the CHG pin will be set to a high impedance.

An external thermistor network is sampled at regular
intervals. If the thermistor value exceeds design limits,
charging is suspended. If the thermistor value returns to
an acceptable value, charging resumes. An external resis-
tor on the R

pin sets the total charge time. The timer can

be defeated by forcing the CHG pin to a low voltage.

As the battery approaches the final float voltage, the
charge current will begin to decrease. When the current
drops to 10% of the programmed charge current, an
internal C/10 comparator will indicate this condition by
sinking 25

A at the CHG pin. The charge timer is also reset

to 25% of the total charge time. If this condition is caused
by an input current limit condition, described below, then
the C/10 comparator will be inhibited. When a time-out
occurs, charging is terminated immediately and the CHG
pin changes to a high impedance. The charger will auto-
matically restart if the cell voltage is less than 3.9V. To
restart the charge cycle manually, simply remove the input
voltage and reapply it, or force the ACP/SHDN pin low
momentarily. When the input voltage is not present, the
charger goes into a sleep mode, dropping battery current
drain to 15

A. This greatly reduces the current drain on the

battery and increases the standby time. The charger can be
inhibited at any time by forcing the ACP/SHDN pin to a low
voltage.

Input FET

The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLN pin
and provides the logic indicator of AC present on the
ACP/SHDN pin. It controls the gate of the input FET to keep
a low forward voltage drop when charging and also
prevents reverse current flow through the input FET.

If the input voltage is less than V

CLN

, it must go at least

170mV higher than V

CLN

to activate the charger. When this

occurs the ACP/SHDN pin is released and pulled up with
an internal load to indicate that the adapter is present. The
gate of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLN drops to less than 25mV,
the input FET is turned off slowly. If the voltage between

DCIN and CLN is ever less than 25mV, then the input FET
is turned off in less than 10

s to prevent significant

reverse current from flowing in the input FET. In this
condition, the ACP/SHDN pin is driven low and the charger
is disabled.

Battery Charger Controller

The LTC4006 charger controller uses a constant off-time,
current mode step-down architecture. During normal op-
eration, the top MOSFET is turned on each cycle when the
oscillator sets the SR latch and turned off when the main
current comparator I

CMP

resets the SR latch. While the top

MOSFET is off, the bottom MOSFET is turned on until
either the inductor current trips the current comparator
I

REV

or the beginning of the next cycle. The oscillator uses

the equation:

OFF

DCIN

BAT

DCIN

OSC

to set the bottom MOSFET on time. This activity is dia-
grammed in Figure 1.

Figure 1

TGATE

OFF

BGATE

INDUCTOR

CURRENT

OFF

TRIP POINT SET BY ITH VOLTAGE

OFF

4006 F01

The peak inductor current, at which I

CMP

resets the SR

latch, is controlled by the voltage on I

. I

is in turn

controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by R

IMON

at the I

MON

pin and adjusts

until:

REF

IMON

CSP

BAT

11 67

LTC4006

4006i

therefore,

CHARGE

REF

IMON

SENSE

11 67

The voltage at BAT is divided down by an internal resistor
divider and is used by error amp EA to decrease I

if the

divider voltage is above the 1.19V reference. When the
charging current begins to decrease, the voltage at I

MON

will decrease in direct proportion. The voltage at I

MON

then given by:

IMON

CHARGE

SENSE

IMON

(

)

11 67

IMON

is plotted in Figure 2.

The amplifier CL1 monitors and limits the input current to
a preset level (100mV/R

). At input current limit, CL1 will

decrease the I

voltage, thereby reducing charging cur-

rent. When this condition is detected, the C/10 indicator

OPERATIO

will be inhibited if it is not already active. If the charging
current decreases below 10% to 15% of programmed
current, while engaged in input current limiting, BGATE
will be forced low to prevent the charger from discharging
the battery. Audible noise can occur in this mode of
operation.

An overvoltage comparator guards against voltage tran-
sient overshoots (>7% of programmed value). In this
case, both MOSFETs are turned off until the overvoltage
condition is cleared. This feature is useful for batteries
which "load dump" themselves by opening their protec-
tion switch to perform functions such as calibration or
pulse mode charging.

As the voltage at BAT increases to near the input voltage
at DCIN, the converter will attempt to turn on the top
MOSFET continuously ("dropout''). A watchdog timer
detects this condition and forces the top MOSFET to turn

Table 1. Truth Table for LTC4006 Operation

MODE

DCIN

BAT VOLTAGE

BAT CURRENT

ACP/SHDN

TIMER STATE

CHG*

Shut Down by Low Adapter Voltage

<BAT

>UVLO

Leakage

LOW

Reset

HIGH

Conditioning a Depleted Battery

>BAT

<2.5V/Cell

10% Programmed

HIGH

Running

LOW

Current

Normal Charging

>BAT

>2.5V/Cell

Programmed

HIGH

Running

LOW

Current

Input Current Limited Charging

>BAT

>2.5V/Cell

Unknown

HIGH

Running

LOW

Charger Paused Due to Thermistor Out of Range

>BAT

OFF

HIGH

Paused

LOW

(Faulted)

Shut Down by ACP/SHDN Pin

>BAT

OFF

Forced LOW

Reset

HIGH

Terminated by Low-Battery Fault (Note 1)

>BAT

<2.5V/Cell

OFF

HIGH

>T/4 Stopped

HIGH

(Faulted)

Top-Off Charging. C/10 is Latched

>BAT

FLOAT

OFF

HIGH

<T/4 After C/10

Comparator Trip.

Running

Timer is Reset by C/10 Comparator (Latched),

>BAT

FLOAT

OFF

HIGH

>T/4 After C/10

HIGH

then Terminates After 1/4 T

Comparator Trip.

(Waiting

Stopped

for Restart)

Terminated by Expired Timer

>BAT

FLOAT

OFF

HIGH

>T Stopped

HIGH

(Waiting

for Restart)

Timer Defeated. (Low-Battery Conditioning Still

Forced LOW

Functional)

Shut Down by Undervoltage Lockout

>BAT

<UVL

OFF

HIGH

Reset

HIGH**

and <UVL

Timer Defeated Until V

BAT

> 3.9V/Cell

>BAT

2.5V

BAT

3.9V

Programmed

HIGH

Running

LOW

(V/Cell)

Current

*Open Drain. High when used with pull-up resistor.
**Most probable condition, X = Don't care

Note 1: If a depleted battery is inserted while the charger is in this state,
the charger must be reset to initiate charging.

LTC4006

4006i

OPERATIO

NTC

LTC4006

32.4k

C7
0.47

10k

NTC

60k

~4.5V

CLK

45k

15k

BAD

4006 F03

Figure 3

Figure 2. I

MON

vs I

CHARGE

CHARGE

(% OF MAXIMUM CURRENT)

PROG

(V)

0.2

0.4

0.6

0.8

4006 F02

1.0

1.2

100

1.19V

0.309V

This voltage is stored by C7. Then the switch is opened for
a short period of time to read the voltage across the
thermistor.

HOLD

= 10 · R

· 17.5pF = 54

for R

= 309k

When the t

HOLD

interval ends the result of the thermistor

testing is stored in the D flip-flop (DFF). If the voltage at
NTC is within the limits provided by the resistor divider
feeding the comparators, then the NOR gate output will be
low and the DFF will set T

BAD

to zero and charging will

continue. If the voltage at NTC is outside of the resistor
divider limits, then the DFF will set T

BAD

to one, the charger

will be shut down, and the timer will be suspended until
T

BAD

returns to zero (see Figure 4).

off for about 300ns at 40

s intervals. This is done to

prevent audible noise when using ceramic capacitors at
the input and output.

Charger Startup

When the charger is enabled, it will not begin switching
until the I

voltage exceeds a threshold that assures initial

current will be positive. This threshold is 5% to 15% of the
maximum programmed current. After the charger begins
switching, the various loops will control the current at a
level that is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation but is typically less than 100

Thermistor Detection

The thermistor detection circuit is shown in Figure 3. It
requires an external resistor and capacitor in order to
function properly.

The thermistor detector performs a sample-and-hold func-
tion. An internal clock, whose frequency is determined by
the timing resistor connected to R

, keeps switch S1

closed to sample the thermistor:

SAMPLE

= 127.5 · 20 · R

· 17.5pF = 13.8ms,

for R

= 309k

The external RC network is driven to approximately 4.5V
and settles to a final value across the thermistor of:

V R

RTH FINAL

(

)

4 5

CLK

(NOT TO

SCALE)

NTC

SAMPLE

VOLTAGE ACROSS THERMISTOR

HOLD

4006 F04

COMPARATOR HIGH LIMIT

COMPARATOR LOW LIMIT

Figure 4

LTC4006

4006i

APPLICATIO S I FOR ATIO

Charger Current Programming

The basic formula for charging current is:

CHARGE MAX

SENSE

(

)

100

Table 2. Recommended R

SENSE

Resistor Values

MAX

(A)

SENSE

(

) 1%

SENSE

(W)

1.0

0.100

0.25

2.0

0.050

0.25

3.0

0.033

0.5

4.0

0.025

0.5

Setting the Timer Resistor

The charger termination timer is designed for a range of
1hour to 3 hour with a

15% uncertainty. The timer is

programmed by the resistor R

using the following

equation:

TIMER

= 2

· R

· 175pF (Refer to Figure 5)

It is important to keep the parasitic capacitance on the R

pin to a minimum. The trace connecting R

to R

should

be as short as possible.

CHG Status Output Pin

When the charge cycle starts, the CHG pin is pulled down
to ground by an internal N-channel MOSFET that can drive
more than 100

A. When the charge current drops to 10%

of the full-scale current (C/10), the N-channel MOSFET is
turned off and a weak 25

A current source to ground is

connected to the CHG pin. After a time out occurs, the pin
will go into a high impedance state. By using two different
value pull-up resistors, a microprocessor can detect three
states from this pin (charging, C/10 and stop charging).
See Figure 6.

Battery Detection

It is generally not good practice to connect a battery while
the charger is running. The timer is in an unknown state
and the charger could provide a large surge current into
the battery for a brief time. The circuit shown in Figure 7
keeps the charger shut down and the timer reset while a
battery is not connected.

Alternatively, a normally closed switch can be used to
detect when the battery is present (see Figure 8).

Figure 5. t

TIMER

vs R

)

100

TIMER

(MINUTES)

100

200

140

200

300

350

4006 F05

160

180

120

150

250

400 450

500

LTC4006

CHG

33k

200k

4006 F06

3.3V

OUT

Figure 6. Microprocessor Interface

DCIN

ACP/SHDN

470k

LTC4006

ADAPTER

POWER

SWITCH CLOSED IF

BATTERY CONNECTED

4006 F07

Figure 7

DCIN

ACP/SHDN

LTC4006

ADAPTER

POWER

SWITCH OPEN WHEN

BATTERY CONNECTED

4006 F08

Figure 8

LTC4006

4006i

Soft-Start

The LTC4006 is soft started by the 0.12

F capacitor on the

pin. On start-up, I

pin voltage will rise quickly to 0.5V,

then ramp up at a rate set by the internal 40

A pull-up

current and the external capacitor. Battery charging
current starts ramping up when I

voltage reaches 0.8V

and full current is achieved with I

at 2V. With a 0.12

capacitor, time to reach full charge current is about 2ms
and it is assumed that input voltage to the charger will
reach full value in less than 2ms. The capacitor can be
increased up to 1

F if longer input start-up times are

needed.

Input and Output Capacitors

The input capacitor (C2) is assumed to absorb all input
switching ripple current in the converter, so it must have
adequate ripple current rating. Worst-case RMS ripple
current will be equal to one half of output charging current.
Actual capacitance value is not critical. Solid tantalum low
ESR capacitors have high ripple current rating in a rela-
tively small surface mount package,

but caution must be

used when tantalum capacitors are used for input or
output bypass. High input surge currents can be created
when the adapter is hot-plugged to the charger or when a
battery is connected to the charger. Solid tantalum capaci-
tors have a known failure mechanism when subjected to
very high turn-on surge currents. Only Kemet T495 series
of "Surge Robust" low ESR tantalums are rated for high
surge conditions such as battery to ground.

The relatively high ESR of an aluminum electrolytic for C1,
located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event. Refer to Appli-
cation Note 88 for more information.

Highest possible voltage rating on the capacitor will mini-
mize problems. Consult with the manufacturer before use.
Alternatives include new high capacity ceramic (at least
20

F) from Tokin, United Chemi-Con/Marcon, et al. Other

alternative capacitors include OS-CON capacitors from
Sanyo.

The output capacitor (C3) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:

APPLICATIO S I FOR ATIO

L f

RMS

BAT

DCIN

(

)

( )( )

0 29

For example:

DCIN

= 19V, V

BAT

= 12.6V, L1 = 10

H, and

f = 300kHz, I

RMS

= 0.41A.

EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
may be added to increase battery impedance at the 300kHz
switching frequency. Switching ripple current splits be-
tween the battery and the output capacitor depending on
the ESR of the output capacitor and the battery impedance.
If the ESR of C3

is 0.2

and the battery impedance is

raised to 4

with a bead or inductor, only 5% of the

current ripple will flow in the battery.

Inductor Selection

Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency gener-
ally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value on
ripple current and low current operation must also be
considered. The inductor ripple current

decreases

with higher frequency and increases with higher V

( )( )

f L

OUT

Accepting larger values of

allows the use of low

inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is

= 0.4(I

MAX

). In no case should

exceed 0.6(I

MAX

) due to limits imposed by I

REV

and

CA1. Remember the maximum

occurs at the maxi-

mum input voltage. In practice 10

H is the lowest value

recommended for use.

Lower charger currents generally call for larger inductor
values. Use Table 3 as a guide for selecting the correct
inductor value for your application.

LTC4006

4006i

Table 3

MAXIMUM

INPUT

MINIMUM INDUCTOR

AVERAGE CURRENT (A)

VOLTAGE (V)

VALUE (

20%

> 20

20%

> 20

20%

> 20

20%

> 20

20%

Charger Switching Power MOSFET
and Diode Selection

Two external power MOSFETs must be selected for use
with the charger: a P-channel MOSFET for the top (main)
switch and an N-channel MOSFET for the bottom (syn-
chronous) switch.

The peak-to-peak gate drive levels are set internally. This
voltage is typically 6V. Consequently, logic-level threshold
MOSFETs must be used. Pay close attention to the BV

DSS

specification for the MOSFETs as well; many of the logic
level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the "ON"
resistance R

DS(ON)

, total gate capacitance Q

, reverse

transfer capacitance C

RSS

, input voltage and maximum

output current. The charger is operating in continuous
mode at moderate to high currents so the duty cycles for
the top and bottom MOSFETs are given by:

Main Switch Duty Cycle = V

OUT

Synchronous Switch Duty Cycle = (V

OUT

)/V

The MOSFET power dissipations at maximum output
current are given by:

PMAIN = V

OUT

MAX

)(1 +

T)R

DS(ON)

+ k(V

)(I

MAX

)(C

RSS

)(f

OSC

)

PSYNC = (V

OUT

)/V

MAX

)(1 +

T)R

DS(ON)

Where

is the temperature dependency of R

DS(ON)

and k

is a constant inversely related to the gate drive current.
Both MOSFETs have I

R losses while the PMAIN equation

includes an additional term for transition losses, which are

highest at high input voltages. For V

< 20V the high

current efficiency generally improves with larger MOSFETs,
while for V

> 20V the transition losses rapidly increase

to the point that the use of a higher R

DS(ON)

device with

lower C

RSS

actually provides higher efficiency. The syn-

chronous MOSFET losses are greatest at high input volt-
age or during a short circuit when the duty cycle in this
switch in nearly 100%. The term (1 +

T) is generally

given for a MOSFET in the form of a normalized R

DS(ON)

temperature curve, but

= 0.005/

C can be used as an

approximation for low voltage MOSFETs. C

RSS

is usually

specified in the MOSFET characteristics; if not, then C

RSS

can be calculated using C

RSS

= Q

. The constant

k = 2 can be used to estimate the contributions of the two
terms in the main switch dissipation equation.

If the charger is to operate in low dropout mode or with a
high duty cycle greater than 85%, then the topside
P-channel efficiency generally improves with a larger
MOSFET. Using asymmetrical MOSFETs may achieve cost
savings or efficiency gains.

The Schottky diode D1, shown in the Typical Application
on the back page, conducts during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency. A 1A Schottky is generally a
good size for 4A regulators due to the relatively small
average current. Larger diodes can result in additional
transition losses due to their larger junction capacitance.

The diode may be omitted if the efficiency loss can be
tolerated.

Calculating IC Power Dissipation

The power dissipation of the LTC4006 is dependent upon
the gate charge of the top and bottom MOSFETs (Q

and

respectively) The gate charge is determined from the

manufacturer's data sheet and is dependent upon both the
gate voltage swing and the drain voltage swing of the
MOSFET. Use 6V for the gate voltage swing and V

DCIN

for

the drain voltage swing.

= V

DCIN

· (f

OSC

+ Q

) + I

DCIN

)

APPLICATIO S I FOR ATIO

LTC4006

4006i

APPLICATIO S I FOR ATIO

Figure 9. Adapter Current Limiting

Table 5. Common R

Resistor Values

ADAPTER

RCL VALUE*

RCL POWER

RATING (A)

(

) 1%

DISSIPATION (W)

RATING (W)

1.5

0.06

0.135

0.25

1.8

0.05

0.162

0.25

0.045

0.18

0.25

2.3

0.039

0.206

0.25

2.5

0.036

0.225

0.5

2.7

0.033

0.241

0.5

0.03

0.27

0.5

* Values shown above are rounded to nearest standard value.

As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one can
simply set the adapter current limit value to the actual
adapter rating (see Table 5).

Designing the Thermistor Network

There are several networks that will yield the desired
function of voltage vs temperature needed for proper
operation of the thermistor. The simplest of these is the
voltage divider shown in Figure 10. Unfortunately, since
the HIGH/LOW comparator thresholds are fixed internally,
there is only one thermistor type that can be used in this
network; the thermistor must have a HIGH/LOW resis-
tance ratio of 1:7. If this happy circumstance is true for
you, then simply set R9 = R

TH(LOW)

If you are using a thermistor that doesn't have a 1:7 HIGH/
LOW ratio, or you wish to set the HIGH/LOW limits to
different temperatures, then the more generic network in
Figure 11 should work.

Once the thermistor, R

, has been selected and the

thermistor value is known at the temperature limits, then
resistors R9 and R9A are given by:

For NTC thermistors:

R9 = 6 R

TH(LOW)

· R

TH(HIGH)

/(R

TH(LOW)

TH(HIGH)

)

R9A = 6 R

TH(LOW)

· R

TH(HIGH)

/(R

TH(LOW)

7 · R

TH(HIGH)

)

For PTC thermistors:

R9 = 6 R

TH(LOW)

· R

TH(HIGH)

/(R

TH(HIGH)

TH(LOW)

)

R9A = 6 R

TH(LOW)

· R

TH(HIGH)

/(R

TH(HIGH)

7 ·

TH(LOW)

)

100mV

CLP

LTC4006

CLN

4006 F09

15nF

CL1

AC ADAPTER

INPUT

100mV

ADAPTER CURRENT LIMIT

Example:

DCIN

= 19V, f

OSC

= 345kHz, Q

= Q

= 15nC.

PD = 292mW

Adapter Limiting

An important feature of the LTC4006 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the prod-
uct to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
maximum possible rate of which the adapter is capable.

This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed-loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1
in Figure 9 senses the voltage across R

, connected

between the CLP and DCIN pins. When this voltage ex-
ceeds 100mV, the amplifier will override programmed
charging current to limit adapter current to 100mV/R

. A

lowpass filter formed by 5k

and 15nF is required to

eliminate switching noise. If the current limit is not used,
CLP should be connected to CLN.

Setting Input Current Limit

To set the input current limit, you need to know the
minimum wall adapter current rating. Subtract 5% for the
input current limit tolerance and use that current to deter-
mine the resistor value.

= 100mV/I

LIM

= Adapter Min Current

(Adapter Min Current · 5%)

LTC4006

4006i

Example #1: 10k

NTC with custom limits

TLOW = 0

C, THIGH = 50

= 10k at 25

TH(LOW)

= 32.582k at 0

TH(HIGH)

= 3.635k at 50

R9 = 24.55k

24.3k (nearest 1% value)

R9A = 99.6k

100k (nearest 1% value)

Example #2: 100k

NTC

TLOW = 5

C, THIGH = 50

= 100k at 25

TH(LOW)

= 272.05k at 5

TH(HIGH)

= 33.195k at 50

R9 = 226.9k

226k (nearest 1% value)

R9A = 1.365M

1.37M (nearest 1% value)

Example #3: 22k

PTC

TLOW = 0

C, THIGH = 50

= 22k at 25

TH(LOW)

= 6.53k at 0

TH(HIGH)

= 61.4k at 50

R9 = 43.9k

44.2k (nearest 1% value)

R9A = 154k

Sizing the Thermistor Hold Capacitor

During the hold interval, C7 must hold the voltage across
the thermistor relatively constant to avoid false readings.
A reasonable amount of ripple on NTC during the hold
interval is about 10mV to 15mV. Therefore, the value of C7
is given by:

C7 = t

HOLD

/(R9/7 · ln(1 8 · 15mV/4.5V))

= 10 · R

· 17.5pF/(R9/7 · ln(1 8 · 15mV/4.5V)

Example:

R9 = 24.3k
R

= 309k (~2 hour timer)

C7 = 0.58

0.56

F (nearest value)

APPLICATIO S I FOR ATIO

Disabling the Thermistor Function

If the thermistor is not needed, connecting a resistor
between DCIN and NTC will disable it. The resistor should
be sized to provide at least 10

A with the minimum voltage

applied to DCIN and 10V at NTC. Do not exceed 30

A into

NTC. Generally, a 301k resistor will work for DCIN less
than 15V. A 499k resistor is recommended for DCIN
between 15V and 24V.

PCB Layout Considerations

For maximum efficiency, the switch node rise and fall times
should be minimized. To prevent magnetic and electrical
field radiation and high frequency resonant problems,
proper layout of the components connected to the IC is
essential. (See Figure 12.) Here is a PCB layout priority list
for proper layout. Layout the PCB using this specific order.

1. Input capacitors need to be placed as close as possible

to switching FET's supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.

2. The control IC needs to be close to the switching FET's

gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that con-
nect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.

3. Place inductor input as close as possible to switching

FET's output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current--no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.

4. Place the output current sense resistor right next to

the inductor output but oriented such that the IC's

Figure 10. Voltage Divider Thermistor Network

Figure 11. General Thermistor Network

LTC4006

NTC

4006 F10

LTC4006

NTC

R9A

4006 F11

LTC4006

4006i

APPLICATIO S I FOR ATIO

current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time with
smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at the
sense resistor location.

5. Place output capacitors next to the sense resistor

output and ground.

6. Output capacitor ground connections need to feed

into same copper that connects to the input capacitor
ground before tying back into system ground.

General Rules

7. Connection of switching ground to system ground or

internal ground plane should be single point. If the
system has an internal system ground plane, a good
way to do this is to cluster vias into a single star point
to make the connection.

8. Route analog ground as a trace tied back to IC ground

(analog ground pin if present) before connecting to

any other ground. Avoid using the system ground
plane. CAD trick: make analog ground a separate
ground net and use a 0

resistor to tie analog ground

to system ground.

9. A good rule of thumb for via count for a given high

current path is to use 0.5A per via. Be consistent.

10. If possible, place all the parts listed above on the same

PCB layer.

11. Copper fills or pours are good for all power connec-

tions except as noted above in Rule 3. You can also use
copper planes on multiple layers in parallel too--this
helps with thermal management and lower trace in-
ductance improving EMI performance further.

12. For best current programming accuracy provide a

Kelvin connection from R

SENSE

to CSP and BAT. See

Figure 12 as an example.

It is important to keep the parasitic capacitance on the R

CSP and BAT pins to a minimum. The traces connecting
these pins to their respective resistors should be as short
as possible.

4006 F12

BAT

HIGH

FREQUENCY

CIRCULATING

PATH

BAT

SWITCH NODE

CSP

4006 F13

DIRECTION OF CHARGING CURRENT

SNS

BAT

Figure 12. High Speed Switching Path

Figure 13. Kelvin Sensing of Charging Current

GN16 (SSOP) 0502

.016 .050

(0.406 1.270)

.015

.004

(0.38

0.10)

TYP

.007 .0098

(0.178 0.249)

.053 .068

(1.351 1.727)

.008 .012

(0.203 0.305)

.004 .0098

(0.102 0.249)

.0250

(0.635)

BSC

.229 .244

(5.817 6.198)

.150 .157**
(3.810 3.988)

16 15 14 13

.189 .196*

(4.801 4.978)

12 11 10 9

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 .165

.0250 TYP

.0165

.0015

.045

.005

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:
1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

LTC4006

4006i

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

LINEAR TECHNOLOGY CORPORATION 2003

LT/TP 0503 1K · PRINTED IN USA

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TYPICAL APPLICATIO

2A Li-Ion Battery Charger

DCIN

CHG

ACP/SHDN

MON

NTC

GND

CHG

ACP

INFET

CLP

CLN

TGATE

BGATE

PGND

CSP

BAT

LTC4006

0.12

THERMISTOR

10k

NTC

309k

TIMING

RESISTOR

(~2 HOURS)

0.0047

C7
0.47

R9 32.4k

CHARGING

CURRENT MONITOR

R3
100k

LOGIC

DCIN

0V TO 20V

2.5A

6.04k

0.1

INPUT SWITCH

D1: MBRM140T3
Q1, Q3: Si3457
Q2: Si3454

C4
15nF

C2
20

TO LOAD

H 2A

SENSE

0.05

0.04

C3
20

BATTERY

4006 TA02

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC4006-6

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC4006-6