240
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP723
The SP723 is an array of SCR/Diode bipolar structures for ESD and
over-voltage protection of sensitive input circuits. The SP723 has 2
protection SCR/Diode device structures per input. There are a total of 6
available inputs that can be used to protect up to 6 external signal or bus
lines. Over-voltage protection is from the IN (Pins 1 - 3 and Pins 5 - 7)
to V+ or V-.
The SCR structures are designed for fast triggering at a threshold of one
+VBE diode threshold above V+ (Pin 8) or a -VBE diode threshold below
V- (Pin 4). From an IN input, a clamp to V+ is activated if a transient
pulse causes the input to be increased to a voltage level greater than
one VBE above V+. A similar clamp to V- is activated if a negative pulse,
one VBE less than V-, is applied to an IN input.
Refer to Fig 1 and Table 1 for further details. Refer to Application Note
AN9304 and AN9612 for further detail.
Features
ESD Interface per HBM Standards
- IEC 61000-4-2, Direct Discharge . . . . . . . . . . . . . . . . . 8kV (Level 4)
- IEC 61000-4-2, Air Discharge . . . . . . . . . . . . . . . . . . 15kV (Level 4)
- MIL-STD-3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25kV
Peak Current Capability
- IEC 61000-4-5 8/20s Peak Pulse Current. . . . . . . . . . . . . . . . . 7A
- Single Transient Pulse, 100s Pulse Width. . . . . . . . . . . . . . . . . . 4A
Designed to Provide Over-Voltage Protection
- Single-Ended Voltage Range to . . . . . . . . . . . . . . . . . . . . . . . . +30V
- Differential Voltage Range to. . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Fast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ns Risetime
Low Input Leakages . . . . . . . . . . . . . . . . . . . . . . . . 2nA at 25
o
C Typical
Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5pF Typical
An Array of 6 SCR/Diode Pairs
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . -40
o
C to 105
o
C
Applications
Microprocessor/Logic Input Protection
Data Bus Protection
Analog Device Input Protection
Voltage Clamp
Pinout
SP723
(PDIP, SOIC)
TOP VIEW
Ordering Information
Functional Diagram
PART
NUMBER
Min. Order
Qty.
TEMP. RANGE
(
o
C)
PACKAGE
PKG. NO.
SP723AP
-40 to 105
8 Ld PDIP
E8.3
2000
1960
2500
SP723AB
-40 to 105
8 Ld SOIC
M8.15
SP723ABT
-40 to 105
8 Ld SOIC
Tape and Reel
M8.15
4
V+
V-
IN
3, 5-7
IN
IN
1
8
2
IN
IN
IN
V-
1
2
3
4
8
7
6
5
V+
IN
IN
IN
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5
TVS DIODE ARRA
YS
TVS Diode Arrays
SP723
Electronic Protection Array for ESD and Overvoltage Protection
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specification
TA =40
o
C to 105
o
C, VIN = 0.5VCC, Unless Otherwise Specified
Absolute Maximum Ratings
Continuous Supply Voltage, (V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . +35V
Forward Peak Current, IIN to VCC, IIN to GND
(Refer to Figure 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4A, 100s
Peak Pulse Current, 8/20s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7A
ESD Ratings and Capability (Figure 1, Table 1)
Load Dump and Reverse Battery (Note 2)
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65
o
C to 150
o
C
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . .. . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
ESD Capability
ESD capability is dependent on the application and defined test
standard.The evaluation results for various test standards and methods
based on Figure 1 are shown in Table 1.
The SP723 has a Level 4 HBM capability when tested as a device to the
IEC 61000-4-2 standard. Level 4 specifies a required capability greater
than 8kV for direct discharge and greater than 15kV for air discharge.
For the "Modified" MIL-STD-3015.7 condition that is defined as an "in-
circuit" method of ESD testing, the V+ and V- pins have a return path to
ground and the SP723 ESD capability is typically greater than 25kV from
100pF through 1.5k
. By strict definition of MIL-STD-3015.7 using "pin-
to-pin" device testing, the ESD voltage capability is greater than 10kV.
For the SP723 EIAJ IC121 Machine Model (MM) standard, the ESD capa-
bility is typically greater than 2kV from 200pF with no series resistance.
STANDARD
TYPE/MODE
R
D
C
D
V
D
IEC 1000-4-2
(Level 4)
HBM, Air Discharge
330
150pF 15kV
HBM, Direct Discharge
330
150pF
8kV
MIL-STD-3015.7 Modified HBM
1.5k
100pF 25kV
Standard HBM
1.5k
100pF 10kV
EIAJ IC121
Machine Model
0k
200pF
2kV
H.V.
SUPPLY
V
D
IN
DUT
C
D
R
1
IEC 1000-4-2: R
1
50 to 100M
R
D
CHARGE
SWITCH
DISCHARGE
SWITCH
MIL-STD-3015.7: R
1
1 to 10M
FIGURE 1. ELECTROSTATIC DISCHARGE TEST
TABLE 1. ESD TEST CONDITIONS
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP723
FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP
CURVE
FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP
CURVE
600
800
1000
1200
FORWARD SCR VOLTAGE DROP (mV)
200
160
120
80
40
0
FOR
W
ARD SCR CURRENT (mA)
T
A
= 25
o
C
SINGLE PULSE
5
4
3
2
1
0
FOR
W
ARD SCR CURRENT (A)
T
A
= 25
o
C
SINGLE PULSE
V
FWD
I
FWD
0
1
2
3
FORWARD SCR VOLTAGE DROP (V)
EQUIV. SAT. ON
THRESHOLD ~ 1.1V
FIGURE 4. TYPICAL APPLICATION OF THE SP723 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1V
BE
ABOVE V+ OR
LESS THAN -1V
BE
BELOW V-
+V
CC
INPUT
DRIVERS
SP723 INPUT PROTECTION CIRCUIT (1 OF 6 SHOWN)
OR
SIGNAL
SOURCES
IN 5 - 7
IN 1 - 3
SP723
V-
TO +V
CC
LINEAR OR
DIGITAL IC
INTERFACE
V+
+V
CC
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5
TVS DIODE ARRA
YS
TVS Diode Arrays
SP723
Electronic Protection Array for ESD and Overvoltage Protection
Peak Transient Current Capability of the SP723
The peak transient current capability rises sharply as the width of the
current pulse narrows. Destructive testing was done to fully evaluate the
SP723's ability to withstand a wide range of peak current pulses vs time.
The circuit used to generate current pulses is shown in Figure 5.
The test circuit of Figure 5 is shown with a positive pulse input. For a
negative pulse input, the (-) current pulse input goes to an SP723 `IN'
input pin and the (+) current pulse input goes to the SP723 V- pin. The
V+ to V- supply of the SP723 must be allowed to float. (i.e., It is not tied
to the ground reference of the current pulse generator.) Figure 6 shows
the point of overstress as defined by increased leakage in excess of the
data sheet published limits.
The maximum peak input current capability is dependent on the ambient
temperature, improving as the temperature is reduced. Peak current
curves are shown for ambient temperatures of 25
o
C and 105
o
C and a 15V
power supply condition. The safe operating range of the transient peak
current should be limited to no more than 75% of the measured over-
stress level for any given pulse width as shown in the curves of Figure 6.
Note that adjacent input pins of the SP723 may be paralleled to improve
current (and ESD) capability. The sustained peak current capability is
increased to nearly twice that of a single pin.
+
-
CURRENT
SENSE
VOLTAGE
PROBE
6
7
8
5
1
2
3
4
IN
IN
IN
V-
V+
IN
IN
IN
+
-
R
1
~ 10
TYPICAL
SP723
V
X
V
X
ADJ. 10V/A TYPICAL
R
1
(
-
)
(+)
C1 ~ 100
F
C1
VARIABLE TIME DURATION
CURRENT PULSE GENERATOR
FIGURE 5. TYPICAL SP723 PEAK CURRENT TEST CIRCUIT
WITH A VARIABLE PULSE WIDTH INPUT
FIGURE 6. SP723 TYPICAL SINGLE PULSE PEAK CURRENT CURVES SHOWING THE MEASURED POINT OF OVERSTRESS IN
AMPERES vs PULSE WIDTH TIME IN MILLISECONDS
0.001
0.01
0.1
1
PULSE WIDTH TIME (ms)
PEAK CURRENT (A)
10
14
12
10
8
6
4
2
0
100 1000
CAUTION:
OF THE VALUES SHOWN ON EACH CURVE.
PULSE WIDTH TO BE NO GREATER THAN 75%
THE MAXIMUM PEAK CURRENT FOR A GIVEN
V+ TO V- SUPPLY = 15V
T
A
= 105
o
C
T
A
= 25
o
C
SAFE OPERATING CONDITIONS LIMIT
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP723
Dual-In-Line Plastic Packages (PDIP)
E8.3
(JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
C
L
E
e
A
C
e
B
e
C
-B-
E1
INDEX
1 2 3
N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A
1
-A-
0.010 (0.25)
C
A
M
B S
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the "MO Series Symbol List" in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and
are measured with the leads constrained to be per-
pendicular to datum
.
7. e
B
and e
C
are measured at the lead tips with the leads uncon-
strained. e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
e
A
-C-
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8, 10
C
0.008
0.014
0.204
0.355
-
D
0.355
0.400
9.01
10.16
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
e
A
0.300 BSC
7.62 BSC
6
e
B
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
8
8
9
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TVS Diode Arrays
SP723
Electronic Protection Array for ESD and Overvoltage Protection
Small Outline Plastic Packages (SOIC)
M8.15
(JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
0.25(0.010)
B
M
M
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
8
8
7
0
o
8
o
0
o
8
o
-
TVS DIODE ARRA
YS
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