DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/

23/2000LDS.29C525-G

u Dual 8-Deep Pipeline Register
u

u Configurable to Single 16-Deep
u

u Low Power CMOS Technology
u

u Replaces AMD Am29525
u

u Load, Shift, and Hold Instructions
u

u Separate Data In and Data Out Pins
u

u Three-State Outputs
u

u Package Styles Available:

· 28-pin Plastic DIP
· 28-pin Plastic LCC, J-Lead

FEATURES

DESCRIPTION

L29C525

Dual Pipeline Register

DEVICES INCORPORATED

The L29C525 is a high-speed, low
power CMOS pipeline register. It is
pin-for-pin compatible with the AMD
Am29525. The L29C525 can be
configured as two independent 8-level
pipelines or as a single 16-level
pipeline. The configuration imple-
mented is determined by the instruc-
tion code (I

1-0

) as shown in Table 2.

The I

1-0

instruction code controls the

internal routing of data and loading of
each register. For instruction I

1-0

= 00

(Push A and B), data applied at the
D

7-0

inputs is latched into register A0

on the rising edge of CLK. The
contents of A0 simultaneously move
to register A1, A1 moves to A2, and so
on. The contents of register A7 are
wrapped back to register B0. The
registers on the B side are similarly
shifted, with the contents of register
B7 lost.

Instruction I

1-0

= 01 (Push B) acts

similarly to the Push A and B
instruction, except that only the B side
registers are shifted. The input data is
applied to register B0, and the
contents of register B7 are lost. The
contents of the A side registers are
unaffected. Instruction I

1-0

= 10 (Push

A) is identical to the Push B
instruction, except that the A side
registers are shifted and the B side
registers are unaffected.

Instruction I

1-0

= 11 (Hold) causes no

internal data movement. It is equiva-
lent to preventing the application of a
clock edge to any internal register.

The contents of any of the registers is
selectable at the output through the
use of the S

3-0

control inputs. The

independence of the I and S control
lines allows simultaneous reading and
writing. Encoding for the S

3-0

controls

is given in Table 3.

L29C525 B

LOCK

IAGRAM

7-0

1-0

CLK

MUX

3-0

DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/27/2000LDS.29C525-G

ABLE

EGISTER

OAD

PERATIONS

Single 16 Level

Dual 8 Level

Push A and B

Push A

Hold All Registers

Push B

HOLD

ABLE

NSTRUCTION

ABLE

UTPUT

ELECT

Inputs

Mnemonics

Description

Shift

Push A and B

LDB

Push B

LDA

Push A

HLD

Hold All Registers

7-0

DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/32/2000LDS.29C525-G

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Output High Voltage

= Min., I

= 12 mA

2.4

Output Low Voltage

= Min., I

= 24 mA

0.5

Input High Voltage

2.0

Input Low Voltage

(Note 3)

0.0

0.8

Input Current

Ground

(Note 12)

µA

Output Leakage Current

Ground

OUT

(Note 12)

µA

CC1

Current, Dynamic

(Notes 5, 6)

CC2

Current, Quiescent

(Note 7)

1.0

Storage temperature ........................................................................................................... 65°C to +150°C

Operating ambient temperature ........................................................................................... 55°C to +125°C

supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V

Input signal with respect to ground ........................................................................................ 3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... 3.0 V to +7.0 V

Output current into low outputs ............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

AXIMUM

ATINGS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

PERATING

ONDITIONS

To meet specified electrical and switching characteristics

LECTRICAL

HARACTERISTICS

Over Operating Conditions (Note 4)

Mode

Temperature Range (Ambient)

Supply

Voltage

Active Operation, Commercial

0°C to +70°C

4.75 V

5.25 V

Active Operation, Military

55°C to +125°C

4.50 V

5.50 V

DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/27/2000LDS.29C525-G

1234567890123456789012345678901

L29C525

Symbol

Parameter

Min

Max

Min

Max

Clock to Output Delay

SEL

Select to Output Delay

Clock Pulse Width

Data Setup Time

Data Hold Time

Instruction Setup Time

Instruction Hold Time

ENA

Three-State Output Enable Delay

(Note 11)

DIS

Three-State Output Disable Delay

(Note 11)

OMMERCIAL

PERATING

ANGE

(0°C to +70°C)

Notes 9, 10 (ns)

SWITCHING CHARACTERISTICS

ILITARY

PERATING

ANGE

(55°C to +125°C)

Notes 9, 10 (ns)

L29C525

25*

20*

Symbol

Parameter

Min

Max

Min

Max

Clock to Output Delay

SEL

Select to Output Delay

Clock Pulse Width

Data Setup Time

Data Hold Time

Instruction Setup Time

Instruction Hold Time

ENA

Three-State Output Enable Delay

(Note 11)

DIS

Three-State Output Disable Delay

(Note 11)

WITCHING

AVEFORMS

HIGH IMPEDANCE

CLK

7-0

1-0

3-0

SEL

DIS

ENA

1234567890123456789

ISCONTINUED

PEED

RADE

DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/32/2000LDS.29C525-G

1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.

2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.

3. This device provides hard clamping of
transient undershoot and overshoot. In-
put levels below ground or above V

will be clamped beginning at 0.6 V and
V

+ 0.6 V. The device can withstand

indefinite operation with inputs in the
range of 0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.

4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.

5. Supply current for a given applica-
tion can be accurately approximated by:

where

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.

7. Tested with all inputs within 0.1 V of
V

or Ground, no load.

8. These parameters are guaranteed
but not 100% tested.

NCV F

NOTES

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t

DIS

test), and input levels of nominally

0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified I

and I

at an output

voltage of V

min and V

max

respectively. Alternatively, a diode
bridge with upper and lower current
sources of I

and I

respectively,

and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.

This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

a. A 0.1 µF ceramic capacitor should be
installed between V

and Ground

leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device V

and the tester common, and device
ground and tester common.

b. Ground and V

supply planes

must be brought directly to the DUT
socket or contactor fingers.

c. Input voltages should be adjusted to
compensate for inductive ground and V

noise to maintain required DUT input
levels relative to the DUT ground pin.

10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.

11. For the t

ENA

test, the transition is

measured to the 1.5 V crossing point
with datasheet loads. For the t

DIS

test,

the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V

, is set at 3.5 V for Z-to-0

and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.

12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

DUT

0.2 V

DIS

ENA

0.2 V

1.5 V

3.5V Vth

1.5 V

0V Vth

Measured V

with I

= 10mA and I

= 10mA

Measured V

with I

= 10mA and I

= 10mA

IGURE

B. T

HRESHOLD

EVELS

IGURE

A. O

UTPUT

OADING

IRCUIT

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: L29C525C-20