Video Imaging Products
1
LF3370
High-Definition Video Format Converter
03/13/2001LDS.3370-F
DEVICES INCORPORATED
COLORSPACE
CONVERTER/
KEY SCALER
INPUT DE-MULTIPLEXER SECTION
55-TAP HALF-BAND
INTERPOLATION/
DECIMATION
FILTERS
OUTPUT MULTIPLEXER SECTION
B
12-0
C
12-0
A
12-0
D
12-0
X
12-0
Y
12-0
W
12-0
Z
12-0
1K x 13-Bit
LOOK-UP-TABLES
INPUT BIAS ADDERS
OUTPUT BIAS ADDERS
FEATURES
LF3370
High-Definition Video Format Converter
DEVICES INCORPORATED
u
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u 83 MHz Data Rate for HDTV
Applications
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u
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u
u Supports Multiple Video Formats
Bi-Directional Conversions:
- 4:2:2:4
- 4:4:4:4
- R/G/B/Key
- Y/U/V/Key
u
u
u
u
u Multiplexed and Non-multiplexed
I/O Data
u
u
u
u
u User-Programmable:
- 3 x 3 Colorspace Converter
- LUT for Gamma Correction
- I/O Bias Compensation
- Bypass Capability
u
u
u
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u 13-bit Data Path, Colorspace
Converter Coefficients and Key
Channel Scaling Coefficients
u
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u 160-lead PQFP
DESCRIPTION
The LF3370 is a video format
converter capable of operating at
HDTV data rates. This device
converts to and from any of the
various SDTV/HDTV digital video
formats by utilizing an internal
3 x 3 Matrix Multiplier and two
1:2 Interpolation/2:1 Decimation
Half-Band Filters.
Using the Input Demultiplexer
and Output Multiplexer, the
LF3370 can accept and output
interleaved or non-interleaved
video. For example, R/G/B/Key
data can be color space converted
to Y/U/V/Key and down-con-
verted to 4:2:2:4. By re-arranging
the order of the functional sec-
tions, the opposite conversion can
be achieved. The coefficients for
the 3 x 3 Matrix Multiplier are
fully user programmable to sup-
port a wide range of color space
conversions. The two Interpola-
tion/Decimation Half-Band Filters
are fully compliant with SMPTE
260M.
Input and Output Bias Adders are
included for removing or adding a
user-defined bias into the video
signal. In addition, three pro-
grammable 1K x 13-bit Look-Up
Tables (LUTs) have also been
included for various uses such as
gamma correction. A Scaler has
been included on the Key Channel
for scaling to a desired magnitude
using user programmable coeffi-
cients.
Input signals can also be forced to
user-defined levels for horizontal
blanking. Furthermore, Round/
Select/Limit (RSL) circuitry is
provided at the end of various
stages to provide the best possible
conversions without color viola-
tions. For additional flexibility,
the Halfband Filter can be indi-
vidually bypassed using an inter-
nal programmable length delay.
All control and coefficient registers
are loaded through the LF Inter-
faceTM.
This device operates at 3.3 V (5 V
tolerant I/O) and is available in
160-lead PQFP package.
LF3370 B
LOCK
D
IAGRAM
LF3370
High-Definition Video Format Converter
2
03/13/2001LDS.3370-F
Video Imaging Products
DEVICES INCORPORATED
F
IGURE
1.
LF3370 F
UNCTIONAL
B
LOCK
D
IAGRAM
(H
ALF
-B
AND
F
ILTER
TO
C
OLORSPACE
A
RRANGEMENT
)
HALF-BAND
FILTER/
INTERPOLATOR
HALF-BAND
FILTER/
INTERPOLATOR
1K x 13-bit
LUT*
1K x 13-bit
LUT*
1K x 13-bit
LUT*
CHROMA HALF-BAND FILTER / INTERPOLATOR
OUTPUT
MUX
3 X 3 MATRIX MULTIPLY / KEY SCALER
OUTPUT
BIAS
ADDER
OUTPUT
BIAS
ADDER
OUTPUT
BIAS
ADDER
COLORSPACE
CONVERTER
KEY SCALER
2
1
INPUT
DEMUX
INPUT
BIAS
ADDER
INPUT
BIAS
ADDER
INPUT
BIAS
ADDER
1K x 13-bit
LUT*
1K x 13-bit
LUT*
1K x 13-bit
LUT*
2
13
13
20
13
20
13
35
13
13
13
13
13
35
13
13
13
13
13
13
13
13
13
13
13
13
WOUT
12-0
XOUT
12-0
YOUT
12-0
ZOUT
12-0
RSL
1-0
ROUND
SELECT
LIMIT
ROUND
SELECT
LIMIT
20
13
20
13
ROUND
SELECT
LIMIT
ROUND
SELECT
LIMIT
20
ROUND
SELECT
LIMIT
20
ROUND
SELECT
LIMIT
13
13
1
3
INBIAS
1-0
13
13
13
13
13
13
13
AIN
12-0
BIN
12-0
CIN
12-0
DIN
12-0
13
13
13
13
2
OE
3
2
3-5
COEFFICIENT
BANKS 0-9
2
CA
1-0
2
2
OUTBIAS
1-0
LF
INTERFACE
CF
12-0
LD
13
PAUSE
SYNC
HBLANK
DATAPASS
RESET
FLAG
GENERATOR
HF
0
HF
1
CLK
INPUT LOOK-UP-TABLE*
OUTPUT LOOK-UP-TABLE*
CONFIGURATION AND
CONTROL REGISTERS
NOTE:
NUMBERS IN REGISTERS INDICATE NUMBER OF PIPELINE DELAYS WHICH IS ALSO EQUIVALENT
TO NUMBER OF PIPELINE DELAYS THROUGH THAT PARTICULAR FUNCTIONAL BLOCK
*
UP TO ONE LOOK-UP-TABLE MAY BE USED PER DATA PATH. THE INHERENT DELAY THROUGH
THE LOOK-UP-TABLE IS TWO REGARDLESS OF WHETHER IT IS USED OR NOT.
Video Imaging Products
3
LF3370
High-Definition Video Format Converter
03/13/2001LDS.3370-F
DEVICES INCORPORATED
F
IGURE
2.
LF3370 F
UNCTIONAL
B
LOCK
D
IAGRAM
(C
OLORSPACE
TO
H
ALF
-B
AND
F
ILTER
A
RRANGEMENT
)
1K x 13-bit
LUT*
1K x 13-bit
LUT*
1K x 13-bit
LUT*
OUTPUT
MUX
OUTPUT
BIAS
ADDER
OUTPUT
BIAS
ADDER
OUTPUT
BIAS
ADDER
2
1
INPUT
DEMUX
INPUT
BIAS
ADDER
INPUT
BIAS
ADDER
INPUT
BIAS
ADDER
1K x 13-bit
LUT*
1K x 13-bit
LUT*
1K x 13-bit
LUT*
2
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
WOUT
12-0
XOUT
12-0
YOUT
12-0
ZOUT
12-0
RSL
1-0
13
13
13
13
1
INBIAS
1-0
13
13
13
13
13
13
13
AIN
12-0
BIN
12-0
CIN
12-0
DIN
12-0
13
13
13
13
2
OE
2
3-5
HALF-BAND
FILTER/
DECIMATOR
HALF-BAND
FILTER/
DECIMATOR
CHROMA HALF-BAND FILTER / INTERPOLATOR
20
20
35
35
ROUND
SELECT
LIMIT
ROUND
SELECT
LIMIT
2
2
OUTBIAS
1-0
LF
INTERFACE
CF
12-0
LD
13
PAUSE
3 X 3 MATRIX MULTIPLY / KEY SCALER
COLORSPACE
CONVERTER
KEY SCALER
20
20
ROUND
SELECT
LIMIT
ROUND
SELECT
LIMIT
20
ROUND
SELECT
LIMIT
20
ROUND
SELECT
LIMIT
3
3
COEFFICIENT
BANKS 0-9
CA
1-0
2
SYNC
HBLANK
DATAPASS
RESET
FLAG
GENERATOR
HF
0
HF
1
CLK
INPUT LOOK-UP-TABLE*
OUTPUT LOOK-UP-TABLE*
CONFIGURATION AND
CONTROL REGISTERS
NOTE:
NUMBERS IN REGISTERS INDICATE NUMBER OF PIPELINE DELAYS WHICH IS ALSO EQUIVALENT
TO NUMBER OF PIPELINE DELAYS THROUGH THAT PARTICULAR FUNCTIONAL BLOCK
*
UP TO ONE LOOK-UP-TABLE MAY BE USED PER DATA PATH. THE INHERENT DELAY THROUGH
THE LOOK-UP-TABLE IS TWO REGARDLESS OF WHETHER IT IS USED OR NOT.
13
13
13
13
LF3370
High-Definition Video Format Converter
4
03/13/2001LDS.3370-F
Video Imaging Products
DEVICES INCORPORATED
HBLANK -- Horizontal Blanking Control
HBLANK is used for data replacement
corresponding to user-selectable
blanking levels. A HIGH to LOW
transition resets the counter and the
HFx flags.This signal is latched on the
rising edge of CLK.
INBIAS
1-0
-- Input Bias Control
INBIAS
1-0
determines which of the
four user-programmable Input Bias
registers are used to sum with the
input data. These pins are latched on
the rising edge of CLK.
OUTBIAS
1-0
-- Output Bias Control
OUTBIAS
1-0
determines which of the
four user-programmable Output Bias
registers are used to sum with the
output data.These pins are latched on
the rising edge of CLK.
RSL
1-0
-- Round/Select/Limit Control
RSL
1-0
determines which of the user-
programmable Round/Select/Limit
registers (RSL registers) are used in
the RSL circuitry. A value of 00 on
RSL
1-0
selects RSL register 0. A value
of 01 selects RSL register 1 and so on.
RSL
1-0
is latched on the rising edge of
CLK.
OE -- Output Enable
When OE is LOW, W
12-0
, X
12-0
, Y
12-0
,
and Z
12-0
are enabled for output.
When OE is HIGH, W
12-0
, X
12-0
, Y
12-0
,
and Z
12-0
are placed in a high-
impedance state.
PAUSE -- LF Interface
TM
Pause
When PAUSE is HIGH, the LF3370
LF Interface
TM
loading sequence is
halted until PAUSE is returned to a
LOW state. This effectively allows
the user to load coefficients and
control registers at a slower rate than
the master clock. This pin is latched
SIGNAL DEFINITIONS
Power
V
CC
and GND
+3.3 V power supply. All power pins
must be connected.
Clock
CLK -- Master Clock
The rising edge of CLK strobes all
enabled registers. To guarantee data
integrity, a minimum of 25KHz must
be maintained.
Inputs
A
12-0
, B
12-0
, C
12-0,
D
12-0
-- Data Inputs
A
12-0
, B
12-0
, C
12-0
, and D
12-0
are the
13-bit registered data input ports.
Data is latched on the rising edge of
CLK.
CF
12-0
-- Coefficient Input
CF
12-0
is used to address and load
Colorspace/Key Scaler coefficient
banks, Round/Select/Limit registers,
and Configuration registers. Data
present on CF
12-0
is latched into the
LF Interface
TM
on the rising edge of
CLK when LD is LOW.
CA
1-0
-- Coefficient Address
CA
1-0
determines which of the four
user-programmable Colorspace/Key
Scaler Coefficients are used.
Outputs
W
12-0
, X
12-0
, Y
12-0
, Z
12-0
-- Data Outputs
W
12-0
, X
12-0
, Y
12-0
, and Z
12-0
are the
13-bit registered data output ports.
Outputs are updated on the rising
edge of CLK.
HF
1
/HF
0
-- HBlank Flags
HF
1
and HF
0
are two general purpose
flags used to indicate when a 20-bit
counter reaches its user-defined
terminal count; a HIGH to LOW
transition of HBLANK and/or RESET
will reset the flags.
Controls
LD -- Configuration Load
When LD is LOW, data on CF
12-0
is
latched into the LF3370 LF Interface
TM
on the rising edge of CLK. When LD
is HIGH, data is not loaded into
the LF Interface
TM
. When enabling
the LF Interface
TM
for data input, a
latched HIGH to LOW transition of
LD is required in order for the input
circuitry to function properly.
Therefore, LD must be set HIGH
immediately after power up to
ensure proper operation of the input
circuitry.
SYNC -- Synchronization for data alignment
SYNC control signal is required to
properly synchronize the input
demultiplexer, output multiplexer,
and halfband filters to the data
flowing through the LF3370. A
latched HIGH to LOW transition tells
the core which sample corresponds to
a Cb/Cr sample for proper de-multi-
plexing and multiplexing. This signal
will also synchronize the half-band
filters into a decimation/interpolation
sequence. This signal is latched on the
rising edge of CLK.
DATAPASS -- Datapass Mode
DATAPASS is used to place the
LF3370 in a mode of operation that
allows the user to pass data through
the core (Input/Output Bias Adders,
LUTs, Hafband Interpolator/
Decimator, Colorspace/Key Scaler)
without any processing. This signal is
latched on the rising edge of CLK.
Video Imaging Products
5
LF3370
High-Definition Video Format Converter
03/13/2001LDS.3370-F
DEVICES INCORPORATED
on the rising edge of CLK.
RESET -- Reset
RESET is used to reset all program-
mable flags and line up clock edges
during single muxed input or single
muxed output events. RESET is used
at power up or just after device
configuration. This pin is latched on
the rising edge of CLK.
LF3370 Device Initialization
This section explains how to initialize the
device for proper operation. It also serves as
a summary of all conditions that should be
considered before using the device or for
troubleshooting.
Configuration Register 0 and Configuration
Register 1 must be loaded before operation
of the device. If Core Bypassing is desired,
Configuration Register 2 must be loaded
before use. If use of the Half-Band Filters is
desired, at least one Half-Band Filter RSL
Register Set must be loaded and selected for
each Half-Band Filter.
If use of the Matrix Multiplier/Key Scaler is
desired, at least one Matrix Multiplier/Key
Scaler RSL Register Set and coefficient
address must be loaded and selected for
each channel. If use of the Input Bias Adder
is desired, at least one Input Bias Adder
Register must be loaded and selected before
use. If use of the Output Bias Adder is
desired, at least one Output Bias Adder
Register must be loaded and selected before
use. If use of the Look-Up Table is desired,
the Look-Up Table must be loaded before
use.
When using a single channel input or
output with interleaved video, SYNC and
RESET should be used for proper initializa-
tion as shown in Figure 5. If 12 bits or less
input data is desired, the input data should
be shifted so the MSBs are aligned.
Input Demultiplexer
The input demultiplexer section acts as a
buffer between the user's datapath and the
* Not all input/output combinations are valid. If single channel interleaved video
is used on either the input or output, the core clock will be running at CLK/2.
Thus the maximum input, output, and core data rate must be considered.
Input
Input Format*
Channel
4:4:4:4
4:2:2:4
4:2:2:4
4:2:2:4
A
12-0
R
Y
Y
Y/Cb/Cr
B
12-0
G
Cb
Cb/Cr
N/A
C
12-0
B
Cr
N/A
N/A
D
12-0
Key
Key
Key
Key
T
ABLE
1.
I
NPUT
/O
UTPUT
F
ORMATS
Output
Output Format*
Channel
4:4:4:4
4:2:2:4
4:2:2:4
4:2:2:4
W
12-0
R
Y
Y
Y/Cb/Cr
X
12-0
G
Cb
Cb/Cr
N/A
Y
12-0
B
Cr
N/A
N/A
Z
12-0
Key
Key
Key
Key
F
IGURE
3. I
NPUT
AND
O
UTPUT
F
ORMATS
12 11 10
2
1
0
2
0
(Sign)
2
1
2
2
2
10
2
11
2
12
Coefficient Data
12 11 10
2
1
0
2
12
(Sign)
2
11
2
10
2
2
2
1
2
0
12 11 10
2
1
0
2
12
(Sign)
2
11
2
10
2
2
2
1
2
0
Input Data
Output Data
INPUT BIAS ADDER/OUTPUT BIAS ADDER
MATRIX MULTIPLIER/KEY SCALER
F
19
F
18
F
17
F
2
F
1
F
0
2
15
(Sign)
2
14
2
13
2
2
2
3
2
4
F
19
F
18
F
17
F
2
F
1
F
0
2
13
(Sign)
2
12
2
11
2
4
2
5
2
6
*Matrix Multiplier Output
*Key Scaler Output
12 11 10
2
1
0
2
12
(Sign)
2
11
2
10
2
2
2
1
2
0
Input Data
*Format of Matrix Multiplier/Key Scaler ouput feeding the RSL Circuitry. F
19
-F
0
corresponds to 20 MSBs of which a
13-bit window can be selected from F
19
-F
4
.
HALF-BAND FILTER
**Filter Output (Non-Interpolate)
**Filter Output (Interpolate)
12 11 10
2
1
0
2
12
(Sign)
2
11
2
10
2
2
2
1
2
0
Input Data
*Format of Half-Band Filter ouput feeding the RSL Circuitry. F
19
-F
0
corresponds to 20 MSBs of which a
13-bit window can be selected from F
19
-F
4
(see Table 3).
F
19
F
18
F
17
F
2
F
1
F
0
2
12
(Sign)
2
11
2
10
2
5
2
6
2
7
F
19
F
18
F
17
F
2
F
1
F
0
2
13
(Sign)
2
12
2
11
2
4
2
5
2
6
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