QUADRATURE CLOCK CONVERTER
FEATURES:
x1, x2 and x4 mode selection
Up to 16 MHz output clock frequency
INDEX input and output
UP/DOWN indicator output
Programmable output clock pulse width
On-chip filtering of inputs for optical or
magnetic encoder applications.
TTL and CMOS compatible I/Os
+4.5V to +10.0V operation (V
DD
-V
SS
)
LS7082 (DIP); LS7082-S (SOIC ) - See Figure 1
INPUT/OUTPUT DESCRIPTION:
V
DD
(Pin 1)
Supply Voltage positive terminal.
INDX (Pin 2)
Encoder Index pulses are applied to this input.
RBIAS (Pin 3)
Input for external component connection. A resistor con-
nected between this input and V
SS
adjusts the output clock
pulse width (Tow). For proper operation, the output clock
pulse width must be less than or equal to the A,B pulse
separation (T
OW
T
PS)
.
V
SS
(Pin 4
)
Supply Voltage negative terminal.
A (Pin 5)
Quadrature Clock Input A. This input has a filter circuit to
validate input logic level and eliminate encoder dither.
x2 (Pin 8)
A low level applied to this input selects x2 mode of opera-
tion. See Table 1 for Mode Selection Truth Table and
Figure 2 for Input/Output timing relationship.
B (Pin 9)
Quadrature Clock Input B. This input has a filter circuit
identical to input A.
x4/x1 (Pin 10)
This input selects between x1 and x4 modes of operation.
See Table 1 for Mode Selection Truth Table and Figure 2
for Input/Output timing relationship.
UP/DN (Pin 11)
The count direction at any instant is indicated at this out-
put. An UP count direction is indicated by a high, and a
DOWN count direction is indicated by a low (See Figure 2).
DNCK (Pin 12)
This DOWN Clock output consists of low-going pulses gen-
erated when A input lags the B input (See Figure 2).
UPCK (Pin 13)
This UP Clock output consists of low-going pulses gener-
ated when A input leads the B input (See Figure 2).
INDX (Pin 14)
This output consists of low-going pulses generated by
clock transitions at the A input when INDX input is high and
B input is low (See Figure 2).
NOTE: All unused input pins must be tied to V
DD
or V
SS
.
DESCRIPTION:
The LS7082 is a monolithic CMOS silicon gate quadrature
clock converter. Quadrature clocks derived from optical or
magnetic encoders, when applied to the A and B Inputs of the
LS7082, are converted to strings of Up Clocks and Down
Clocks. Pulses derived from the Index Track of an encoder,
when applied to the INDX input, produce absolute position ref-
erence pulses which are synchronized to the Up Clocks and
Down Clocks. These outputs can be interfaced directly with
standard Up/Down counters for direction and position sensing
of the encoder.
October 2000
1
2
3
4
5
6
7
LS7082
INDX
UPCK
DNCK
U P / D N
x 4 / x 1
B
x2
V
DD
(+V)
INDX
RBIAS
V
SS
(-V)
A
NC
NC
14
13
12
11
8
9
10
FIGURE 1
PIN ASSIGNMENT - TOP VIEW
LSI
7082-100600-1
TABLE 1. MODE SELECTION TRUTH TABLE
x2 Input x4/x1 Input MODE
0
Don't Care
x2
1
0
x1
1
1
x4
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
LS7082
UL
A3800
ABSOLUTE MAXIMUM RATINGS
:
PARAMETER
SYMBOL
VALUE
UNITS
DC Supply Voltage
V
DD
- V
SS
11.0
V
Voltage at any input
V
IN
V
SS
-.3 to V
DD
+.3
V
Operating temperature T
A
0 to +70 C
Storage temperature T
STG
-55 to +150 C
DC ELECTRICAL CHARACTERISTICS:
(All voltages referenced to V
SS
, T
A
= 0C to 70C.)
PARAMETER
SYMBOL
MIN
MAX
UNITS
CONDITION
Supply voltage
V
DD
4.5
10.0
V
-
Supply current
I
DD
-
6.0
A
V
DD
= 10.0V, All
input frequencies = 0 Hz
RBIAS = 2M
x4/x1, x2, INDX Logic Low
V
IL
-
0.3V
DD
V
-
A,B Logic Low
V
IL
-
0.6
V
V
DD
= 4.5V
-
1.0
V
V
DD
= 9V
-
1.1
V
V
DD
= 10.0V
x4/x1, x2, INDX Logic High
V
IH
0.7V
DD
-
V
-
A,B Logic High
V
IH
3.1
-
V
V
DD
= 4.5V
5.0
-
V
V
DD
= 9V
5.6
-
V
V
DD
= 10.0V
ALL OUTPUTS:
Sink Current
I
OL
1.75
-
mA
V
DD
= 4.5V
V
OL
= 0.4V
5.0
-
mA
V
DD
= 9V
5.7
-
mA
V
DD
= 10.0V
Source Current
I
OH
1.0
-
mA
V
DD
= 4.5V
V
OH
= V
DD
- 0.5V
2.5
-
mA
V
DD
= 9V
3.0
-
mA
V
DD
= 10.0V
TRANSIENT CHARACTERISTICS:
(T
A
= 0C to 70C)
PARAMETER
SYMBOL
MIN
MAX
UNITS
CONDITION
A,B inputs:
Validation Delay
Tv
D
-
85
ns
V
DD
= 10.0V
-
100
ns
V
DD
= 9V
-
160
ns
V
DD
= 4.5V
A,B inputs:
Pulse Width
T
PW
T
VD
+T
OW
Infinite
ns
-
A to B or B to A
Phase Delay
T
PS
T
OW
Infinite
ns
-
1
A,B frequency
f
A,B
-
2T
PW
Hz
-
Input to Output Delay
T
DS
-
120
ns
V
DD
= 10.0V
-
150
ns
V
DD
= 9V
-
235
ns
V
DD
= 4.5V
Includes input
validation delay
Output Clock Pulse Width
T
OW
50
-
ns
See Fig. 4 & 5
7082-100600-2
Figure 4. Tow vs RBIAS, K
V
DD
=5V
V
DD
=9V
V
DD
=10.0V
100
200
300
400
500
250
500
750
1000
1250
1500
OUTPUT CLOCK PULSE WIDTH, Tow, ns
E N C O D E R
A CLOCK
B CLOCK
INDEX
5
9
2
13
12
14
8
10
1
3
4
R
B
UPCK
DNCK
R E S E T
x2
x 4 / x 1
V
DD
A
B
RBIAS
V
SS
UPCK
DNCK
INDX
FIGURE 6. A TYPICAL APPLICATION IN x4 MODE
V
SS
V
DD
L S 7 0 8 2
5
4
14
16
8
+V
4 0 1 9 3
+V
INDX
V
DD
=5V
V
DD
=9V
V
DD
=10.0V
25
30
20
15
10
5
2
4
6
8
10
12
Figure 5. Tow vs RBIAS, M
OUTPUT CLOCK PULSE WIDTH, Tow, s
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
7082-100100-4
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