PROGRAMMABLE DIGITAL DELAY TIMER
July 2003
FEATURES:
Eight timing ranges Four modes
RC controlled on-chip oscillator
Power-On-Reset (POR)
Reset input for delay abort
Complementary outputs
Delay-in-Progress Indicator output
LS7213 (DIP), LS7213-S (SOIC) - See Figure 1
APPLICATIONS
Time delay relays for HVAC equipment and industrial controls.
DESCRIPTION
The LS7213 is a CMOS integrated circuit for generating pro-
grammable time-delays. The delay is initiated by a logic transition
at the Trigger input and the completion of the delay is marked by a
change of status at the Out1 and the Out2 outputs. Three inputs,
D1, D2 and D3 select 1-of-8 scale factors, s. The delay, td is re-
lated to s by the expression, td = s/frc, where frc is the frequency at
the RC input produced by an internal oscillator. An external re-
sistor-capacitor pair connected to the RC pin controls the oscillator
frequency. There are four modes of operation selected by inputs A
and B. The operating modes are:
On-Delay (OND), Off-Delay (OFD), Dual-Delay (DLD) and One-
Shot(OST). These modes are described below:
On-Delay (OND) Mode
A positive transition at the Trigger input starts the on-delay timer. At
the end of the delay Out1 switches low and Out2 switches high. A
negative transition at the Trigger input immediately aborts any on-
delay in progress. If the Trigger input is switched low, Out1 if low
will switch high and Out2 if high will switch low without delay. The
states of Out2 in the preceding description applies only if Flashen
input is low at the time of the Trigger input transition. See the Out2
pin section for a complete description.
Off-Delay (OFD) Mode
A negative transition at the Trigger input starts the off-delay timer.
At the end of the delay Out1 switches high and Out2 switches low.
A positive transition at the Trigger input immediately aborts any off-
delay in progress. If the Trigger input is switched high, Out1 if high
will switch low and Out2 if low will switch high without delay. The
states of Out2 in the preceding description applies only if Flashen
input is low at the time of the Trigger input transition. See the Out2
pin section for a complete description.
Dual-Delay (DLD) Mode
In Dual-Delay mode, the delay is generated for both positive and
negative transitions at the Trigger input. A positive transition at the
Trigger input starts the on-delay timer and aborts any off-delay tim-
ing in progress. At the end of the delay Out1 switches low and Out2
switches high. A negative transition at the Trigger input starts the
off-delay timer and aborts any on-delay timing in progress. At the
end of the delay Out1 switches high and Out2 switches low. The
states of Out2 in the preceding description applies only if Flashen
input is low at the time of the Trigger input transition. See the Out2
pin section for a complete description.
One-Shot (OST) Mode
A positive transition at the Trigger input causes Out1 to switch
low and Out2 to switch high immediately and start the one-shot
delay timer. At the end of the delay Out1 switches high and Out2
switches low. Thus in effect, a positive transition at the Trigger in-
put produces a negative pulse at Out1 and a positive pulse at
Out2. The one-shot delay timer is restarted with every positive
trigger transition, thus rendering the Out1 and Out2 pulse-widths
stretchable to any duration by periodic re-trigger. A negative tran-
sition at the Trigger input has no effect. The states of Out2 in the
preceding description applies only if Flashen input is low at the
time of the Trigger input transition. See the Out2 pin section for a
complete description.
INPUTS/OUTPUTS
Following is a description of all the input/output pins and their
functions.
Delay Select Inputs: D1, D2, D3 (Pin3, Pin2, Pin1)
The logic states applied to these three inputs enable the user to
select a scale factor, s, for generating a delay, td, fromTrigger in-
put to Out1/Out2 outputs according to Table1. The delay is given
by the expression:
td = s/frc,
where, s is the scale factor, and frc is the oscillator frequency at
the RC input. The sample delays in Table1 are based on an os-
cillator frequency, frc = 10kHz.
TABLE 1. Delay Selection
D3 D2 D1 s td (= s/frc)
0 0 0 1x10
3
0.1sec
0 0 1 1x10
4
1.0sec
0 1 0 1x10
5
10.0sec
0 1 1 60x10
3
0.1min
1 0 0 60x10
4
1.0min
1 0 1 60x10
5
10.0min
1 1 0 3600x10
3
0.1hr
1 1 1 3600x10
4
1.0hr
D1, D2 and D3 inputs have internal pull-down resistors
7213-071403-1
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
LS7213
1
2
3
4
5
6
7
14
LSI
13
12
11
10
9
8
LS7213
D3
D2
D1
A
B
FLASHEN
V
DD
(+V)
V
SS
(-V)
OUT1
OUT2
RESET
RC
CAP
TRIGGER
FIGURE 1
PIN ASSIGNMENT
TOP VIEW
UL
A3800
Mode Select Inputs: A, B (Pin 5, Pin 6)
The four operating modes are selected by inputs A and B
according to Table 2.
TABLE 2. Mode Selection
A B Mode
0 0 On-Delay (OND)
0 1 Off-Delay (OFD)
1 0 Dual-Delay (DLD)
1 1 One-Shot (OST)
Inputs A and B have internal pull-down resistors.
Driver Outputs: Out1, Out2 (Pin 13, Pin 12)
Out1 is an output for driving DC loads requiring high current sink,
such as relays, power transistors, etc. In steady-state condition
Out1, with the exception of one-shot mode, is always inverse in
polarity with respect to the Trigger input. Depending on the oper-
ating mode, the steady-state condition is reached immediately or
after a specified delay following a change of state at the Trigger
input. In one-shot mode, Out1 is always at logic high in the
steady state, independent of the logic state of the Trigger input.
Out2 operates in two different modes depending on the state of
the Flashen input.
If Flashen is at logic low then:
Out2 operates exactly as Out1 but with inverse polarity. In this
mode, Out2 is an output for driving DC loads requiring high cur-
rent source, such as relays, power transistors, etc. In steady-
state condition Out2, with the exception of one-shot mode, is al-
ways at the same polarity as the Trigger input. Depending on the
operating mode, the steady-state condition is reached immedi-
ately or after a specified delay following a change of state at the
Trigger input. In one-shot mode Out2 is always at logic low in the
steady state, independent of the logic state of the Trigger input.
If Flashen is at logic high then:
Out2 operates as a delay-in-progress indicator by generating pe-
riodic positive pulses during a delay timing. The pulse-rate, fpf
and the pulse-width tpf at Out2 is controlled by an internal os-
cillator whose frequency, fcf, is set by a capacitor connected to
the Cap input. fpf and fcf are related by the following expres-
sions:
fpf = 20/fcf,
for scale factors 1x10
3
and 1x10
4
and
fpf = 100/fcf,
for all other scale factors.
The pulse-width, tpf for both pulse-rates is given by:
tpf = 2/fcf
At the end of timeout, Out2 returns to logic low with the cessation
of pulses.
Timer Start Input: Trigger (Pin 8)
Any logic transition at the Trigger input, positive or negative caus-
es the outputs Out1 and Out2 to switch with or without delay, de-
pending on the operating mode.
Any transition of the Trigger input also causes the logic states of
the following inputs to be strobed into internal latches: A, B, D1,
D2, D3 and Flashen. This prevents any changes at any of these
inputs from disrupting the timer when a timeout is in progress.
See the description of modes on Page1 and Out1, Out2 section
on Page 2 for a complete description of the Trigger input.
TheTrigger input has an internal pull-down resistor.
Flash Enable Input: Flashen (Pin 4)
The Flashen input modifies the operation of Out2 to function in
one of two modes.
When Flashen = 0, Out2 functions exactly as Out1 but with in-
verse polarity from Out1. When Flashen = 1, Out2 functions as a
flashing delay-in-progress indicator. In this mode periodic positive
pulses are generated at Out2 during a delay timing which can be
used to produce a flashing LED display for user feedback. For a
complete description see Out2 section on Page 2. The Fashen
input has an internal pull-down resistor.
Master Clear Input: Reset (Pin 11)
When Reset is brought to logic high, all timing functions are
aborted, the timer is cleared, Out1 is forced high and Out2 is
forced low. Switching the Reset input low causes the mode select
inputs, the delay select inputs, the Flashen input and the Trigger
input to be sampled by internal logic. Following this, any in-
consistencies between the Trigger input and the Out1 and Out2
outputs are resolved and the steady state is reached with or with-
out delay based on the status of the mode select inputs. For ex-
ample, if the Trigger input is high, the Flashen input is low and
the mode is off-delay when the Reset input is switched from high
to low, Out1 and Out2 will immediately be switched low and high,
respectively, from its forced reset condition. In this example if the
mode is on-delay instead of off-delay, then Out1 and Out2 will be
switched after the completion of the programmed delay td.
It should be noted here that the states of Out1 and Out2 in the
reset condition and One-Shot mode steady state condition are
the same namely, Out1 = 1 and Out2 = 0. Because of this, in
one-shot mode, no change in Out1 and Out2 takes place when
the Reset input is switched low, irrespective of the status of the
Trigger input. The Reset input has an internal pull-down resistor
.
NOTE: A POR circuit (See Fig. 2) generates a reset upon power
up that produces the same conditions described for Reset
(Pin 11).
Timer Oscillator Input: RC (Pin 10)
A resistor-capacitor pair connected to the RC input serves as the
basic timing element for the delay timer oscillator.
The oscillator frequency is given by the expression:
frc = 1/RC,
where R and C are the resistor and the capacitor values at the
RC input. Chip to chip tolerance of frc is + 5% for V
DD
= 3V to 5V.
The delay, td, is given by the expression:
td = s/frc,
where s is the scale factor selected by inputs D1, D2 and D3.
Flash Oscillator Input: Cap (Pin 9)
A capacitor, C, connected from the Cap input to ground regulates
an internal flash oscillator frequency according to the relation:
fcf = (k/C)x10
-6
where k is a V
DD
dependent constant ranging in value between
2.1 at V
DD
= 3V to 4.8 at V
DD
= 5V. The flash oscillator frequency
controls the pulse-rate, fpf and the pulse width, tpf at Out2 in
flash mode according to the following relationships:
fpf = 20/fcf,
for scale factors 1x10
3
and 1x10
4
and
fpf = 100/fcf,
for all other scale factors; and for the pulse-width,
tpf = 2/fcf, for all scale factors.
Chip to chip tolerance of fcf is + 10% at fixed V
DD
.
Power Supplies V
DD
, Vss (Pin 14, Pin 7)
V
DD
is the power supply positive terminal and Vss is the negative
or ground terminal.
7213-071403-2
7213-012703-4
LATCH
LATCH
LATCH
LATCH
LATCH
D3
D2
D1
RC
A
TRIGGER
RANGE
D E C O D E R
TIMER
OSC
CONTROL LOGIC
POR
GENERATOR
O U T P U T
DRIVER
O U T 1
O U T 2
LATCH
B
LATCH
F L A S H E N
FIGURE 2. LS7213 BLOCK DIAGRAM
1
2
3
10
4
5
6
8
+V
14
V
DD
-V
7
Vss
O U T P U T
DRIVER
OSC
CAP
9
13
12
R E S E T
11
A
B
D
C
E
F
G
H
OUT1(DLD)
O U T 1 ( O F D )
O U T 1 ( O N D )
O U T 1 ( O S T )
R E S E T
TRIG
A. Turn-on delay in OND and DLD modes; Pulse-width in OST mode.
B. Turn-off delay in OFD and DLD modes.
C. Pulse-width extended by re-trigger in OST mode. No effect in
OND and DLD modes because TRIG switches back low before
turn-on delay has timed out.
D. Turn-off delay in OFD mode.
FIGURE 3.
MODE ILLUSTRATION
WITH TRIG, OUT1 AND RESET
1
2
3
4
5
7
6
D3
D2
D1
A
B
F L A S H E N
Vss(-V)
V
DD
(+V)
14
O U T 1
13
O U T 2
12
R E S E T
11
RC
10
CAP
9
8
RESET INPUT
FIGURE 4. TYPICAL APPLICATION WITH OUT1 AS RELAY
DRIVE AND OUT2 AS FLASHER
TRIGGER INPUT
L S 7 2 1 3
+5V
LED
C2
C1
3 0 0
R1
R2
E. Turn-on delay in OND and DLD modes; pulse-width in OST mode.
F. No effect in OND, OFD and DLD modes because of Trig's
switching back to opposite levels.
G. Time-out aborted and OUT1 forced high by RESET.
H. After the removal of RESET, OUT1 switches to the inverse polarity
of TRIG immediately (OFD) or after the timeout (OND, DLD).
No effect in OST.
The table below shows the delays obtained with the
following components R1 = 56k
, R2 = 500k
and
C2 = 0.002F. At any scale factor, the delay changes
from minimum to maximum as the potentiometer, R2
is varied from minimum to maximum.
D3 D2 D1 TIMING RANGE
0 0 0 0.1 sec - 1 sec.
0 0 1 1 sec. - 10 sec.
0 1 0 10 sec - 100 sec.
0 1 1 0.1 min. to 1 min.
1 0 0 1 min. - 10 min
1 0 1 10 min. - 100 min.
1 1 0 0.1 hr. - 1 hr.
1 1 1 1 hr. - 10 hr.
C1 = 0.22F, produces flash pulses of 0.1 sec
duration at Out2
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